8 Bit Computer

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Rensselaer Polytechnic Institute

Advanced Computer Hardware Design ECSE 4780

Computer Architecture Prototyping ECSE 6700

Design of an 8-bit bus-oriented computer

Written By Sung-Gon Lee

Rev. B Modified By Jon Riehl

A. Objectives

This laboratory assignment is an introduction to a complete 8-bit bus-oriented computer

design using Alteras Quartus software. Students are expected to construct and to

implement McCallas 8-bit computer on the Altera FPGA Hardware. Possible use of a logic

analyzer may be required to debug when implementing.

B. Preparatory reading and other References

1. Thomas R. McCalla. Digital Logic and Computer Design, Ch 12 (Macmillan,1992)

2. Thomas R. McCalla. Digital Logic and Computer Design, Ch 14 (Macmillan,1992)

3. Altera Quartus II Tutorial, http://www2.uic.edu/~wahmad1/quartus_ii_tutorial.pdf4. Manual of Logic Analyzer

C. General Description of McCallas 8-bit bus-oriented computer

As described in McCallas book on Ch 12, a simple computer can be divided into two major

components: a processor and an I/O subsystem. The Input to a system can be realized by an

external HEXKEY switch or by VHDL code programmed for a program-load facility. The

processor can be also divided into two major modules: a CPU and a Memory Subsystem. In

the Memory Subsystem, a RAM is required to store a specified set of instructions. There

are various ways to design a RAM in Xinlix software. Even though there is no limit to

choosing a size of the RAM, the size may affect implementing the system onto a FPGA chip

since the RAM normally consumes a large amount of resources in the chip. This may result

in timing conflicts among the control signals when routing. Then, the CPU is composed of

a Data Path Subsystem and a Control Unit Subsystem. The Data Path Subsystem is also

known as Arithmetic Logic Unit (ALU), whose main job is to add and subtract two binary

words stored in Registers A and B. The Control Unit Subsystem fetches program instruction

from a single bus and generates logic control signals that are used in other modules such as

RPI


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Data Path Subsystem and Memory Subsystem. The hierarchical view of the McCallas

system is illustrated in .

Hierarchical view of a computer system

D. Functional Descriptions of each subsystem

1. I/O Subsystem

This Subsystem is necessary to load a given set of instructions into a memory so that a

computer executes each instruction every cycle. It is possible to install a VHDL coded

STARTUP module to perform this function, but it is more ideal to construct a pre-

programmed RAM module using the MegaWizard plug-in manager. This option will be

described in the memory subsystem section.

When implementing your design into an Altera FPGA board, you need to add IPAD or

OPAD to interface your software design with an external signal for clocking. You may

use a function generator as an external clock and use the seven-segment LED display

attached to the board to verify your output. Pin layouts for the LED display will be

provided in lab.

2. Memory Subsystem

There are various ways to design a memory subsystem using Altera. A memory

subsystem can have a RAM or a ROM which holds a set of instructions such as LOAD,

ADD, SUB, STORE etc. For a real computer system simulation, it is possible to upload

instructions into the memory before running the entire system. To accomplish this, you

may create a HDL coded module, which loads the instructions into a RAM by giving

Computer

CPU

I/O SubsystemData Path

Subsystem (ALU)

Memory

Subsystem

Control Unit

Subsystem

Processor


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LD_MA and LD_MW signals at an appropriate time. However, it is cumbersome work

to design a system with the HDL editor since it is harder to debug later on. Hence, a

pre-programmed RAM module using MegaWizard plug-in manager is ideal for the

McCallas 8-bit bus-oriented computer. The MegaWizard plug-in manager is a

graphical interactive tool that a designer can create high-level modules such as

accumulators, multiplexers, and counters. It is located under the tool option in the

schematic editor. The following section describes how to use the MegaWizard plug-in

manager.

MegaWizard Plug-In Manager

1. Select MegaWizard Plug-In Manager in the tools menu.2. Select the option to Create a new custom megafunction variation and hit Next.3. Select LP_RAM_DQ from the megafunction list (under the storage directory).4. Make sure the device family is set to FLEX10K, and select the HDL of your

choice for the output file. Modify the output file name as desired

(xxx.vhd for VHDL outputs). Click next.

5. Set Data Bus Width to 8 (this is an 8-bit bus-oriented computer).6. Select the Memory Depth: 32, 64, 128, 256, etc. and click next.

Altera MegaWizard Plug-In Manager for steps 5 and 6

7. Select which ports should be registered (most likely you only want the two inputports to be registered) and hit next.

8. Select yes to specify a file for pre-loaded memory content data. Select the


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included init.hex file (you can modify this later). Click next.

9. Finally, select all of the desired output files (the bsf file is recommended) andclick finish. You may now use your memory block the same as any other chip.

shows the .hex file editor, which allows you to insert a set of instructions.Make sure that the word size is 8 when you open the .hex file. Each box in the

window holds an instruction, so that there are eight instructions per line.

.hex File Window

The following segment of data must be inserted after DATA field in the Data Section.

A binary number representation has been used to describe the memory addresses and

data values. The four digits on the left field represent 4-bit memory addresses. Ifyou look at the schematic of the memory subsystem, you can easily find that I used

4-bit bus going into RAM module. The eight bits on the right represent data value.

For example, the first data value is composed of 3-bit opcode and 5-bit direct address

field. Only if you use the RAM with depth 32 and width 8, your memory

subsystem must utilize 5-bit direct address field. However, since I use RAM16x8, I

am only required to have four bits for the direct memory address. The instruction

LDA executes loading the content stored in the memory address 01000 into Register

A. One thing noticeable in filling out the data values is that you can have two data

fields, 00000110 and 00000010, given a specified memory address as shown in thelast line. In other words, you can specify the memory address for the first data

value, and the value followed by comma is stored in the next memory address 10001

in this example. This is only a simple set of instructions that have been used for

demonstrating a simple 8-bit bus-oriented computer. Instructions that you can add

into pre-designed computer are illustrated in from the McCalla text.


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Instruction Repertoire

3. Control Unit Subsystem

A control unit subsystem is composed of a next-state generator and an output decoder.

The next-state generator generates a process control algorithm for the next-state table and

the output decoder generates the logic for data path control signals. A simple computer

uses 3-bit opcode to develop 8 instructions using a decoder. It is not required to design a

complicted 8-bit computer, but if you want to add more than 8 instructions, you may have

to use more bits for the opcode. A control unit subsystem traces the control flow for

each instruction and can be constructed by a help of an instruction-time (or p-term) event

table as shown in . You dont have to create a new table for your instructions

but just manipulate them if you add more instructions.


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p-term event table

p-term/control point activation table

An careful examination of the instruction (p-term) event table to identify each control

point leads to the construction of a p-term/control point activation table, as shown in

. You can verify the entries by tracing each instructions micro-operations

through the data path in . This figure illustrates the memory and data path of

a bus-oriented computer. A 3-state buffer interfaces the shared bus (Z-bus) with data

path and memory.


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4. Data Path Subsystem (ALU)

A data path subsystem is a computing device that supports a variety of arithmetic and

logic operations. A simple computer can add and subtract by using AND and XOR

operations, but is not limited to complementing, incrementing and negating the stable

value stored in the Register A. You may use two parallel 4-bit adders to perform this

operation or just use an 8-bit adder for your convenience. A sample data path subsystem

is drawn at the end of this lab. As implementing data path subsystem with control unit

subsystem, a CPU has been realized. A CPU and a memory subsystem realize a stored-

program computer processor which fetches an instruction from memory, decodes and

executes each program instruction. A step-by-step procedure to accomplish the fetch is

done by incrementing a program counter that traces a memory address from zero.

5. Program Counter (PC)

A program counter is an incrementing device for a step-by-step procedure to fetch an

instruction or an address in each instruction cycle. In the McCallas book, the program

counter is designed with two parallel 4-bit counters used to fetch an instruction from

memory address 00H (Hex). The program counter must be set to zero before the clock

starts running. Therefore, as the clock starts, it tries to fetch an instruction stored in

memory address, 00H, and the three bits of the instruction will be fetched onto an output

decoder in control unit subsystem to generate control signals to drive the data path

subsystem. This program counter macro takes four major inputs: DATA, LD_PC, PCO

and T1.

T1 The program counter is incremented every T1 in the instruction cycle.

PC Controls the program counter output to the Z-bus.

LD_PC Loads the PC with the value of 8-bit DATA when JMP instruction

DATA 8-bit wide address fetched from memory by JMP instruction

JMP is an absolute jump instruction which directs the process control to a specified

address without incrementing the program counter. It is different from BRA instruction

since the BRA instruction is a conditional jump instruction, and thus you are required to

design a simple program counter to perform both incrementing a PC by one when a

normal operation and jumping to a specified address when JMP or BRA instruction.

For detailed information on the structure of a computer system, read carefully on Ch. 12

and Ch.14 of the McCallas Digital Logic and Hardware Design.


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E. Design Requirements

It is a good practice to divide the system into several subsystems depending on their functions.

Once each of these subsystems is constructed, a computer can be assembled by a bottom-up

procedure implementation. Each subsystem can be built as a macro with a Quartus II

schematic editor. Also, the Quartus II Student Edition supports designing a system with

VHDL code. For example, the control unit subsystem can be built by a sequence of micro-

operations at specific times within an instruction cycle. The micro-operations are well

described in Ch 14 with an instruction-time event table. This table is very useful to

understand the ways that each control signal is constructed with when processing each

instruction. Each macro can be verified by a functional simulation using an example set of

input.

The objective of this lab is to design a simple 8-bit bus-oriented computer as described in

McCallas book. This lab provides basic structures of system and guides you to follow the

step-by-step procedures. The advanced objective of this lab is to modify the simple

computer you have initially designed by adding more instructions. This requires some

changes in the schematic of Control Unit subsystem. Furthermore, you may need to re-

design the RAM to hold more instructions. The step-by-step procedures to accomplish your

design implementation are described in the section, Design with Altera Foundation Series 2.1i.

After you have completely implemented your design onto Altera FPGA board, you are

required to change your system design with extended capability as described in .

Unlike the instructions for a simple computer, this table includes additional types of

instructions in the basic categories. The additional instructions include subroutine jump,

jump indirect, multiply and divide, and conditional branch instructions. This type of design

requires a different cycle period for each instruction, i.e. another D-Flip Flop to generate an

additional time T4 in Ring Counter Clock.


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Instructions Table with extended capability

F. Summary of an 8-bit bus-oriented computer

The individual operation involved in fetching, decoding, and executing an instruction is

referred to as a micro-operation. The execution of each operation requires a finite amount

of time, which is one instruction cycle. A memory read operation is initiated at the time T0,

and causes an addressed memory location to be read out onto the bus after some propagation

delays (propagation delay must be carefully considered when doing verification!). The

processing (fetch, decode, execute) of each instruction is accomplished in the next cycle, T1.

The 3-bit opcode is sent to an output decoder in the control unit subsystem. The 5-bit direct

address field is used to read out the content stored in that address and the program counter is

automatically incremented to fetch the next instruction for the subsequent operation.

Depending on the instruction, the addressed memory puts out the content onto the Z-bus and

other module such as Data path subsystem is ready to load the value that exists in the bus at

time T2. For example, the addressed value existing in the bus is loaded into Register B for

addition or subtraction. When a simple arithmetic operation is executed, the resulting

output is placed into Register A at time T3. The instruction execution for a simple 8-bit

computer is completed within four clock cycles. More complicated system may require five

clock cycles for an instruction cycle. An example of timing diagram for an instruction cycle

is illustrated in .


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Timing Diagram for a simple computer

The McCallas computer utilizes a shared bus structure and devices with 3-state outputs to

make the design of digital system much simpler. Since the computer is designed with a

single Z-bus structure, a bus conflict arises when more than one bus driver tries to drive the

bus at the same time. Since more than one module feeds the bus, each device driving the

bus must be interfaced by a 3-state buffer. This would functionally prevent bus contention

from being taken place among devices feeding the bus. However, you may still encounter a

bus conflict error when you verify the system after implementation in Altera. For this kind

of error, you need to come out with a distinctive logic to ensure that no two devices feed the

bus at the same time.

G. Design with Altera Quartus II

1. Divide a computer into subsystems2. Design each subsystem as a Macro: Datapath, Control unit, Memory subsystems3. Draw a schematic for each subsystem or use the HDL editor4. Test each macro with the Simulator tool (you need to supply a set of input to each

macro)

5. Once all the subsystems work properly, then assemble them as one system6. Test the entire system in the Simulator. Make sure that all the macros or schematics

in the project you created are ACTIVE. For example, if you design a subsystem

with the HDL Editor, it might not have an updated Netlist. You will need to update

the HDL macro before you simulate it.


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3. Postlab (20% of final grade) Due Friday of Week 8 (before Spring Break)

1. Complete the modified McCalla machine (with all students instructions and BRA0).

2. Display Register As value on the seven segment display on the FPGA.

3. Show complete instruction sets and code.

4. Write up a final report including detailed design functionality, debugging process.

You should also include the schematics/HDL files and a functional waveform.

Grading will be based on both functionality and students knowledge of the design.

A separate report is required by each team member.

5. Grading Breakdown for postlab:

i. Describe your design in detail, including each subsystem (30%)

ii. Debugging Issues (10%)

iii. Schematics (10%)

iv. Functional Waveform (20%)

v. Timing Diagram (10%)

vi. Final Implementation on FPGA as verified by TA (20%)

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8 Bit Computer