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741 OPAMP POLE/ZERO
ANALYSIS
Analog Electronics Winter 1390 | SUT25761
Siavash Kananian ©
u741schematic
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Simplified, Conceptual Schematic
Diagram of the 741 Op Amp
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Multicollector Lateral PNP
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Simplified Schematic of the 741 Op
Amp with Idealized Biasing
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Bias circuitry
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Input Stage Biasing of the 741 Op Amp
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Darlington Gain Stage Biasing
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Output Stage Biasing of the 741 Op Amp
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Siavash Kananian ©
Freq. Response
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Pole @ node 14
A 30pF cap. Is shunted with node 14
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Parasitic capacitance between nodes 5 & 6
A 13pF cap. is placed between nodes 5 & 6
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Output From HSPICE
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Pole at node 7
A 10pF cap. is shunted with node 7.
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Pole @ node 9
A 100pF cap. is shunted with node 9
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