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Multi-Cycle MIPS

Implementation

Ellen Spertus

MCS 111November 4, 2003

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ComparisonSingle-cycle Each instruction

takes one clockcycle.

There is one set ofcontrol signalsforeach instruction.

The clock period isthe length of theslowest instruction.

Multi-cycle Each instruction

takes multiple clockcycles.

There is one set ofcontrol signals foreach cycle of eachinstruction.

The clock period isthe length of theslowest stage.

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Single-cycle datapath

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Sample program

Assembly code:top: add $r1, $r2, $r3

sw $r5, 0x3000($r2)beq $r2, $r5, endj top

end:

Machine code:4000: add $r1, $r2, $r3

4004: sw $r5, 0x3000($r2)4008: beq $r2, $r5,_____400C: j____

op (6 bits) target address (26 bits)

000010 00 0000 0000 0000 0001 0000 0000

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add$r1, $r2, $r3

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Instruction Fetch Register Read ALU Register write

# Inst. Reg = Mem[PC]IorD = 0MemRead = 1IRWrite = 1# PC = PC + 4

ALUSrcA = 0ALUSrcB = 01ALUOp = add

PCSource = 00PCWrite = 1

#A = Reg[IR[25-21]]# B = Reg[IR[20-16]]

#ALUOut = A op BALUOp = functALUSrcA = 1ALUSrcB = 00

# Reg[IR[15-11] = ALUOutRegDst = 1RegWrite = 1MemToReg = 0

Multi-cycle datapath

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How to produce control bits?

Single-cycle

Input: opcode bits

Output: control bits

Multi-cycle

Input: opcode bits, cycle

Output: control bits

op2 op1 op0 RegDst

r-type 0 0 0 1lw 0 1 1 0sw 0 1 1 xbeq 1 0 0 x

(I dropped op5, op4, and op3 because theyre not needed for

the MIPS subset were examining.)

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Multi-cycle truth table (1)

op2 op1 op0 cyc1 cyc0 RegDst MemRead MemWrite

r-type 0 0 0 0 0

r-type 0 0 0 0 1

r-type 0 0 0 1 0

r-type 0 0 0 1 1

Instruction Fetch Register Read ALU Register write

# Inst. Reg = Mem[PC]IorD = 0

MemRead = 1IRWrite = 1# PC = PC + 4

ALUSrcA = 0

ALUSrcB = 01ALUOp = add


#A = Reg[IR[25-21]]# B = Reg[IR[20-16]]

#ALUOut = A op BALUOp = funct

ALUSrcA = 1ALUSrcB = 00

# Reg[IR[15-11] = ALUOutRegDst = 1

RegWrite = 1MemToReg = 0

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sw $r5, 0x3000($r2)

5

2

3000

Instruction Fetch 00 Register Read 01 ALU 10 Memory write 11


ALUSrcA = 0ALUSrcB = 1ALUOp = add


#A = Reg[IR[25-21]]# B = Reg[IR[20-16]]

(Assume that $r2=2 and$r5=5.)

#ALUOut = A plus immedALUSrcA =ALUSrcB =ALUOp =

# Mem[ALUOut] = BIorD =MemWrite =

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Multi-cycle truth table (2)

op2 op1 op0 cyc1 cyc0 RegDst MemRead MemWriter-type 0 0 0 0 0r-type 0 0 0 0 1r-type 0 0 0 1 0r-type 0 0 0 1 1

sw 0 1 1 0 0sw 0 1 1 0 1sw 0 1 1 1 0sw 0 1 1 1 1

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Big picture

Can we add a counter that keeps trackof what cycle were on?

Can we come up with a booleanfunction to convert from (opcode, cycle)to control bits?

Consequence:

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Datapath with cycle counter

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beq$r2, $r5, -3

5

2

3000

Instruction Fetch 00 Register Read 01 ALU 10


ALUSrcA = 0ALUSrcB = 1ALUOp = addPCSource = 0PCWrite = 1

#A = Reg[IR[25-21]]# B = Reg[IR[20-16]]

# Compute branch targetALUOp =ALUSrcA =ALUSrcB =

#ALUOut = A-BALUOp =ALUSrcA =ALUSrcB =

# If equal, PC gets new valuePCSource =PCWrite =PCWriteCond =

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j 0x4000

1000

Instruction Fetch 00 Write PC 01

(Same as for others) PCSource =PCWrite =

op (6 bits) target address (26 bits)

000010 00 0000 0000 0000 0001 0000 0000

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Details I ignored

We actually need 5 cycles (and __ bitsto represent them) for load-word.

I didnt always show the value ofdeasserted signals (such as RegWrite).

To simplify logic, the second cyclealways computes the branch target

address, even if it is not needed (e.g.,for r-type instructions).

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Actual implementation

While a giant truth table like I describedwould work, thats not how its done inpractice.

The book describes using a finite stateautomaton (although thats not veryefficient either).

The actual implementation is withmicrocode.

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FSA big picture

current state

data input

new state

actions

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Alternative: microcode

Each microinstruction consists of a setof control signals

Every machine instruction (e.g., )leads to the execution of severalmicroinstructions

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Microcode controller (fig. 5.47)

Microprogram counter

Address select logic

Adder

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Input

Datapathcontrol

outputs

Microcodestorage

Inputs from instruction

register opcode field

Outputs

Sequencing

control

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Levels of instructions

MIPS assembly language instructions Written by assembly language programmer

Example:

MIPS machine language instructions Created by assembler

Example:

MIPS microinstruction Created by architect

Example:

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