7.13001330_high Throughput Lithography_Semicon Taiwan 2011

8/3/2019 7.13001330_high Throughput Lithography_Semicon Taiwan 2011

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High Throughput Lithography andBonding Technology forLED Manufacturing

Markus Wimplinger, EV GroupCorporate Technology Development & IP Director


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Outline

Introduction EVG

EVG solutions for HB-LED manufacturing High-throughput lithography for HB-LEDs

Wafer-bonding technology for vertical LEDs Summary


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EV Group (EVG) is a global supplier of Wafer Bonders Aligners Coaters / Developers Temporary Bonders / Debonders

(Laminator)

Cleaners Inspection Systems

EV Group (EVG) is a global supplier to

Advanced Packaging, 3D Interconnect MEMS (MicroElectroMechanical Systems) SOI (Silicon-On-Insulator) Compound Semiconductor and Silicon based Power Devices

Nanotechnology

EV Group holds the dominant share of the market for wafer bondingequipment (especially SOI bonding) and is a leader in lithography for

advanced packaging and nanotechnology.

EV Group at a Glance


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Founded in 1980

Installed base in excess of 1,500 tools world widein High Volume Production and R&D

Corporate headquarters in Austria subsidiaries in JP, KR, TW and US

Approx. 480 employees worldwide

World wide sales and customer support organization

R&D investment: 20 % of sales revenue

EV Group at a Glance


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Improving the LED efficiency

Main factors for efficiencygain:

Design improvements

(p-contacts & quantumwells)

Enhanced Chip Layout

Patterned sapphiresubstrates

Photonic crystals

Wafer bonding

Wafer level packagingadapted from S. Nakamura / UCSB


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Improving the white LEDefficiency

EQE

EQE

internal

internal

extraction

extraction

conversion

conversion

packaging

packaging

GaN growth substratesSubstrate pre-structuringEngineered substrates

Patterned sapphire substratesPhotonic crystals-cone etching

Phosphor efficiencyPhosphor placement

Thermal conductivityLight extraction efficiencyPower losses


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Chip-Designs for GaN-basedLEDs

Lateral Chip Design

Flip Chip Design Thin Film Flip Chip Design

Vertical Thin Film Design


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EVG Solutions for HB LED Manufacturing


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Lithography Layers

Vertical Thin Film Design

Lateral Chip Design

Essential Lithograpyh

Layers:

-MESA etch mask-Passivation etch mask-Contact to n-GaN-Contact to p-GaN

Optional Layers:

-Bonding or Bumping layerpatterning-Current distribution layers-Surface structurization (PhCs)

-Light management layers

Current high performance LEDs are fabricated byfive sevenindividual litho processes.

Depending on the LED design different optional litho layers are added

to essential lithography layers.


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EV Group Confidential and Proprietary Slide 12

Parameters Impacting LithographyYield

Contamination &

Defects

Equipment

stability

Metrology

Solutions

Process

Window

Alignment accuracy Exposure uniformity

Simulation

Contactless processing Sophisticated handling

Reliable autoalignment Accurate alignment

Robust system design

Accuracy Speed

YIELDYIELD


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Optical Lithography

Challenges:Warpage: Changing exposure gap and handling difficulty for

warped wafers.

Visibility: Low alignment key visibility, due transparency and lightscattering features of LED wafers.

Thickness variation: Reduced alignment accuracy by defocus

presented at Semiconl Taiwan Septemper 8th 2011

Main cost contributors: Yield: Maximum yield for highest process output and lowest CoO Throughput: Highest throughput for lowest CoO Automation: Highest automation for longest continuous operation


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Proximity Lithography Requirements

Attractive Cost-Of-Ownershipand low CapEx

High throughput

High overlay accuracyfor multiple mask processing(front- to frontside, front- to backside)

High print resolution for homogenous currentdistribution

Advanced handling and processing of

bowed / warped wafers

Fast changeover times for multiple substrate sizes


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EVG620HBL Mask Aligner

Source: EVG

Supporting wafer sizes up to 150 mm

Autonomous processingof up to 125wafers

Up to 220 wafers per hour in first print

mode with highest throughput design* Up to 165 wafers per hourthroughput

including automatic alignment*

High-contrast illumination mode

for optimum alignment results

High powerlight source (1kW lamp)

EVG620HBL is a dedicated, fully automatedmask aligner system for high volumemanufacturing of high-brightness LEDs

*5 cassette continuous operation equivalent,optimized process parameters


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Advantages of vertical thin film design:

High light extraction efficiency

Low forward bias

Easy scalability of LED chip size at a constant efficiency

Lambertian far field radiation pattern

Good heat conduction to submount/package

Schematic vertical thin film design layout:

Vertical Thin Film design

carriercarrier

oxideoxide

layerlayer

nn--GaNGaN

MQWMQW

pp--GaNGaNmirrormirror

layerlayer

soldersolder

metalmetal


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Vertical Thin Film design Fabrication process

1. Epitaxy and high-reflectivity p-contact

deposition

2. Wafer bonding

3. Substrate removal 4. Surface structuring (roughening

or NIL)


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Vertical Thin Film Design BondingRequirements

Requirements for metal bonding layer / bonding process:

Mechanical stability during temperature cycling of HB-LED operation

High electrical conductivity for low ohmic losses

Efficient heat conduction from the HB-LED active region

Low bonding temperature for low GaN strain incorporation

Various metal bonding types and techniques:

Thermo compression, Eutectic and Transient Liquid Phase bonding

Low temperature bonding with plasma activation

SEM cross section ofGaAs/InP wafers pair

bonded with Au:Sneutectic


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Overview Wafer Bonding Processes


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1. Evacuate2. Purge Inert Gas

3. Heating Below Eutectic

4. Evacuate to Bonding Pressure

5. Remove Spacers

6. Apply Contact Force

7. Heating Above Eutectic Point8. Bonding

9. Cooling

Eutectic Wafer Bonding

Principle:Formation of an eutectic alloy / intermetalliccompound as bonding layer.


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Eutectic Bonding Results

Au rich Au-Sn already popular inelectronics packaging

Bonding Temperature 300C

Cr/Au/Sn/Au electroplated cap

Cr/Au deposited device wafer

AuAu--SnSn

BondingBonding AuAu--Si BondingSi Bonding

Recently very popular for vacuumencapsulation

Eutectic Temperature 363C


Au deposition, Si from bulk or Poly-Si thinfilms

Excellent Interface Uniformities

Courtesy of SILEX

C-SAM


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Eutectic Wafer Bonding Au:Sn

SEM cross section image of GaAs/InP wafers pair bonded with Au:Sn eutectic


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Low Temperature TLP

In melting point 156C (AuIn2 with 53,8 wt% In)


Courtesy of Samsung SAIT

L1 In rich AuIn2

L2 Au rich AuIn

L3

Au-In solid

Courtesy of non-disclosed EVG customer

Transient Liquid Phase BondingResultsAuAu--In TLP BondingIn TLP Bonding


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Transient Liquid Phase BondingResults

C-SAM

CuCu--SnSn

TLP BondingTLP Bonding NiNi--SnSn

TLP BondingTLP Bonding

Cu3Sn gets isothermally solid whenall Sn is used up for complete alloyforming

Stable Cu3Sn has excellentmechanical and electrical propertiesand a melting point >600C

Low Temp. Bond Process: (270C)

Fast heating rate required to melt tinbefore reacting to an intermetallic

Low Temp. Bond Process: 300C


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Au-Au Thermocompr. Bonding

SAM images of Si-Si wafer pairs bonded

with Au-Au thermo-compression bonding

at various temperatures.

(small defects mainly due to particles)

Bond strength vs. bonding temperature

Measured by tensile testing for Si-Si wafer pairs

bonded with Au-Au thermo-compression bonding.

C C B d S h


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Cu-Cu Bond Strength:Bonding Temp. Effect

Experimental Conditions

Si(100)/SiO2

/Ta(25nm)/PVD-Cu(1.5m)

Wafer-level bonding : 25kN, 10

-3

Torr, N2

atm, 30min

Bonding temperature : 300, 350 and 400C

No pre-bond/post-bond treatments

300C

350C

400C

1um

Bonding temperature (C)

Interfacialadhesio

nenergy,

G(J/m2)

300 400350

1

2

3

4

5

0

seam

seam

no seam

Collaboration with Andong NationalUniversity Dr. Young-Bae Park

C C B d S h


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Cu-Cu Bond Strength:Post-bond Anneal Effect

Experimental Conditions

Si(100)/SiO2

/Ta(25nm)/PVD-Cu(1.5m)

Wafer-level bonding :

300C,

25kN, 10-3

Torr, N2

atm, 30min

Post-bond annealing : 200, 250 and 300C for 60min under N2

atm

1um

200C

300C

no annealing

250C

large seam large seam

small seamAlmost no seam

Annealing temperature (C)

Interfacialadhesionene

rgy,

G(J/m2)

no anneal 200 250 300

3

6

9

12

0

15

Minimum requirement

Post-bond annealing significantly improves interfacial properties and

adhesion energy when bonding is done at a low temp.

Collaboration with Andong NationalUniversity Dr. Young-Bae Park


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EVG560 HBL: HB-LED WaferBonding System

Multi-substrate wafer bondingfor highestthroughput up to 176 bonds/h(2 wafer equiv.)

Automatic handling of bowed and warpedwafers

Low temperature metal bonding

Eutectic, Transient-Liquid Phase andThermo-compression bonding

integrated pre-processing modules

Modular design with swap-in modules

Up to four process modules

Easy switch between wafer sizes

Cassette-to-cassette operation

EVG560 HBL Automated Wafer BondingSystem for HB-LED fabrication


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Summary

Cost per lumen demands further decreaseto enable solid state lighting technology for general

lighting EVGs solutions support efficient cost reduction by

increased throughput as well as highest processing

yield in optical lithography and wafer bonding. EVG620HBL fully automated mask aligner with 165 wafers

per hour throughput including automatic alignment

EVG560HBL fully automated wafer bonder with up to 176bonds/h (2 wafer equiv.) using our proprietarymultisubstrate bonding technology (also available forsemiautomated systems)


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Thank you for your attention!

Please visit our booth #2506

Documents

7.13001330_high Throughput Lithography_Semicon Taiwan 2011