6A Power-Efficient 33 GHz 2 1 Static Frequency Divider in 0.12-Pm

8/2/2019 6A Power-Efficient 33 GHz 2 1 Static Frequency Divider in 0.12-Pm

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TU2B-5A Power-Efficient 33 GHz 2: 1 Static Frequency Divider in 0.12-pm

SO1 CMOSJean-Olivier Piouchart', Jonghae Kim', Hector Recoules2,Noah Zamdmer', Yue Tan', MelanieSherony', Asit Ray', Lawrence Wagner'

IBM Semicond uctor Research and Developmen t Center, Hopew ell Junction, NY 12533IBM Essonnes Components Technology Laboratory, 9 1 Essonnes, Corbeil, FranceI

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Absfrucf - A 2 : l static frequency divider was fabricatedin a 0.12-pm SO1 CMOS technology. The divider exhibits amaximum operating frequency of 33 GHz. When the powerconsumption is scaled down to 2.1 mW, a maximum operatingfrequencyof2 5 GHz is measured.I. INTRODUCTION

High-speed static 2:l frequency divider circuits arerequired for many applications, from frequency synthesisin wireless communications, to quadrature signalgeneration and clock recovery in high-speed serial links.These applications require high speed, low power, highsensitivity and monolithic integration. To date, mainlybipolar and 111-V technologies employing the Current-Mode Logic (CML) style have been used to fabricatefrequency dividers, due to the high performancerequirements of communications systems. For example, an87 GH z InP DHBT static frequency divider was published[ I ] , though the 700 mW power consumption prohibits ahigh level of integration. CMOS technologies are nowbeing used, though at lower speed: a CMOS staticfrequency divider achieved a maximum operatingfrequency of 18.5 GHz [2], at a power consumption of 21mW per MSFF. Technology scaling, and materialsinnovations such as SOI, promise to improve theperformance o f CMO S frequency dividers. The impact ofSO1 on digital CMOS power and speed is welldemonstrated [3,4, 51. In this paper we present the impactof an advanced SO1 technology on the power consumptionand speed o f a CM L divider-by-two.

11. Crrccurr DESIGNFigure 1 shows the block diagram of the 2 1 staticfrequency divider. It is based on CML master and slavelatches connected in series. All the signals are differential,

though the latches would also function with a single-endedclock. It can be shown that the cross connection betweenthe output of the slave latch and the input of the mastercauses the clock frequency to be divided by two. The static

0-7803-76943/03/$17.00 2003 IEEE

frequency divider by 2 is usually the slowest functionbecause of the feedback loop used. The divider is furtherslowed by the load presented by the output buffer to theslave latch. The latches and the output buffer are biasedthrough current mirrors. The latches and the output bufferhave a separate power supply connection so that thelatches' current consumption can be monitored.

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Fig. 1. Static frequency divider block-diagramAs shown in Fig 2 each latch is implemented in a classic

CML architecture. Following circuit optimization, thzwidths of the clock and data differential-pair NFETs weredesigned to be 30 pm and 10 pm, respectively. Eventhough low-Vt NFETs are available in the technology,regular Vt NFETs were used because of the transistormatching concem. Poly silicon resistor loads of 400 Rwere used in the latches. This is a rather high load for highfrequency applications [Z], and it reflects the small devicesizes we were able to employ because of the low drainparasitic capacitance of SO1 technology.'V"I)Fig. 2. Latch circuit schematic

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The small device sizes decrease power consumption, butmake a 400 0 load-resistor necessary to maintain a 70 0mV peak-to-peak voltage swing. The minimum devicesizes are determined by the parasitic capacitances that donot scale with device width, and also by differential-pairmatching. No inductive peaking was used to extend thebandwidth frequen cy. The current biases of the latches andthe output buffer current bias are set by current sourcescontrolled by a current mirror. Despite the power losses,current sources are necessaly in many applications fortemperature compensation or to allow switching betweenstandby and ac tive modes. T he output buffer is adifferential FET pair loaded with on-chip 50 Cl resistors.The output buffer power can be set independently of thedivider core by chan ging the .independent voltage supplyVDD . The schematic is given in figure 3.FTI:N + H t. N-+ ISw Q3Fig. 3. Buffer schematic used for the simulation111. TECHNOLOGY

The circuits are fabricated in a 0.12pm IBM SO1 CMOStechnology with 8 copper metal layers. The chip size is0.35x0.25 m2ncluding th e 4 RF input and output pads.We fabricated the 'dividers on a Regular-ResistivitySubstrate (RRS) and on a High-Resistivity Substrate(HRS) with resistivities of 12 Q.cm and 100 Q.cmrespectively.

Fig. 4. Dividercore layout view (a = 70pm and b = 40pm)

The manufactured NMOS transistors have a cut offrequency of 150 GH z and more than 200 GHz for thecurrent gain (fT) and maximum available power gain (fm.)respectively [ 5 ] . The technology offers a wide variety ofhigh-Q passives such as inductors (Peak Q>50),accumulation varactors, and interdigitated back-end andMIM linear capacitors. The technology offers polysiliconresistors as well. Owing to the tight ground-rules of thetechnology the circuit layout, shown in figure 4, is velycompact. The total area is 40 pm x 70 pm .

IV. EXPERIMENTAL RESULTSThe divider was measured at various power supply

voltage biases. As shown in figure 5 , a maximu m divisionfrequency of 33 G Hz was measured at 2 .4 V. Since threetransistors are stacked between Vdd and ground, we canuse voltage supply as high as 2.6 V without compromisingthe transistors' reliability.

L_ ??.ill 33./02 GHzo u t p u t Y

ICI"I"r 7 0 rJ., 1 G sa." .a r*,

, , . . I . . ,,m, Il:,i.l.*,Fig. 5 .GHz, for a 33.02 GHz input signal.

Divider output spe cm m measurement in a span of 40

To the authors' knowledge, this is the fastest reportedstatic frequency divider fabricated in a CMO S technology.As expected with a static divider, the circuit functionsproperly at low frequency (Fig. 6).

The minimum input power required to insure properfrequency division (circuit input sensitivity), as function offrequency was measured for four different supply voltages1, 1.5, 2 and 2.4 V (Fig. 6). The maximum operatingfrequencies achieved at 1, 1.5, 2 an d 2.4 V are 25, 28.6 30and 33 GHz respectively. The best reported static CMOSdivider has a maximum operating frequency of 18.5 GHzat 1.5V supply [2], and requires an input power of I O dBm(Fig. 6) .Figure 6shows that the divider natural oscillation

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frequency is twice as high at the same 1 .5 V power supplyvoltage for SO1 than for bulk.5 , I01 O.12um CMOS 121 P Thiswork 1

0 5 10 15 20 25 30 35Input frequency (GHr)Fig. 6 .divider-by4 for different supply voltages

Sensitivity versus frequency of static CM L frequency

The performance advantage o f SO1 over bulktechnology is largely aided by the absen ce of reverse bodyeffect in SOI. Even though several devices are stacked inthe CML frequency divider, in SO1 these devices do notsuffer from Vt increases. The SO1 CM L frequency divideri s also more sensitive at maximum frequency than the bulkversion.

Figure 7shows the impact of substrate resistivity onthe circuit input sensitivity. We measured the dividers with1.0 V supply for low power circuit applications. Thecircuit sensitivity on HR S is several dB higher than onRRS. In high frequency applications, the substrate lossesresult in leakages and circuit performance degradations.The HRS provides also better isolation [ 7 ] . Overall, wemeasure consistently better circuit performances with HRSthan RRS.

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-e- A:Vdd=l.OV(RRS).m. B:Vdd=l.OV (HRS) . ... .'r'L I0 5 10 15 20 25Input frequency (GHz)

Fig. 7 .Fig. 8 shows the maximum operating frequency as

function of power consumption. The maximum operating

Sensitivity comparison between RRS and HRS

frequency of 33 GHz is achieved at power consumption of22.1 mW per MSFF from a 2 .4 V supply. At I , 1. 5 an d 2V supply a maximum operating frequency of 2 5 , 2 8 . 6 an d30 GHz is achieved for a power consumption of 2.7, 7.66and 12 mW per MSFF respectively. This shows the powerscalability of. the SO1 technology to very low-voltageoperation. The fastest CMOS 0.12 pm frequency dividerby 2 using the same CML latch architecture withoutinductive peaking operates up to 18.5 GHz, for an inputpower of more than I O dBm, with a power consumption of27 mW per MSFF from a 1. 5 V supply [2].

0 5 10 15 20MSFF Power(mW) 5

Fig. 8.consumptionMaximum operating frequency versus MSFF power

One way to compare the power and speed performancesof different circuit dividers is to comp ute the pow er delayproduct. At 1 V the SO1 divider exhibits a record energyper gate of 13.5 fJ, assuming 2 gates delay per flip-flopand an equivalent complexity of 4 logic gates [6]. Fig. 9shows a comparison of state of the art static dividers inseveral technologies.

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Fig. 9.

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1 , 1 1 1 ,

0 10' 1o2 10'Power per Flip-Flop, mWPower-delay product of state of the art static dividers

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This is to the authors knowledge, the lowest staticdivider energy reported for any technology at a higheroperating frequency than 2 0 GHz. Th e closest energy is 24fl for an AlInAs HBT technology, which is a 78 % higherenergy than that reported i n this work. The mechanism forenergy reduction is very different for an SO1 CM OStechnology than for an HB T compound technology. Owingto the threshold and supply voltage scaling, low-operatingvoltage supply can be used. This allows dramaticreduction of switching energy. If we compare to bulkCMOS, the lower parasitic capacitance offered by the SO1technology is an important factor for power consumptionreduction. These results combined with the ULSlcapabilities of the technology are very promising for theintegration of multiple high-speed serial links on the samechip. This integration could lead to the aggregation andprocessing of unsurpassed amounts o f data.

Fig. 10 shows the chip microphotographs and the inputand output access coplanar wave-guides.

CPWLINE CLK QOUT

CLKB QOUTBFig. 10. Divider microphotograph

V. CONCLUSIONA low-power and high-performance CML static

frequency divider was designed in 0 . 1 2 pn SO1 C M O Stechnology. At 1 V a maximum operating frequency of 25GHz was measured for a power dissipation of only 2.7m W per MSFF. This is equivalent to a power delayproduct of 13.5 0. his is the lowest energy reported forany technology for any static divider operating at afrequency higher than 2 0 GHz. At 2.4 V a record 3 3 GH zoperating frequency for CMOS technology is achieved.This demonstrates the speed and power advantages of SO1technology for CM L latches used extensively for RF an dhigh-speed communications.

ACKNOWLEDGEMENTWe acknowledge the contributions of our colleagues at

the Advanced Semiconductor Technology Center, and thesupport of Susan Chaloux, G. Shahidi, B. Davari, MarcDupasquier, D. Friedman, and M. Soyuer.

REFERENCESKrishnan, S. ; Griffith, Z. ; Urteaga, M.; Wei, Y.; Scott, D.;Dahlstrom, M.; Parthasarathy, N. ; Rodwell, M., 87 GHzstatic frequency divider in an InP-based mesa DHBTtechnology, GaAs IC Symposium, 2002. 24th AnnualTechnical Digest, 2002, Page(s): 294 -296Hans-Dieter Wohlmuth, Daniel Kehrer, Werner Simbuger,A High Sensitivity Static 2:1 Frequency Divider up to I9GHz in 120 nm CMOS, IEEE RFIC2002, Proceedings, pp.231-234, June 2002N. amdmer, A. Ray, 1O Ploucbart, L. Wagner, N. Fong,K. A. Jenkins, W. Jin, P. Smeys, I. Yang, G. Shahidi, F.Assaeraghi, A 0.13-lm SO1 CMOS technology for low-power digital and RF applications, VLSI Tech. Symp.,2001.. P a d s ) . 85-86.G. hahid ; SO1 technology for the GHz era,h t t ~ : l l r e s e a r c h w e b . w a t s o ~ . i b m . c o ~ i o u l l r ~ 4 6 2 l s h a h i d i . ~ d f .

[ 5 ] N.Zamdmer, J.-0. Plouchart, J. Kim, L-H. Lu, S .Narasimha, P. A. @Neil, A. Ray, M. Sherony, L. Wagner,Suitability of Scaled SO1 CMOS for High-frequencyAnalog Circuits, 2002 European S olid-State DeviceResearch Conference.161 S okolich. A.: Thomas. S.. 111: Fields. C.H.. Hieh-meed_and low-power InAIAdInG&s heterojunction- bipolartransistors for dense ultra high speed digital applications,Electron Devices Meerins. 2001. IEDM Technical Dieest.International, 2001, Pagers): 35.5.1 -35.5.4.[7] Raskin, I.-P.; Viviani, A.; Flandre, D.; Colinge, JPSubstrate crosstalk reduction using SO1 technologyElectron Devices, IEEE Transactions on , Volume: 44Issue: 1 2 , Dec. 1997, Page(s): 2252-2261.181 Sokolich, M.: Fields, C.H.: Thomas. S. . 111.; Binqianz Shi;

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. . -Boegeman, Y.K.: Martinez, R.; G e r , A.R.: Ma.&av, M.,A low-power 72.8-GHz static frequency divider inAlInAdlnGaAs HBT technology, IEEE Journal of Solid-Stare Circuits, Volume: 36 Issue: 9 , Sept. 2001, pp. 1328 -1334.[9] Vaucher, C.S.; Apostolidou, M., A low-power 20 GHzstatic frequency divider with programmable inputsensitivity,2002 IEEE RFIC Sym posium, pp. 235 -238.[ I O ] Washio, K.; Ohue, E.; Oda, K.; Hayami, R.; Tanabe, M.;Shimamoto, H Optimization of characteristics related tothe em itter-base junction in self-aligned SEG SiGe HBTsand their application in 72-GHz-staticl92-GHz-dynamicfrequency dividers, Elecnon Devices, IEEE Tronsoctionson , Volume: 49 Issue: I O , Oct. 2002, Page(s): I755 -1760.[ I l l Hayami, R; Washio, K, 40 GHz 7. 9 mW low-powerfrequency divider IC using self-aligned selective-epitaxial-

growth SiG e HBTs, Electronics Letters, Volume: 38 Issue:1 4 , 4 uly 2002, Page(s): 707 -709.

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6A Power-Efficient 33 GHz 2 1 Static Frequency Divider in 0.12-Pm