6476 IEEE TRANSACTIONS ON POWER …msrprojectshyd.com/upload/academicprojects...6476 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 Dual Flying Capacitor Active-Neutral-Point-Clamped

6476 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016

Dual Flying Capacitor Active-Neutral-Point-ClampedMultilevel Converter

Roozbeh Naderi, Student Member, IEEE, Arash Khoshkbar Sadigh, Member, IEEE,and Keyue Ma Smedley, Fellow, IEEE

Abstract—Hybrid multilevel converters combine features of con-ventional multilevel topologies to provide an acceptable tradeoffbetween the advantages and disadvantages of these converters.For many industrial applications, common dc link is a require-ment that limits the choice of topologies to neutral point clamped(NPC) and flying capacitor multicell (FCM) hybrid types. Thispaper investigates the operation of a hybrid five-level topology andproposes a modulation method that takes the advantage of thecombined features of NPC and FCM. The dual flying capacitor(FC) active-neutral-point-clamped (DFC-ANPC) converter pro-vides certain advantages such as natural soft switching of linefrequency switches, elimination of the transient voltage balanc-ing snubbers, and a more even loss distribution. Simulation resultsand experimental verification of the five-level DFC-ANPC con-verter are presented to validate the performance of the converteras well as the applied modulation technique.

Index Terms—Flying capacitor (FC), multilevel converter,neutral point clamped (NPC).

I. INTRODUCTION

M EDIUM-VOLTAGE multilevel converters have foundwide use in applications such as motor drive, grid-tied

inverter and rectifier, and medium voltage dc (MVDC) [1], [2].The main motivation for the use of multilevel converters is toachieve higher voltage capability with commercially availablelower voltage semiconductor devices. Typical fast switches suchas IGBTs and IGCTs with voltage ratings up to 6.5 kV canreliably operate at about 4 kV [3], [4]. One way to handle highervoltage applications is direct series connection of switchingdevices; however, this solution has inherent transient voltagebalancing and high dv/dt issues. Multilevel converters thus roseto the occasion. They also have the added advantages of betterwaveform quality, lower total harmonic distortion (THD), and

Manuscript received May 14, 2015; revised August 26, 2015; acceptedNovember 2, 2015. Date of publication November 18, 2015; date of currentversion March 25, 2016. Recommended for publication by Associate EditorJ. R. Rodriguez.

R. Naderi is with the Department of Electrical Engineering and Com-puter Science, University of California Irvine, Irvine, CA 92697 USA (e-mail:[email protected]).

A. K. Sadigh was with the Department of Electrical Engineering andComputer Science, University of California Irvine, Irvine, CA 92697USA. He is now with Extron Electronics, Anaheim, CA 92805 USA (e-mail:[email protected]).

K. M. Smedley is with the Department of Electrical Engineering and Com-puter Science, University of California Irvine, Irvine, CA 92697 USA, andalso with One-Cycle Control, Inc., Irvine, CA 92618 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2015.2501401

lower electromagnetic interference (EMI) over their two-levelcounterparts [5].

For applications such as MVDC, a common dc link among thethree phases is a requirement. For some other applications suchas motor drive, a common dc link offers the option of eliminatingor reducing the complexity of phase-shift transformer at thepassive front end. For certain configurations such as active frontend, typically a common dc link is required. In addition, lessprotection and clamp circuit is required for a single common dclink in contrast to several dc links [5]–[9].

Conventionally, two multilevel converter topologies, neutralpoint clamped (NPC) [10] and flying capacitor multicell (FCM)[11], [12], are known to provide a common dc link. NPC and itsenhanced variety, active NPC (ANPC), are widely used in indus-try for three-level applications [7]. For higher levels, however,NPC encounters the critical dc-link voltage balancing problem,excessive number of clamping diodes, and unbalanced loss dis-tribution among semiconductor devices. FCM stands out as analternative for higher levels with balanced flying capacitor (FC)voltage and excellent loss distribution [9]. The disadvantage ofFCM topology, however, is the excessive number of capacitorsin higher levels. Capacitors are usually avoided due to highinitial price, maintenance and replacement surcharges, and lowreliability [13].

Hybrid multilevel converter topologies with a common dclink combine some features of NPC and FCM that opens thepossibilities to take advantages of both topologies. Among hy-brid topologies, the five-level FC active NPC (FC-ANPC) pro-vides an acceptable compromise between cost and performanceand consequently, found its way to industrial applications [14].FC-ANPC provides a balanced dc-link voltage by using onlyone FC at the cost of four additional switches per phase com-pared to the conventional basic topologies [15]. It offers a goodtradeoff compared to the disadvantages of FCM and NPC con-verters. One drawback of the FC-ANPC topology is the fourpairs of series-connected switches, which, although operatingat the line frequency, require transient voltage balancing snub-bers [16]. The uneven loss distribution among semiconductordevices is another major issue that limits the nominal power ofthis converter.

In this paper, the operation of a hybrid multilevel convertertopology, dual FC-ANPC (DFC-ANPC), proposed originally in[17], [18], is investigated in Section II. Certain features suchas zero-voltage switching of line frequency switches are pre-sented, which reduces the switching loss and eliminates theneed for transient voltage balancing snubbers. In Section III,carrier-based and non-carrier-based modulation techniques for

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NADERI et al.: DUAL FLYING CAPACITOR ACTIVE-NEUTRAL-POINT-CLAMPED MULTILEVEL CONVERTER 6477

Fig. 1. Five-level DFC-ANPC topology.

the five-level DFC-ANPC converter are presented. Section IVbriefly presents the generalized case of DFC-ANPC. SectionV provides a comparison between selected five-level convertertopologies featuring a common dc link. Simulation and exper-imental verification of the operation of five-level DFC-ANPCare provided in Section VI.

II. DFC-ANPC TOPOLOGY AND OPERATION

The five-level DFC-ANPC topology, as shown in Fig. 1, canbe viewed as two three-level FCM converter units connectedto the output through line frequency switches S5 and S6 . Thetop FCM unit uses high-frequency switches S1 , S

′1 , S2 , and S ′

2along with capacitor C1 to generate the positive half cycle of thepulsewidth-modulated (PWM) waveform. The generated volt-age is transferred to the output through S5 during the positivehalf cycle. During the negative half cycle, the bottom FCMunit, consisting of S3 , S

′3 , S4 , S

′4 , and C2 , generates the PWM

waveform, which is transferred to the output through S6 .The voltage of the FCs, C1 and C2 , can be individually bal-

anced through the existing redundant states of each FCM unit.Table I lists the switching states for the DFC-ANPC converterand the effect of each state on the FCs voltages. The redundantstates for level +E, i.e., +EP and +E0, are used to balance C1’svoltage. Similarly, the redundant states for level −E, i.e., −E0and −EN, are used to balance C2’s voltage.

During the normal operation, the operating voltage of bothFCs in the DFC-ANPC five-level converter is a quarter of thedc-link voltage, which means E. This results in clamping thevoltage stress of high-frequency switches to E. For line fre-quency switches, however, voltage stress is half of the dc-link

TABLE ISWITCHING STATES OF THE FIVE-LEVEL DFC-ANPC CONVERTER

Level State S1 S2 S3 S4 S5 S6 C1 C2

+2E +2E 1 1 1 1 1 0 N.A. N.A.+E +EP 1 0 1 1 1 0 ix > 0 Charge N.A.

ix < 0 Discharge+E0 0 1 1 1 1 0 ix > 0 Discharge N.A.

ix < 0 Charge0 0P 0 0 1 1 1 0 N.A. N.A.

00 0 0 1 1 1 1 N.A. N.A.0N 0 0 1 1 0 1 N.A. N.A.

−E −E0 0 0 1 0 0 1 N.A. ix > 0 Chargeix < 0 Discharge

−EN 0 0 0 1 0 1 N.A. ix > 0 Dischargeix < 0 Charge

−2E −2E 0 0 0 0 0 1 N.A. N.A.

S ′1 , S ′

2 , S ′3 , S ′

4 are switched complementary to S1 , S2 , S3 , S4 , respectively.ix > 0 represents outbound current and ix < 0 represents inbound current.N. A. = Not Affected.

voltage, i.e., 2E, which may be realized by two switches inseries, as shown in Fig. 1.

An important feature of this topology is the “soft cycle com-mutation” between the positive and negative half cycles. States0P, 0N, and 00, as listed in Table I, can generate level 0 ei-ther through the top part switches S ′

1 , S′2 , S5 , the bottom part

switches S3 , S4 , S6 , or both. The inbound and outbound currentpaths in each case are shown in Fig. 2. At the transition from 0Pto 00, S6 must turn on while the voltage across it is near zero.When switching back from 00 to 0P, S6 must turn off whilethe voltage across it is near zero. In a similar fashion, the volt-age across S5 is near zero when switching between 00 and 0N.Therefore, if 00 is used as an intermediate state between 0P and0N, line frequency switches S5 and S6 will hold zero-voltageswitching operation at all times. So, when the phase voltage halfcycle changes, the operating FCM unit can be softly detachedfrom output, and the operation can be softly handed over to theother FCM unit. An advantage of this phenomenon is the elim-ination of switching loss on S5 and S6 . More importantly, notransient voltage balancing snubber is required when realizingS5 and S6 by series-connected switches. Note that the blockingmode voltage balancing resistors may still be required due tothe switching devices’ cutoff current tolerance [16].

III. MODULATION TECHNIQUES

Various modulation techniques may be adapted for the DFC-ANPC topology. Carrier-based modulation with sinusoidal ormodified reference as well as non-carrier-based techniques suchas space vector modulation (SVM) and selective harmonic elim-ination (SHE) may be used to generate the gate signals [5], [19].The choice of a modulation technique is mostly a tradeoff amongthe requirements of the application, complexity of the software,and relative cost of the control hardware. For the DFC-ANPCtopology, the main requirement is to ensure the FC voltages arebalanced and the neutral point voltage is maintained at half ofthe dc-link voltage.


Fig. 2. Soft cycle commutation concept. Inbound and outbound current paths for states (a) 0P, (b) 00, and (c) 0N.

A. Carrier-Based Modulation

Carrier set’s arrangement and reference waveform’s shapeare the main sources of varieties in carrier-based modulationtechniques for multilevel converters.

As for carrier set’s arrangement, level-shifted carriers (LSCs)and phase-shifted carriers (PSCs) are the two main categoriesthat are suitable for diode-clamped and multicell structures.Two members in the LSC family, alternative phase oppositiondisposition (APOD) and phase disposition (PD), are known togenerate the best results for singe-phase and three-phase con-verters, respectively [19]. PSC in its original form has beenshown to generate a multilevel PWM waveform that matcheswith APOD [20]. Also a modified version of PSC with dynamicphase shift has been shown to match with PD [21].

The reference for single-phase applications is usually a sim-ple sinusoidal waveform. For three-phase applications, a varietyof reference waveforms are available due to the possibility ofcommon-mode injection in three-phase structure. This flexibil-ity has been used to serve different purposes such as increaseddc-link utilization, lower THD, lower loss, and neutral pointvoltage control [22], [23].

For the DFC-ANPC converter, a hybrid modulation techniqueis required due to the hybrid structure of the topology. Fig. 3illustrates the carrier-based modulation technique using PSCwith sinusoidal reference for single-phase case. It is intuitiveto separate the operation to positive and negative half cycles,since each one is generated with an independent three-levelFCM unit. The gate signals for each FCM unit is then generatedusing PSC to provide natural voltage balancing for the FCs [24].Switches S5 and S6 must be on during the positive and negativehalf cycles, respectively, to connect the associated FCM unit tothe output. Note that, soft cycle commutation, S5 and S6 canbe achieved by a short duration of overlap at transition from

positive half cycle to negative half cycle and vice versa. ThePWM waveform generated at the output matches the APODscheme.

For three-phase cases, a similar approach may be adoptedexcept that, to generate a PD scheme equivalent, the positivehalf cycle carriers should hold π/2 phase shift with respect tothe negative half-cycle carriers. Also, the carriers incorporatea dynamic phase shift, which always adds up by π/2 at thecarrier band transitions for sampled reference waveforms [21].For the reference waveform, centered space vector PWM (CSV-PWM) sampled at half PD carrier period can provide similarperformance as SVM [22], [25]. Fig. 4 illustrates the modula-tion technique using sampled CSV-PWM along with modifiedPSC for the DFC-ANPC converter. It is important to choose areference waveform with balanced common-mode injection tomaintain the neutral point’s voltage balance. Also, higher fre-quency and lower amplitude of the injected common mode candecrease the neutral point’s voltage ripple.

B. Non-carrier-based Modulation

For non-carrier-based modulation techniques such as SVMand SHE, the five-level PWM waveform may be generated firstand then decomposed to the required switching signals. In thisprocedure, as shown in Fig. 5, the five-level PWM waveformis first separated to positive and negative half-cycle three-levelPWMs. Each half cycle is then decomposed to switching signalseither through a state machine decoder or an active balancingalgorithm. The state machine decoder ensures that transitionsare uniformly distributed between the switches and, therefore,provides natural voltage balancing [26]. The active balancingalgorithm compares the FCs voltages to their target value ateach transition. Based on this comparison, it decides whether the


Fig. 3. Carrier-based modulation using PSC with sinusoidal reference forsingle-phase converters. (a) Reference and carriers arrangement. (b) Gate sig-nals. (c) Output waveform.

capacitor needs to be charged or discharged. Then consideringthe direction of output current at the moment, it determineswhich redundant state to switch to, to provide the charging ordischarging and, therefore, to balance the FCs voltages [27].

To provide soft cycle commutation, cycle separation unitneeds to know the half cycle change before it actually occurs.This cannot be extracted from the five-level PWM signal itself,since the half-cycle change cannot be detected until the firsttransition in the next half cycle occurs when it is too late togenerate the 00 state. Therefore, PWM modulator should notifythe half-cycle separator block of half-cycle change in advance.

It is important to note that this procedure is independent of theadopted modulation technique. Therefore, it can be used withcarrier-based modulation techniques or non-carrier-based ones.This should be a good alternative when the complexity of thecarrier-based technique is relatively high, e.g., for PD scheme.

Fig. 4. Carrier-based modulation using modified PSC with sampled CSV-PWM reference for three-phase converters. (a) Reference and carriers arrange-ment. (b) Gate signals. (c) Output waveform.

IV. GENERALIZATION

The DFC-ANPC topology can be generalized to higher num-ber of levels. The number of levels should be odd and greaterthan or equal to five, due to the symmetry of the topologywith respect to the neutral point. Fig. 6 shows the generalizedtopology for an N-level converter. The top and bottom unitsare (N + 1)/2-level FCM converters that are connected to theoutput through SN and SN +1 . Each FCM unit can individuallybalance the associated FCs during its operating half cycle, us-ing the available redundant states. SN and SN +1 are realizedby (N − 1)/2 switches in series without any transient voltagebalancing snubber due to the soft cycle commutation advantageof the DFC-ANPC converter. Modulation techniques similar tothose mentioned in Section III may be used for the generalizedcase.


Fig. 5. Non-carrier-based modulation for a phase leg of DFC-ANPC converterusing: (a) state machine decoder and (b) active balancing algorithm.

Fig. 6. Generalized topology of N-level DFC-ANPC.

V. COMPARISON

This section provides a general comparison between the DFC-ANPC topology and other five-level converter topologies witha common dc link. Table II lists the number of capacitors,switches, and diodes for a three-phase five-level converter for

TABLE IICOMPARISON OF FIVE-LEVEL TOPOLOGIES

Topology Capacitors Switches Diodes Loss CommentsDistribution

NPC 0 24 36 Poor Low switch countHigh diode count

Unbalanced dc-link voltageFCM 18 24 0 Excellent High capacitor count

Low switch countSMC 6 36 0 Good Low capacitor count

High switch countFC-ANPC 3 36 0 Fair Very low capacitor count

High switch countLow-frequency series switches

CFC-ANPC 2 34 0 Poor Very low capacitor countHigh switch count

DFC-ANPC 6 36 0 Good Low capacitor countHigh switch count

Soft-switched series switches

NPC, FCM, stacked multicell (SMC), FC-ANPC, common FC-ANPC (CFC-ANPC), and DFC-ANPC topologies.

The advantage of NPC is the use of low number of switchesand no FCs in the circuit topology. However, excessive num-ber of diodes, uneven loss distribution among semiconductorswitches, and unbalanced voltage of dc-link capacitors makefive-level NPC topology less of an option for MV converter.The 12 diodes per phase leg might not be a big cost and reli-ability burden alone, but the added fact that each diode shouldhave its own cooling system adversely affects the total cost ofthis topology. Loss distribution among semiconductor switchesat low modulation index maybe improved through space vectorredundancies but the problem persists in high modulation index.For the active-front-end configuration, NPC converter has beenshown to have the ability to balance dc-link capacitors. Yet, thecost is the limitation on power factor, which is unfavorable forthe main target application of regenerative motor drives [28].

The FCM converter has the advantages of low switch count,balanced FCs voltages, and uniform loss distribution. The mainproblem with this topology is the excessive number of capaci-tors, which are expensive, less reliable, and require maintenanceand replacement.

In an attempt to decrease the number of capacitors in FCMconverter, SMC topology were developed, which requires onlytwo capacitors per phase leg and also provides good loss dis-tribution between switches [26], [29], [30]. A drawback of thistopology is the need for four extra switches per phase leg. Moreimportantly, the use of bidirectional switches for connecting theneutral point to the output degrades the loss distribution at lowmodulation indexes.

In contrast to the aforementioned topologies, FC-ANPC isa viable alternative [15]. One FC per phase leg and balancedvoltages of main dc-link capacitors are the advantages of thistopology. The disadvantages include high switch count and fourpairs of series-connected switches per phase leg, which requiretransient voltage balancing snubbers. The added snubber lossis small since the associated switches are switching at line fre-quency. Another disadvantage of this topology is the uneven loss


TABLE IIISIMULATION AND EXPERIMENT PARAMETERS

Circuit Parameter Value

Simulation dc-link voltage (Vd c ) 16 kVExperiment dc-link voltage (Vd c ) 400 VDC-link capacitors (Cd c ) 1.6 mFFCs (Cx x ) 400 μFPhase modulation index (M) 1Phase fundamental frequency (fo ) 50 HzPhase switching frequency (fs ) 1650 HzLoad inductance (L l o a d ) 15 mHLoad resistance (R l o a d ) 18 ΩBalance booster inductance (Lb o o s t ) 1.85 mHBalance booster capacitance (Cb o o s t ) 20 μFBalance booster resistance (Rb o o s t ) 1.5 Ω

CSV-PWM with modified PSC used for modulation.Load configuration is Y.

distribution. The four switches of the FCM unit are operating athigh frequency at all times, while the other eight switches areconducting only half a cycle and switching at line frequency.Despite the disadvantages, FC-ANPC has provided a realistictradeoff and has been commercially used for five-level medium-voltage motor drive application [9], [14].

The CFC-ANPC topology proposed in [31] shares two ca-pacitors between all three phases and, therefore, greatly reducesthe number of capacitors. The number of switches is higher thanNPC and FCM but lower than the other topologies in the list.The disadvantage of this topology is its uneven distribution oflosses, since the common switches must conduct the current ofall three phases.

The DFC-ANPC topology requires 12 switches per phase leg,which is in this aspect similar to SMC and FC-ANPC topologies.However, compared to FC-ANPC, it provides a more even lossdistribution among semiconductor switches. As can be seen inFigs. 3(b) and 4(b), the high-frequency transitions are evenly dis-tributed among top and bottom FCM units. Therefore, switchingloss is distributed among eight switches. Also, all the switchesare operating in half a cycle, which provides a better distributionof conduction loss. Since each switch has an individual coolingsystem, a better loss distribution means each switch can operateat higher current. Therefore, lower current derating is requiredand the topology is expected to provide higher nominal powercompared to FC-ANPC. Moreover, the series-connected switchpair S5 and S6 does not need transient voltage balancing snub-bers due to the soft cycle commutation concept explained inSection II. In addition to the lower cost, this will slightly de-crease the total switching loss compared to the FC-ANPC case.The advantage of soft cycle commutation is more prominentfor higher levels where more series-connected switches are re-quired. These advantages come at the cost of an additional FCper phase leg compared to the FC-ANPC topology. Neverthe-less, since each capacitor is operating half cycle, the rms currentpassing through each is �2 times smaller than that of the singlecapacitor of FC-ANPC. In other words, the capacitor loss is alsodistributed among two capacitors, and therefore, longer lifetimeand better reliability are expected from each of them [13].

Fig. 7. Simulation results. (a) Phase voltages and currents. (b) Line voltages.

VI. SIMULATION AND EXPERIMENTAL VERIFICATION

To verify the performance of DFC-ANPC converter, a5-MVA three-phase, 10-kV, five-level model has been simulatedwith PSIM software. The model has been tested under differentsituations including high and low modulation indexes and dif-ferent modulation techniques, output powers, power factors etc.According to the obtained simulation results, the DFC-ANPC


Fig. 8. Simulation results. (a) FC voltages. (b) Neutral point voltage.

Fig. 9. Prototype of the DFC-ANPC converter and experimental setup.

Fig. 10. Experimental results. (a) Phase voltages and currents. (b) Linevoltages.

converter performs well in all the situations generating the ex-pected output waveform and keeping the capacitors voltagesbalanced. In this paper, the simulation results for a typical casewith parameters listed in Table III is presented. Fig. 7(a) showsthe five-level phase voltages and currents, and Fig. 7(b) showsthe nine-level line voltages with a THD of about 17%. The sixFCs’ voltages, shown in Fig. 8(a), are well balanced at 4 kVwith a ripple amplitude of about 5%. As shown in Fig. 8(b),despite the common-mode injection due to the applied modula-tion technique, the neutral point voltage with respect to dc link’snegative is fixed at 8 kV with a small ripple.

A small-scale three-phase prototype has been implemented toexperimentally verify the performance of the DFC-ANPC con-verter. Fig. 9 shows the implemented converter and experimentsetup. The switching signals are generated by a TMS320F28335DSP microcontroller and supplied to the switch modules througha buffering and dead time generation circuit. The experimenthas been setup with similar circuit parameters as the simulation,listed in Table III, except for the voltage that has been scaled


Fig. 11. Experimental results. (a) FCs voltages at startup transient. (b) FCsvoltages at steady state. (c) Neutral point voltage at steady state.

down by 40 times. Consequently, the currents and the powerare scaled down by 40 and 1600 times, respectively. However,the percentage of voltage ripple for FCs and the neutral pointremain the same.

The experimental five-level phase voltages and currents andthe nine-level line voltages are shown in Fig. 10. In practicethe FCs should be precharged to the target value either throughthe ac side or precharge circuitry to avoid overvoltage on theswitches at the startup transient. Yet the startup transient with-out precharging shown in Fig. 11(a) illustrates the FC voltagesevolving to their target value. The steady state FC voltages areshown in Fig. 11(b). It can be seen that the FCs voltages arebalanced at 100 V with a ripple of about 5%, similar to the sim-ulation case. For the neutral point voltage shown in Fig. 11(c),similar to the simulation, the ripple is very small. But an aver-age voltage drift of about 1.5 V can be observed that is due to asmall imbalance in the experimental setup. In this case, an activeneutral point voltage control can solve this issue [5], [23].

VII. CONCLUSION

In this paper, the operation of the DFC-ANPC topology hasbeen investigated and the associated modulation techniques havebeen presented and verified by simulation and experimental re-sults. Compared to the commercialized five-level FC-ANPCconverter, the DFC-ANPC converter under the proposed modu-lation method has the following features:

1) provides more even loss distribution among semiconduc-tor switches and thus higher power rating is expected;

2) eliminates the transient voltage balancing problem ofseries-connected switches;

3) decreases the switching loss and thus slight improvementin efficiency is expected;

4) can be extended to higher levels without transient voltagebalancing problem.

The comparison presented in this paper is mostly based onabductive reasoning and not quantified. For future work, a com-parative study of the FC-ANPC and DFC-ANPC thermal modelswill verify the thermal performance superiority and provide anestimation of the amount of extra power processing capability.

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Roozbeh Naderi (S’12) received the B.S. degree inelectrical engineering from the University of Mazan-daran, Babolsar, Iran, in 2005, and the M.S. degreein electrical engineering from the Iran University ofScience and Technology, Tehran, Iran, in 2009. Heis currently working toward the Ph.D. degree in theDepartment of Electrical Engineering and ComputerScience, University of California Irvine, CA, USA.

His current research interests include power elec-tronics circuits, multilevel converters, and energystorage systems.

Arash Khoshkbar Sadigh (S’09–M’15) received theB.S. and M.S. degrees (both with first-class Hons.) inelectrical engineering from the University of Tabriz,Tabriz, Iran, in 2007 and 2009, respectively, and thePh.D. degree in electrical engineering from the Uni-versity of California, Irvine, USA, in 2014.

He was with AranNagshAra Consultant Engineer-ing Company, Tabriz, from 2007 to 2010, where hewas involved in the design of power transmission anddistribution lines. During summer 2012 and 2013, hewas an Intern with the RTDS Advanced Technology

Laboratory, Southern California Edison. In 2015, he joined Extron Electronics,Anaheim, CA, USA, as a Power Electronics Design Engineer. He is the author orcoauthor of more than 50 journal and conference papers and one book chapter,and he holds one patent. His current research interests include power electronicscircuits, multilevel converters and their applications in power grid and system,power quality, and flexible ac transmission system devices.

Dr. Khoshkbar Sadigh was selected by the University of Tabriz as the Dis-tinguished Student in 2006. In 2007, he joined the Iran’s National Elites Foun-dation as he ranked second in the National Entrance Exam for graduate studyin electrical engineering with a major in power engineering. He was a recipientof an Outstanding Presentation Award from the Annual IEEE Applied PowerElectronics Conference and Exposition in 2013.

Keyue Ma Smedley (S’87–M’90–SM’97–F’08) re-ceived the B.S. and M.S. degrees in electricalengineering from Zhejiang University, Hangzhou,China, in 1982 and 1985, respectively, and the M.S.and Ph.D. degrees in electrical engineering from theCalifornia Institute of Technology, Pasadena, CA,USA, in 1987 and 1991, respectively.

She is currently a Professor in the Department ofElectrical Engineering and Computer Science, Uni-versity of California, Irvine (UCI), USA, the Direc-tor of the UCI Power Electronics Laboratory, and

a Cofounder of One-Cycle Control, Inc., Irvine. Her current research inter-ests include high-efficiency dc–dc converters, high-fidelity class-D power am-plifiers, single-phase and three-phase PFC rectifiers, active power filters, in-verters, V/VAR control, energy storage system, and utility-scale fault currentlimiters. She is an Inventor of One-Cycle Control and the Hexagram powerconverter. Her work has resulted in more than 160 technical publications,more than 10 U.S./international patents, two start-up companies, and numerouscommercial applications.

Dr. Smedley is a Recipient of the UCI Innovation Award in 2005. Herwork with One-Cycle Control, Inc., has won her the Department of the ArmyAchievement Award in the Pentagon in 2010.

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6476 IEEE TRANSACTIONS ON POWER …msrprojectshyd.com/upload/academicprojects...6476 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 Dual Flying Capacitor Active-Neutral-Point-Clamped