64 Bit MAC Document

8/18/2019 64 Bit MAC Document

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CHAPTER 1


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1.INTRODUCTION

1.0. INTRODUCTION:

MAC unit is an inevitable component in many digital signal processing (DSP)applications involving multiplications and/or accumulations. MAC unit is used for high

performance digital signal processing systems. he DSP applications include filtering!

convolution! and inner products.

Most of digital signal processing methods use nonlinear functions such as discrete

cosine transform (DC) or discrete "avelet transforms (D#). $ecause they are basically

accomplished by repetitive application of multiplication and addition! the speed of the

multiplication and addition arithmetic determines the e%ecution speed and performance of theentire calculation.

Multiplication&and&accumulate operations are typical for digital filters. herefore! the

functionality of the MAC unit enables high&speed filtering and other processing typical for

DSP applications. Since the MAC unit operates completely independent of the CP'! it can

process data separately and thereby reduce CP' load. he application lie optical

communication systems "hich is based on DSP ! reuire e%tremely fast processing of huge

amount of digital data. he *ast *ourier ransform (**) also reuires addition and

multiplication. +, bit can handle larger bits and have more memory.

A MAC unit consists of a multiplier and an accumulator containing the sum of the

previous successive products. he MAC inputs are obtained from the memory location and

given to the multiplier bloc. he design consists of +, bit modified #allace multiplier! -

bit carry save adder and a register.

1.1.LITERATURE SURVEY:

0e" multiplier design is proposed "hich reduces the number of partial products by12. his multiplier has been used "ith different adders available in literature to implement

multiplier accumulator (MAC) unit and parameters such as propagation delay! po"er consumed and

area occupied have been compared in each case.


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*rom the results! 3ogg tone adder has been chosen as it provided optimum values of delay

and po"er dissipation. 4ater! the results obtained have been compared "ith that of other multipliers

and it has been observed that the proposed multiplier has the lo"est propagation delay "hen

compared "ith Array and $ooth multipliers.

1.2.MAC OPERATION:

he Multiplier&Accumulator (MAC) operation is the ey operation not only in DSP

applications but also in multimedia information processing and various other applications. As

mentioned above! MAC unit consist of multiplier! adder and register/accumulator. 5n this

paper! "e used +, bit modified #allace multiplier. he MAC inputs are obtained from the

memory location and given to the multiplier bloc. his "ill be useful in +, bit digital signal

processor.

he input "hich is being fed from the memory location is +, bit. #hen the input is

given to the multiplier it starts computing value for the given +, bit input and hence the

output "ill be - bits. he multiplier output is given as the input to carry save adder "hich

performs addition.

he function of the MAC unit is given by the follo"ing euation6

*7 8Pi9i (-)

he output of carry save adder is -: bit i.e. one bit is for the carry (-bits; - bit).

hen! the output is given to the accumulator register. he accumulator register used in thisdesign is Parallel 5n Parallel


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Figure 16 $asic Architecture of MAC unit

1.3.DIFFERENT MULTIPLIERS:

An efficient multiplier should have follo"ing characteristics6&

Accuracy 6& A good multiplier should give correct result.

Speed 6& Multiplier should perform operation at high speed.

Area 6& A multiplier should occupies less number of slices and 4's.

Po"er 6& Multiplier should consume less po"er.

Multiplication process has three main steps6

-. Partial product generation.

. Partial product reduction.

=. *inal addition.

*or the multiplication of an n&bit multiplicand "ith an m bit multiplier! m partial

products are generated and product formed is n ; m bits long. >ere "e discuss about four

different types of multipliers "hich are


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-. $ooth multiplier.

. Combinational multiplier.

=. #allace tree multiplier.

,. Array multiplier.

1. Seuential multiplier.

1.3.1.B!" #u$!i%$ier:&

$ooth multiplication algorithm gives a procedure for multiplying binary integers in

signed &?s complement representation. *ollo"ing steps are used for implementing the booth

algorithm6&

4et @ and are t"o binary numbers and having m and n numbers of bits(m and n are

eual) respectively.

S!e% 1 M'(i)g *!" !'*$e6 5n booth table "e "ill tae four columns one column for multiplier second for previous first 4S$ of multiplier and other t"o (' and B) for partial

product accumulator (P).

-. *rom t"o numbers! choose multiplier (@) and multiplicand ().

. ae ?s complement of multiplicand ().

=. 4oad @ value in the table.

,. 4oad for @&- value.

1. 4oad in ' and B "hich "ill have product of @ at the end of the operation.

+. Mae n ro"s for each cycle because "e are multiplying m and n bits numbers.


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T'*$e.1. $ooth able.

S!e%2 B!" '$gri!"#6

$ooth algorithm reuires e%amination of the multiplier bits! and shifting of the partial

product(P). Prior to the shifting! the multiplicand may be added to P! subtracted from the P! or

left unchanged according to the follo"ing rules6

1. @i @i&- Shift only

- - Shift only

- Add to ' and shift

- Minus from ' and shift

2. ae ' B together and shift arithmetic right shift "hich preserves the sign bit of

?scomplement number. So! positive numbers and negative numbers remains positive and

negative respectively.

3. Circularly right shift @ because this "ill prevent us from using t"o registers for the @

value.

Eepeat the same steps until n no. of cycles are completed. 5n the end "e get the

product of @ and .


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1.3.2.C#*i)'!i)'$ Mu$!i%$ier:

Combinational Multipliers do multiplication of t"o unsigned binary numbers .his

multiplier is also used for the multiplication of t"o signed number. Fach bit of the multiplier

is multiplied against the multiplicand! the product is associated according to the position of

the bit "ithin the multiplier! and the resulting products are then added to form the final result.

Main advantage of binary multiplication is that the generation of intermediate products are

easy. 5f the multiplier bit is a -! the product is an correctly shifted copy of the multiplicandG if

the multiplier bit is a ! the product is simply .5n most of the systems combinational

multipliers are slo" and tae a lot of area.

1.3.3.+'$$',e Tree Mu$!i%$ier6

A #allace tree multiplier is an efficient hard"are implementation of a digital circuit

that multiplies t"o integers devised by an Australian computer scientist Chris #allace in-:+,. #allace tree reduces the no. of partial products and use carry select adder for the

addition of partial products.

F%ample of bitH bit #allace tree multiplier

5n this figure blue circle represent full adder and red circle represent the half adder.

#allace tree has three steps6&


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1. Multiply each bit of multiplier "ith same bit position of multiplicand. Depending on the

position of the multiplier bits generated partial products have different "eights.

2. Eeduce the number of partial products to t"o by using layers of full and half adders.

3. After second step "e get t"o ro"s of sum and carry! add these ro"s "ith conventional

adders.

F%planation of second step6&

As long as there are three or more ro"s "ith the same "eight add a follo"ing layer6

-. ae any three ro"s "ith the same "eights and input them into a full adder. he result "ill

be an output ro" of the same "eight i.e sum and an output ro" "ith a higher "eight for each

three input "ires i.e carry.

. 5f there are t"o ro"s of the same "eight left! input them into a half adder.

=. 5f there is Iust one ro" left! connect it to the ne%t layer.he advantage of the #allace tree is that there are only


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5n a seuential multiplier! themultiplication process is divided into some seuential

steps. 5n each step some partial products "ill begenerated! added to an accumulated partial

sum andpartial sum "ill be shifted to align the accumulated sum"ith partial product of ne%t

steps. herefore! each step of a seuential multiplication consists of three different operations

"hich are generating partial products! adding the generated partial products to the

accumulated partialsum and shifting the partial sum. *igure - sho"s partial product

generation and addition in a seuential multiplier.

Figure.1.1. Eo" by ro" addition in a seuential multiplier.

5n "hat follo"s! the terms multiplicand and multiplier refer to the first and second

operands of a given multiplication! respectively. 5n each multiplication step! one or more

multiples of the multiplicand are generated and added to the partial sum through a t"o& or

multi&operand addition operation. Seuential multipliers can tae a number of cloc cycles to

produce a result. hat?s "hy even they can "or on high cloc freuency! but the latency in

terms of absolute time get an output may be more or eual to that of combinational

multiplier. 5f the numbers "e "ant to multiply are small then acombinational multiplier is o!

as it is very easy to code.


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CHAPTER 2


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2.MODIFIED +ALLACE MULTIPLIER

2.0. INTRODUCTION:

A modified #all ace multiplier is an efficient hard"are implementation of digital

circuit multiplying t"o integers. Jenerally in conventional #allace multipliers many full

adders and half addersare used in their reduction phase. >alf adders do not reduce the

number of partial product bits.

herefore! minimiKing the number of half adders used in a multiplier reduction "ill

reduce the comple%ity. >ence! a modification to the #allace reduction is done in "hich the

delay is the same as for the conventional #allace reduction. he modified reduction method

greatly reduces the number of half adders "ith a very slight increase in the number of fulladders.

Eeduced comple%ity #all ace multiplier reduction consists of three stages. *irst stage

the 0 % 0 product matri% is formed and before the passing on to the second phase the product

matri% is rearranged to tae the shape of inverted pyramid. During the second phase the

rearranged product matri% is grouped into non&overlapping group of three as sho"n in the

figure ! single bit and t"o bits in the group "ill be passed on to the ne%t stage and three bits

are given to a full adder. he number of ro"s in the in each stage of the reduction phase is

calculated by the formula

r I;-7 Lr i/=;r Imod= ()

5f r I mod= 7 ! then r I; - 7 r/= (=)

5f the value calculated from the above euation for number of ro"s in each stage in

the second phase and the number of ro" that are fonned in each stage ofthe second phase

does not match! only then the half adder "ill be used. he final product of the second stage

"ill be in the height of t"o bits and passed onto the third stage. During the third stage the

output of the second stage is given to the carry propagation adder to generate the final output.hus +, bit modified #allace multiplier is constructed and the total number of stages

in the second phase is -.

As per the euation the number of ro" in each of the - stages "as calculated and the

use of half adders "as restricted only to the -th stage.


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he total number of half adders used in the second phase is and the total number of

full addersthat "as used during the second phase is slightly increased that in the conventional

#allace multiplier.

Since the +, bit modified #allace multiplier is difficult to represent! a typical l


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2.1.Bi)'r Aer N!'!i) ') O%er'!i):

As mentioned previously! adders in B4S5 digital systems use binary notation. 5n that

case! add is done bit by bit using $oolean euations.

Fig.2.1: 1&*i! H'$ Aer.

Consider a simple binary add "ith t"o n&bit inputs AG$ and a one&bit carry&in cin

along "ith n&bit output S.

S 4 A 5 B 5 Ci)

#here A 7 an&-! an&NNaG $ 7 bn&-! bn&NNb.

he 5 in the above euation is the regular add operation. >o"ever! in the binary

"orld! only $oolean algebra "ors. *or add related operations! A0D! alf adder! "hich taes only input bits. he solid line highlights the critical path! "hich


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indicates the longest path from the input to the output. Fuation of ci;- can be e%tended to

perform full add operation! "here there is a carry input.

Si 4 'i 6 *i 6 ,i

Ci 5 1 4 'i . *i 5 'i . ,i 5 *i . ,i

Fig.2.2: 1&*i! Fu$$ Aer.A *ull adder can be built based on Fuation above. he bloc diagram of a -&bit full

adder is sho"n in *ig... he full adder is composed of half adders and an ere these t"o terms are separated in order to clarify the

concepts. *or e%ample! for 4ing adders! only pi is used as carry&propagate.

he single bit carry generate/propagate can be e%tended to group version J and P.

he follo"ing euations sho" the inherent relations.


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7i : ( 4 7i : 8 5 Pi : 8 . 78 9 1 : (

Pi : ( 4 Pi : 8 . P8&1:(

#here i 6 denotes the group term from i through .

'sing group carry generate/propagate! carry can be e%pressed as e%pressed in the

follo"ing euation.

Ci 5 1 4 7i : 8 5 Pi : 8 . C8

2.2. Ri%%$e A'rr Aer:

Eipple carry adder is an n&bit adder built from full adders. *ig .- sho"s a ,&bit ripple

carry adder.


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De$' :

he latency of a ,&bit ripple carry adder can be derived by considering the "orst&case

signal propagation path. #e can thus "rite the follo"ing e%pressions6

TRCA&-*i! 4 TFAA0


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generated. Similarly if @ ! a carry is generated if and only if the previous bit&position

generates a carry.

RC? is initial carry!TSU and TCoutU are output sum and carry respectively! then $oolean

e%pression for calculating ne%t carry and addition is6

Pi 4 i r Yi && Carry Propagation

7i 4 i ') Yi && Carry Jeneration

Ci 5 1 4 7i r Pi ') Ci; && 0e%t Carry

Si 4 i r Yi r Ci && Sum Jeneration

hus! for ,&bit adder! "e can e%tend the carry! as sho"n belo"6

C1 4 70 5 P0 C0

C2 4 71 5 P1 C1 4 71 5 P1 70 5 P1 P0 C0

C3 4 72 5 P2 71 5 P2 P1 70 5 P2 P1 P0 C0

C- 4 73 5 P3 72 5 P3 P2 71 5 P3 P2 P1 705 P3 P2 P1 P0 C0

As "ith many design problems in digital logic! "e can mae tradeoffs bet"een area

and performance (delay). 5n the case of adders! "e can create faster (but larger) designs than

the ECA. he Carry 4oo ahead Adder (C4A) is one of these designs (there are others too!

but "e "ill only loo at the C4A).

Dr'@*',( :

*or long bit length! a carry loo&ahead adder is not practical! but a hierarchical

structure one can improve much. he disadvantage of C4A is that the carry logic bloc gets

very complicated for more than ,&bits. *or that reason! C4As are usual implemented as ,&bit

modules and are used in a hierarchical structure to realiKe adders that have multiples of ,&

bits.


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CHAPTER 3

3.CARRY SAVE ADDER


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3.0. INTRODUCTION:

he carry&save adder reduces the addition of = numbers to the addition of numbers.

he propagation delay is = gates regardless of the number of bits. he carry&save unitconsists of n full adders! each of "hich computes a single sum and carries bit based solely on

the corresponding bits of the three input numbers.

he entire sum can then be computed by shifting the carry seuence left by one place

and appending a to the front (most significant bit) of the partial sum seuence and adding

this seuence "ith ECA produces the resulting n;-&bit value.

his process can be continued indefinitely! adding an input for each stage of full

adders! "ithout any intermediate carry propagation. hese stages can be arranged in a binary

tree structure! "ith cumulative delay logarithmic in the number of inputs to be added! and

invariant of the number of bits per input. he main application of carry save algorithm is!

"ell no"n for multiplier architecture is used for efficient CM


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As sho"n in the *ig..,! here "e are computing sum of t"o ,&bit binary numbers! so

"e tae , full adders at first stage. Carry save unit consists of , full adders! each of "hich

computes single sum and carry bit based only on the corresponding bits of the t"o input

numbers. 4et @ and are t"o ,&bit numbers and produces partial sum and carry as S and C

as sho"n in the belo" 6

Si 4 i r Yi Ci 4 i ') Yi

he final addition is then computed as6

-. Shifting the carry seuence C left by one place.

. Placing a to the front (MS$) of the partial sum seuence S.

=. *inally!a ripple carry adder is used to add these t"o together and computing the resulting

sum.

C'rr S'e Aer C#%u!'!'i) :

: 1 0 0 1 1

Y: 1 1 0 0 1

: 5 0 1 0 1 1

S: 0 0 0 0 1

C: 5 1 1 0 1 1

SUM: 1 1 0 1 1 1

5n this design - bit carry save adder is used since the output of the multiplier is -

bits (0). he carry save adder minirniKe the addition from =numbers to numbers. he

propagation delay is =gates despite of the number of bits.

he carry save adder contains n full adders! computing a single sum and carries bit

based mainly on the respective bits of the three input numbers. he entire sum can be

calculated by shifting the carry seuence left by one place and then appending a to most

significant bit of the partial sum seuence.

0o" the partial sum seuence is added "ith ripple carry unit resulting in n ; - bit

value. he ripple carry unit refers to the process "here the carryout of one stage is fed

directly to the carry in of the ne%t stage. his process is continued "ithout adding any

intermediate carry propagation. Since the representation of - bit carry save adder is

infeasible! hence a typical bit carry save adder is sho"n in the figure =.


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>ere "e are computing the sum of t"o - bit binary numbers! then - half adders

at the first stage instead of - full adder.

herefore ! carry save unit comprises of - half adders! each of "hich computes

single sum and carry bit based only on the corresponding bits of the t"o input numbers.

Figure:3.1 bit carry save adder

5f % and y are supposed to be t"o - bit numbers then it produces the partial

products and carry as S and C respectively.

Si 7 %i -V yi (,)

Ci 7 %i yi (1)

During the addition of t"o numbers using a half adder! t"o ripple carry adder is used.

his is due the fact that ripple carry adder cannot compute a sum bit "ithout "aiting for the previous carry bit to be produced! and hence the delay "ill be eual to that of n full adders.

>o"ever a carry&save adder produces all the output values in parallel! resulting in the

total computation time less than ripple carry adders. So! Parallel 5n Parallel


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3.1. C'rr Se$e,! Aer

A carry&select adder is divided into sectors! each of "hich W e%cept for the least&

significant Wperforms t"o additions in parallel! one assuming a carry&in of Kero! the other a

carry&in of one. A four bit carry select adder generally consists of t"o ripple carry adders and

a multiple%er. he carry&select adder is simple but rather fast! having a gate level depth of


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he carry select adder comes in the category of conditional sum adder. Conditional

sum adder "ors on some condition. Sum and carry are calculated by assuming input carry

as - and prior the input carry comes.

#hen actual carry input arrives! the actual calculated values of sum and carry are

selected using a multiple%er.

he conventional carry select adder consists of / bit adder for the lo"er half of the

bits i.e. least significant bits and for the upper half i.e. most significant bits (MS$?s) t"o /bit

adders.

5n MS$ adders one adder assumes carry input as one for performing addition and

another assumes carry input as Kero.

he carry out calculated from the last stage i.e. least significant bit stage is used to

select the actual calculated values of outputcarry and sum. he selection is done by using a multiple%er. his techniue of dividing adder

in to stages increases the area utiliKation but addition operation fastens.


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CHAPTER -


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-.INTRODUCTION OF VLSI

-.0. INTRODUCTION:

Bery&large&scale integration (B4S5) is the process of creating integrated circuits bycombining thousands of transistor&based circuits into a single chip. B4S5 began in the -:Ys

"hen comple% semiconductor and communication technologies "ere being developed. he

microprocessor is a B4S5 device. he term is no longer as common as it once "as! as chips

have increased in comple%ity into the hundreds of millions of transistors.

-.1.Oerie@:

he first semiconductor chips held one transistor each. Subseuent advances addedmore and more transistors! and! as a conseuence! more individual functions or systems "ere

integrated over time. he first integrated circuits held only a fe" devices! perhaps as many as

ten diodes! transistors! resistors and capacitors! maing it possible to fabricate one or more

logic gates on a single device. 0o" no"n retrospectively as Zsmall&scale integrationZ (SS5)!

improvements in techniue led to devices "ith hundreds of logic gates! no"n as large&scale

integration (4S5)! i.e. systems "ith at least a thousand logic gates. Current technology has

moved far past this mar and todays microprocessors have many millions of gates and

hundreds of millions of individual transistors.

At one time! there "as an effort to name and calibrate various levels of large&scale

integration above B4S5. erms lie 'ltra&large&scale 5ntegration ('4S5) "ere used. $ut the

huge number of gates and transistors available on common devices has rendered such fine

distinctions moot. erms suggesting greater than B4S5 levels of integration are no longer in

"idespread use. Fven B4S5 is no" some"hat uaint! given the common assumption that all

microprocessors are B4S5 or better.

As of early ! billion&transistor processors are commercially available! an e%ample

of "hich is 5ntels Montecito 5tanium chip.


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his is e%pected to become more commonplace as semiconductor fabrication moves

from the current generation of +1 nm processes to the ne%t ,1 nm generations ("hile

e%periencing ne" challenges such as increased variation across process corners). Another

notable e%ample is 0B5D5A?s series JP'.

his microprocessor is uniue in the fact that its -., $illion transistor count! capable

of a teraflop of performance! is almost entirely dedicated to logic (5taniums transistor count

is largely due to the ,M$ 4= cache). Current designs! as opposed to the earliest devices! use

e%tensive design automation and automated logic synthesis to lay out the transistors! enabling

higher levels of comple%ity in the resulting logic functionality. Certain high&performance

logic blocs lie the SEAM cell! ho"ever! are still designed by hand to ensure the highest

efficiency (sometimes by bending or breaing established design rules to obtain the last bit of performance by trading stability).

-.2 VLSI:

B4S5 stands for ZBery 4arge Scale 5ntegrationZ. his is the field "hich

5nvolves pacing more and more logic devices into smaller and smaller areas.

-. Simply "e say 5ntegrated circuit is many transistors on one chip.

. Design/manufacturing of e%tremely small! comple% circuitry using modified

semiconductor material.

=. 5ntegrated circuit (5C) may contain millions of transistors! each a fe" mm in siKe.

,. Applications "ide ranging6 most electronic logic devices.

-.3 VLSI Deig) F$@:

-.3.1 Digi!'$ Cir,ui!:

Digital 5Cs of SS5 and MS5 types have become universally standardiKed and have

been accepted for use. #henever a designer has to realiKe a digital function! he uses a

standard set of 5Cs along "ith a minimal set of additional discrete circuitry.


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Clk

On

B

Consider a simple e%ample of realiKing a function as6 9 n;- 7 9 n ; (A $)

>ere on! A! and $ are $oolean variables! "ith 9 n being the value of 9 at the nth

time step. >ere A $ signifies the logical A0D of A and $G the R;? symbol signifies the logical


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System requirements

Circuit requirements

ICsOther components

PCB layout

Wiring & testing

Final circuit

[ 5dentify the maIor functional blocs reuired lie timer! DMA unit! register file etc.! say asin the design of a processor.

[ #henever a function can be realiKed using a standard 5C! use the same Wfor e%ample programmable counter! mu%! demu%! etc.

[ #henever the above is not possible! form the circuit to carry out the bloc functions usingstandard SS5 W for e%ample gates! flip&flops! etc.

[ 'se additional components lie transistor! diode! resistor! capacitor! etc.! "herever essential.

Fig -.16 Process flo"chart


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[ *unctional mismatch6 he realiKed and e%pected functions are different.


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• Farly Ys 4arge Scale 5ntegration (4S5)

• -s of transistor on a chip

• Farly s B4S5 -!s of transistors on a

• chip (later -!s no" -!!s)

'ltra 4S5 is sometimes used for -!!s

SS5 & Small&Scale 5ntegration (&-)

MS5 & Medium&Scale 5ntegration (-&-=)

4S5 & 4arge&Scale 5ntegration (-=&-1)

B4S5 & Bery 4arge&Scale 5ntegration (-1&-Y)

'4S5 & 'ltra 4arge&Scale 5ntegration (]7-Y)

-.3.2 VLSI Deig)

he comple%ity of B4S5s being designed and used today maes the manual approach

to design impractical. Design automation is the order of the day. #ith the rapid technological

developments in the last t"o decades! the status of B4S5 technology is characteriKed by the

follo"ing6

[ A steady increase in the siKe and hence the functionality of the 5Cs.

[ A steady reduction in feature siKe and hence increase in the speed of operation as "ell asgate or transistor density.

[ A steady improvement in the predictability of circuit behavior.

[ A steady increase in the variety and siKe of soft"are tools for B4S5 design.


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he above developments have resulted in a proliferation of approaches to B4S5 design. #e

briefly describe the procedure of automated design flo". he aim is more to bring out the

role of a >ard"are Description 4anguage (>D4) in the design process. An abstraction based

model is the basis of the automated design.

-.3.3 A*!r',!i) Me$

he model divides the "hole design cycle into various domains. #ith such an

abstraction through a division process the design is carried out in different layers.

he designer at one layer can function "ithout bothering about the layers above or

belo". he thic horiKontal lines separating the layers in the figure signify the

compartmentaliKation.

As an e%ample! let us consider design at the gate level. he circuit to be designed

"ould be described in terms of truth tables and state tables. #ith these as available inputs! he

has to e%press them as $oolean logic euations and realiKe them in terms of gates and flip&

flops. 5n turn! these form the inputs to the layer immediately belo". CompartmentaliKation of

the approach to design in the manner described here is the essence of abstractionG it is the

basis for development and use of CAD tools in B4S5 design at various levels.

he design methods at different levels use the respective aids such as $oolean

euations! truth tables! state transition table! etc. $ut the aids play only a small role in the

process. o complete a design! one may have to s"itch from one tool to another! raising the

issues of tool compatibility and learning ne" environments.

-.- ASIC Deig) F$@

As "ith any other technical activity! development of an AS5C starts "ith an idea andtaes tangible shape through the stages of development. he first step in the process is to

e%pand the idea in terms of behavior of the target circuit. hrough stages of programming!

the same is fully developed into a design description W in terms of "ell defined standard

constructs and conventions.


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Microprocessors, me

#egisters, A$%, multipliers

ates, 'ip('ops

)ransistors, $, #, C

ometric o*+ects

Behavioral domain

I!ea

esign !escription

SynthesisSimulation

Physical !esign

he design is tested through a simulation processG it is to chec! verify! and ensure

that "hat is "anted is "hat is described. Simulation is carried out through dedicated tools.

#ith every simulation run! the simulation results are studied to identify errors in the

design description. he errors are corrected and another simulation run carried out.Simulation and changes to design description together form a cyclic iterative process!

repeated until an error&free design is evolved

Fig-.2: Design domain and levels of abstraction


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Fig -.3: MaIor activities in AS5C design

.

Design description is an activity independent of the target technology or

manufacturer. 5t results in a description of the digital circuit. o translate it into a tangible

circuit! one goes through the physical design process. he same constitutes a set of activitiesclosely lined to the manufacturer and the target technology.

-.-.1 Deig) De,ri%!i)

he design is carried out in stages. he process of transforming the idea into a

detailed circuit description in terms of the elementary circuit components constitutes design

description. he final circuit of such an 5C can have up to a billion such componentsG it is

arrived at in a step&by&step manner. he first step in evolving the design description is to

describe the circuit in terms of its behavior. he description loos lie a program in a high

level language lie C.


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Fig -.-. ASIC Deig) ') Dee$%#e)! $@


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-.-.- S)!"ei

#ith the availability of design at the gate (s"itch) level! the logical design is

complete. he corresponding circuit hard"are realiKation is carried out by a synthesis tool.

"o common approaches are as follo"s6

[ he circuit is realiKed through an *PJA. he gate level design description is the starting

point for the synthesis here. he *PJA vendors provide an interface to the synthesis tool.

hrough the interface the gate level design is realiKed as a final circuit. #ith many synthesis

tools! one can directly use the design description at the data flo" level itself to realiKe the

final circuit through an *PJA. he *PJA route is attractive for limited volume production or

a fast development cycle.

[ he circuit is realiKed as an AS5C. A typical AS5C vendor "ill have his o"n library of basic

components lie elementary gates and flip&flops. Fventually the circuit is to be realiKed by

selecting such components and interconnecting them conforming to the reuired design. his

constitutes the physical design. $eing an elaborate and costly process! a physical design may

call for an intermediate functional verification through the *PJA route. he circuit realiKed

through the *PJA is tested as a prototype. 5t provides another opportunity for testing the

design closer to the final circuit.

-.-./ P"i,'$ Deig)

A fully tested and error&free design at the s"itch level can be the starting point for a

physical design. 5t is to be realiKed as the final circuit using (typically) a million components

in the foundry?s library. he step&by&step activities in the process are described briefly as

follo"s6

[ System partitioning6 he design is partitioned into convenient compartments or functional

blocs.


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[ *loor planning6 he positions of the partitioned blocs are planned and the blocs are

arranged accordingly. he procedure is analogous to the planning and arrangement of

domestic furniture in a residence. $locs "ith 5/< pins are ept close to the peripheryG those

"hich interact freuently or through a large number of interconnections are ept close

together! and so on. Partitioning and floor planning may have to be carried out and refined

iteratively to yield best results.

[ Placement6 he selected components from the AS5C library are placed in position on the

TSilicon floor.U 5t is done "ith each of the blocs above.

[ Eouting6 he components placed as described above are to be interconnected to the rest of

the bloc6 5t is done "ith each of the blocs by suitably routing the interconnects.


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CHAPTER /


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/.VERILO7

/.0 INTRODUCTION:

• Berilog synthesis tools can create logic&circuit structures directly from verilog

behavioral description and target them to a selected technology for realiKation

(5.e!translate verilog to actual hard"are).• 'sing verilog ! "e can design !simulate and synthesis anything from a simple

combinational circuit to a complete microprocessor on chip.• Berilog >D4 has evolved as a standard hard"are description language. Berilog >D4

offers many useful features for hard"are design.• Berilog >D4 is a general&purpose hard"are description language that is easy to learn

and easy to use. 5t is similar in synta% to the C programming language. Designers"ith C programming e%perience "ill find it easy to learn Berilog >D4.

• Berilog >D4 allo"s different levels of abstraction to be mi%ed in the same model.

hus! a designer can define a hard"are model in terms of s"itches! gates! E4! or

behavioral code. Also! a designer needs to learn only one language for stimulus and

hierarchical design.• Most popular logic synthesis tools support Berilog >D4. his maes it the language

of choice for designers.

• All fabrication vendors provide Berilog >D4 libraries for post logic synthesissimulation. hus! designing a chip in Berilog >D4 allo"s the "idest choice of

vendors.• he Programming 4anguage 5nterface (P45) is a po"erful feature that allo"s the user

to "rite custom C code to interact "ith the internal data structures of Berilog.

Designers can customiKe a Berilog >D4 simulator to their needs "ith the P45.

/.1.PRO7RAM STRUCTURE:

• he basic unit and programming in verilog is UM


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• he rest of the module contains statements that specify the operation of the module

output and internal signals.• Berilog is a case&sensitive language lie C. hus sense! Sense! SF0SF! sF0se!Netc.!

are all treated as different entities / uantities in Berilog.

SYNTA:

Module ModuleO0ame( P


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#u$e signifies the beginning of a module definition.

e)#u$esignifies the end of a module definition.

/.2.IDENTIFIERS:

Any program reuires blocs of statements! signals! etc.! to be identified "ith an

attached nametag. Such nametags are identifiers. 5t is good practice for us to use identifiers!

closely related to the significance of variable! signal! bloc! etc.! concerned. his eases

understanding and debugging of any program.

e.g.! cloc! enable! gateO-! . . .etc

here are some restrictions in assigning identifier names. All characters

of the alphabet or an underscore can be used as the first character. Subseuent characters can

be of alphanumeric type! or the underscore (O)! or the dollar (^) sign .

*or e%ample

• name! Oname. 0ame! name-! nameO^! . . . all these are allo"ed asidentifiers• name aanot allo"ed as an identifier because of the blan ( TnameU and TaaUare

interpreted as t"o different identifiers)•

^name

not allo"ed as an identifier because of the presence of T^U as thefirstcharacter.-Oname not allo"ed as an identifier! since the numeral T-U is the first

character _name not allo"ed as an identifier because of the presence of the character

T_U.• A;b not allo"ed as an identifier because of the presence of the character T;U.

An alternative format maes it is possible to use any of the printable ASC55

characters in an identifier. Such identifiers are called Tescaped identifiersUG they have to start

"ith the bacslash (V) character.

he character set bet"een the first bacslash character and the first "hite

space encountered is treated as an identifier. he bacslash itself is not treated as a character

of the identifier concerned.

F%amples


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Vb7c

Vcontrol&signal

Vlogic

Vabc // >ere the combination TabcU forms the identifier.

5t is preferable to use the former type of identifiers and avoid the escaped identifiersG they

may be reserved for use in files "hich are available as inputs to the design from other CAD

tools.

/.3.+HITE SPACE CHARACTERS:

$lans (Vb)! tabs (Vt)! ne"lines (Vn)! and form feed form the "hite spacecharacters in Berilog. 5n any design description the "hite space characters are included to

improve readability. *unctionally! they separate legal toens. hey are introduced bet"een

ey"ords! ey"ord and an identifier! bet"een t"o identifiers! bet"een identifiers and

operator symbols! and so on. #hite space characters have significance only "hen they appear

inside strings.

COMMENTS

5t is a healthy practice to comment a design description liberally W as "ith any

other program. Comments are incorporated in t"o "ays. A single line comment begins "ith

T//U and ends "ith a ne" line! and for multiple comments starts "ith TV`U and ends "ithU`VU.

/.-.PORT DECLERATION:

Berilog module declaration begins "ith a ey"ord UmoduleU and ends

"ithUendmoduleU. he input and output ports are signals by "hich the module

communicates "ith each others.


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S)!':

5nput identifierNNNNNN..identifierG


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4


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7 (not eual to)

#ire and reg variables are positive hus (&=?b-) 7 7 =?b--- and (&=d-)]=d--.

>o"ever for integers &-Q +.

F%ample

if (% 7 7 y) e 7 -G

else e 7 G

// Compare in ?s complimentG a]b

reg L=6 a!bG

if (aL=7 7 bL=) aL6 ] bL6G

else bL=G

Bi!&@ie O%er'!r:

$it&"ise operators do a bit&by&bit comparison bet"een t"o operands. >o"ever

seeTEeduction


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(logical 0


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S"i! O%er'!r

Shift operators shift the first operand by the number of bits specified by the second operand.

Bacated positions are filled "ith Keros for both left and right shifts (here is no sign

e%tension).

QQ (shift left)

]] (shift right)

F%ample6

assign c 7 a QQ G /` c 7 a shifted left bitsG

vacant positions are filled "ith ?s `/

C),'!e)'!i) O%er'!r:

he concatenation operator combines t"o or more operands to form a larger vector

(concatenation)

F%ample 6

"ire L-6 a! bG "ire L6 %G "ire L=G y! G

assign % 7 -?b! aG // %L7! %L-7aL-! %L7aL

assign y 7 a! bG /` yL=7aL-! yL7aL! yL-7bL-!

yL7bL `/

assign cout! y 7 % ; G // Concatenation of a result

Re%$i,'!i) O%er'!r:

he replication operator maes multiple copies of an item.


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nitem (n fold replication of an item)

F%ample 6

"ire L-6 a! bG "ire L,6 %G

assign % 7 -?b! aG // Fuivalent to % 7 !!a

assign y 7 a! =bG //Fuivalent to y 7 a!a!b!b

O%er'!r Pre,ee),e:

he belo" table sho"s the precedence of operators from highest to lo"est.


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.


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T'*$e /.2:


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n?*ddd...! "here

n & integer representing number of bits

* & one of four possible base formats6

b (binary)! o (octal)! d (decimal)!

h (he%adecimal). Default is d.

dddd & legal digits for the base format.

• 4iterals "ritten "ithout a siKe indicator default to =&bits or the "ord "idth used by

the simulator program! this may cause errors! so "e should careful "ith unsiKed

literals.

F%ample 6

Ttime isU// string literal

+Y // =&bit decimal number

?b- // &bit binary

?h$=+*// &bit he%adecimal number

Ro+ // =&bit octal number

NET6

Berilog actually has t"o classes of signals

-. nets.

. variables.


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• 0ets represent connections bet"een hard"are elements. \ust as in real circuits! nets

have values continuously driven on them by the outputs of devices that they are

connected to.• he default net type is "ire! any signal name that appears in a module input /output

list! but not in a net declaration is assumed to be type "ire.• 0ets are one&bit values by default unless they are declared e%plicitly as vectors. he

terms "ire and net are often used interchangeably.• 0ote that net is not a ey"ord but represents a class of data types such as "ire! "and!

"or! tri! triand! trior! trireg! etc. he "ire declaration is used most freuently.• he synta% of verilog net declaration is similar to an input/output declaration.

Synta%6

#ire identifier !NNNN.. identifierG

#ire Lmsb6lsb identifier !NNNN.. identifierG

tri identifier !NNNN.. identifierG

tri Lmsb6lsb identifier !NNNN.. identifierG

• he ey"ord tri has a function identical to that of "ire. #hen a net is driven by more

than one tri&state gate! it is declared as tri rather than as "ire. he distinction is for better clarity.

VARIABLE:

• Berilog variables stores the values during the program e%ecution! and they need not

have

Physical significance in the circuit.

• hey are used in only procedural code (i.e!behavioral design).A variable value can be

used ina e%pression and can be combined and assign to other variables! as in

conventional soft"are programming language.• he most commonly used variables are EFJ and 50FJFES.


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• Eegisters represent data storage elements. Eegisters retain value until another value is

placed onto them. Do not confuse the term registers in Berilog "ith hard"are

registers.• 5n Berilog! the term register merely means a variable that can hold a value. 'nlie a

net! a register does not need a driver. Berilog registers do not need a cloc as

hard"are registers do.• Balues of registers can be changed anytime in a simulation by assigning a ne" value

to the register. Eegister data types are commonly declared by the ey"ord reg.

Synta%6

Eeg identifier !NNNN.identifierG

Eeg Lmsb6lsb identifier!NNNN.identifierG

5nteger identifier !NNNN.identifierG

• A register variable is a single bit or vector of bits ! the value of -&bit reg variable is

al"ays !-!@!. the main use of reg variables is to store values in Berilog procedural

code.• An integer variable value is a=&bit or larger integer !depending on the "ord length on

the "ord length used by simulator .An integer variable is typically used to control a

repetitive statements !such as loop! in Berilog procedural code.• he difference bet"een Berilog net?s and variables is subtle. A variable value can

change only "ithin procedural code "ith in a module! it cannot be changed fromoutside the module.

PARAMETER:

Berilog provides a facility for defining named constants "ithin a module !to

improve readability and maintainability of code. he parameter declaration is

Synta%6

Parameter identifier 7valueG

Parameter identifier 7value!

: :


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identifier 7valueG

• An identifier is assigned to a constant value that "ill be used in place of the

identifier throughout the current module.•

Multiple constants can be defined in a single parameter declaration using a comma W separated list of arguments.

• he value in the parameter declaration can be simple constant !or it can be a constant

e%pression.• An e%pression involving multiple operators and constants including other

parameters !that yields a constant result at compile time. he parameter scope is

limited to that module in "hich it is defined.

/.J.ARRAYS:

Arrays are allo"ed in Berilog for reg! integer! time! and vector register data

types. Arrays are not allo"ed for real variables. Arrays are accessed by QarrayOname]

LQsubscript]. Multidimensional arrays are not permitted in Berilog.

Synta%6

Eeg identifier Lstart6endG

Eeg Lmsb6lsb identifier Lstart6endG

5nteger identifier Lstart6end G

F%ample6

integer count L6 Y G 5 5 An array of count variables

reg boolL=-6G 55 Array of = one&bit boolean register variables

time ch&pointL-6-G 55 Array of - time checpoint variables

reg L,6 portOid L6 Y \ G I I Array of portOidsG each portOid is 1 bi ts

"ide

integer matri%L,6 L,6\G 5lrllegaldeclaration.Multidimensional array.


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5t is important not to confuse arrays "ith net or register vectors. A vector

is a single element that is n&bits "ide. S:

During the simulation of any design! a number of activities are to be

carried out to monitor and control simulation. A number of such tass are provided / available

in Berilog. Some other tass serve other functions. >o"ever! a fe" of these are used

commonlyG these are described here. he T^U symbol identifies a system tas. A tas has the

format

^Qey"ord]

i%$':

#hen the system encounters this tas! the specified items are displayed in the formats

specified and the system advances to a ne" line. he structure! format! and rules for these are

the same as for the TprintfU / TscanfU function in C. Eefer to a standard te%t in TCU language

for the te%t formatting codes in common usage LJottfried.

F%amples

^display (The value of a is 6 a 7 ! 2dU! a)G

F%ecution of this line results in printing the value of a as a decimal

number (specified by T2dU). he string present "ithin the inverted commas specifies this.hus if a has the value =.1! "e get the display he value of a is 6 a 7 =.1.

After printing the above line! the system advances to the ne%t line.

^displayG /` his is a display tas "ithout any arguments. 5t advances output to a ne" line. `/


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#)i!r:

he ^monitor tas monitors the variables specified "henever any one of

those specified changes. During the running of the program the monitor tas is invoed and

the concerned uantities displayed "henever any one of these changes. *ollo"ing this! thesystem advances to the ne%t line. A monitor statement need appear only once in a simulation

program.

All the uantities specified in it are continuously monitored. 5n contrast!

the ^display command displays the uantities concerned only once W that is! "hen the

specific line is encountered during e%ecution. he format for the ^monitor tas is identical to

that of the ^display tas.

E'#%$e

^monitor (The value of a is 6 a 7 ! 2dU! a)G

#ith the tas! "henever the value of a changes during e%ecution of a program! its ne" value

is printed according to the format specified. hus if the value of a changes to ., at any time

during e%ecution of the program! "e get the follo"ing display on the monitor.

he value of a is6 a 7 .,.

T'( r C)!r$ Si#u$'!i):

"o system tass are available for control of simulation6

i)i" tas! "hen encountered! e%its simulation. Control is reverted to the


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Continuous assignment statement allo"s to describe a combinational

circuit in terms of the flo" of data and operations on the circuit. his style is called Tdataflo"

design or descriptionU. he basic synta% of a continuous Wassignment statement in Berilog is

S)!':

Assign net&name7e%pressionG

Assign net&nameLbit&inde%7e%pressionG

Assign net&nameLmsb6lsb7e%pressionG

Assign net&concatenation 7e%pressionG

• TAig)U is the ey"ord carrying out the assignment operation. his type of assignment is called a continuous assignment.

• he ey"ord Tassign Uis follo"ed by the name of a net! then anU7Usign and finally an

e%pression giving the value to be assigned• he order continuousWassignment statements in a module doesn?t matter .if the last

statement changes a net value used by the first statement !then the simulator go bac

to that first statement and update it?s result according to the net that Iust changed.• he continuous assignment statement evaluates the value of its right hand side and

assign it to the left hand side .in simulation! the assignment occur in Kero simulationtime.

• 5f a module contains t"o statements Tassign @7U and Tassign 7@U! then the

simulation "ill loop TforeverU(until the simulation times out).

*or e%ample6

'ig) c 7 a bG

•

a and b are operands W typically single&bit logic variables.• TU is a logic operator. 5t does the bit&"ise A0D operation on the t"o• operands a and b.• T7U is an assignment activity carried out.• c is a net representing the signal "hich is the result of the assignment.

5n general! an operand can be of any one of the follo"ing types6


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• A constant number Lincluding real.• 0et of a scalar or vector type including part of a vector.• Eegister variable of a scalar or vector type including part of a vector.• Memory element.• A call to a function that returns any of the above. he function itself can be a

user&defined or of a system type

/.10.STUCTURAL DESI7N OR;7ATE LEVEL MODELIN7 :

• Structural Design 5s the Series of Concurrent Statement .he Most 5mportant

Concurrent Statement 5n the module covered lie instance statements! continuous

Wassignment statement and al"ays bloc. hese gives rise to three distinct styles

of circuit design and description.• Statement of these types! and corresponding design styles! can be freely

intermi%ed "ithin a Berilog module declaration.• Fach concurrent statement in a Berilog module Te%ecutesU simultaneously "ith

other statements in the same module declaration .• 5n Berilog module! if the last statement updates a signal that is used by the first

statement! then the simulator go bac to that first statement and updates its result.

.• 5n fact! the simulator "ill propagating changes and updating results until the

simulated circuit stabiliKes.• 5n structural design style! the circuit description or design individual gates and

other components are instantiated and connected to each other using nets.• Berilog has several built in gate types! the names of these gates are reserved

"ords!some of these are

And %or bufif

0and %nor bufif-


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0or not notif-

S)!' Veri$g i)!'),e !!e#e)!:

ComponentOname instance&identifier(e%pressionNNNNN

e%presssion)G

ComponentOname instance&identifier (. port&name(e%pression)!

: :

. port&name(e%pression))G

B'i, g'!e %ri#i!ie i) Veri$g @i!" e!'i$:

Ru$e r e,ii)g !"e u!%u! '$ue g'!e %ri#i!ie r iere)! i)%u! ,#*i)'!i):


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• Jates and other components are instantiated in an inastance statement.the

statement gives the name of the component !such as TandU!follo"ed by an

identifier for this particular instance !follo"ed by an parenthesis list that

associates component part(inputs and outputs )"ith an e%pression.• "o different formats are allo"ed for the port Wassociated list. he first

format depends on the order in "hich port names appears in the original

component definition.•

he local e%pression are listed in the same order as the ports to "hich they aresupposed to connect.

• *or built in ! multi&input gates !the defined port name order is (output!

inputNNN.)and the order among the multiple inputs doesn?t matter.

I)!')!i'!i) ') u),!i)'$ e!'i$ !ri&!'!e *uer %ri#i!ie:


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he follo"ing observations are common to all the tri&state buffer primitives6

• 5f the control signal has a value that corresponds to the buffer being on! t"o

possibilities e%ist6 he output has the same value as the input if the input is or -. he output is at % other"ise (i.e.! if the input is % or K).

• 5f the control signal has a value that corresponds to the control signal being off! the

output is at K state irrespective of the value of the input.• 5f the control signal is at % or K! three possibilities arise6

5f the input is at % or K! the output is at %. 5f the input is at state! the output is 4 for bufif- and bufif. 5t is at > for

notif- and notif. 5f the input is at - state! the output is > for bufif- and bufif. 5t is at 4 for

notif- and notif.

0ote that > corresponds to - or K state "hile 4 corresponds to or K state.

/.11.BEHAVIORAL MODELIN7:


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$ehavioral level modeling constitutes design description at an abstract

level. ere

direct description of the design is not a primary consideration in the Berilog standard. Eather!

fle%ibility and versatility in describing the design are in focus L5FFF.

Berilog provides designers the ability to describe design functionality in

an algorithmic manner. 5n other "ords! the designer describes the behavior of the circuit.

hus! behavioral modeling represents the circuit at a very high level of abstraction. Design at

this level resembles C programming more than it resembles digital circuit design. $ehavioral

Berilog constructs are similar to C language constructs in many "ays. Berilog is rich in

behavioral constructs that provide the designer "ith a great amount of fle%ibility.

/.12.OPERATIONS AND ASSI7NMENTS:

he design description at the behavioral level is done through a seuence

of assignments. hese are called Rprocedural assignments? W in contrast to the continuous

assignments at the data flo" level. hough it appears similar to the assignments at the data

flo" level discussed in the last chapter! the t"o are different. he procedure assignment is

characteriKed by the follo"ing6

• he assignment is done through the T7U symbol (or the TQ7U symbol) as "as the case

"ith the continuous assignment earlier.• An operation is carried out and the result assigned through the T7U operator to an

operand specified on the left side of the T7U sign W for e%ample!• 0 7 0G

>ere the content of reg 0 is complemented and assigned to the reg 0 itself. he assignment

is essentially an updating activity.

• he operation on the right can involve operands and operators. he operands can be

of different types W logical variables! numbers W real or integer and so on.• All the operands are given in ables +.- to +.:. he format of using them and the

rules of precedence remain the same.


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• he operands on the right side can be of the net or variable type. hey can be scalars

or vectors.• 5t is necessary to maintain consistency of the operands in the operation e%pression W

e.g.!

• 0 7 m / lG

>ere m and l have to be same types of uantities W specifically a reg! integer! time! real!

realtime! or memory type of data W declared in advance.

• he operand to the left of the T7U operator has to be of the variable (e.g.! reg) type. 5t

has to be specifically declared accordingly. 5t can be a scalar! a vector! a part vector!

or a concatenated vector. Procedural assignments are very much lie seuential

statements in C. 0ormally they are carried out one at a time seuentially. As soon as aspecified operation on the right is carried out! the result is assigned to the uantity on

the left W for e%ample

0 7 m ; lG

0- 7 0 ` 0G

he above form a set of t"o procedures placed "ithin an al"ays bloc.

Jenerally they are carried out seuentially in the order specifiedG that is! first m and l areadded and the result assigned to 0. hen the suare of 0 is assigned to 0-. Subseuently the

follo"ing assignment! if any! is carried out. >o"ever! there can be e%ceptions to this "hich

"ill be discussed later. he seuential nature of the assignments reuires the operands on the

left of the assignment to be of reg (variable) type. he basic seuential nature of assignments

here is in direct contrast to the concurrent nature of assignments at the data flo" level.

S!ru,!ure Pr,eure:


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here are t"o structured procedure statements in Berilog6 al"ays and

initial .hese statements are the t"o most basic statements in behavioral modeling. All other

behavioral statements can appear only inside these structured procedure statements.

Berilog is a concurrent programming language unlie the C programming language! "hich is seuential in nature. Activity flo"s in Berilog run in parallel

rather than in seuence. Fach al"ays and initial statement represents a! separate activity flo"

in Berilog. Fach activity flo" starts at simulation time .he statements al"ays and initial

cannot be nested. he fundamental difference bet"een the t"o statements is e%plained in the

follo"ing sections.

A$@':

• he ey element of Berilog behavioral design is the '$@' bloc the al"ays bloc

contains one or more Tprocedural statementsU.• Another type of procedural statement is a Tbegin&endU bloc. $ut the A4#AS bloc

is used in all because of its simplicity! that is "hy "e call it an al"ays bloc.• Procedural statement in an al"ays bloc e%ecutes seuentially .he al"ays bloc

e%ecutes concurrently "ith other concurrent statement in the same module.

Synta%6

-).Al"ays _(signal&name NNNNsignal&name)

Procedural statement

). Al"ays procedural statements

• 5n the first form of al"ays bloc !the_ sign and parenthesiKed list of signal

names called Tsensitivity list T.• A verilog concurrent statement such as al"ays bloc is either e%ecuting or

suspend• A concurrent statement initially is in suspend stste !"hen any signal value

changes its value !it resumes e%ecution starting its first procedural statement

and continuing until the end.


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• A properly "ritten concurrent statement "ill suspend after one or more

e%ecutions. >o"ever it is possible to "rite a statement that never

suspends(e.g.6 assign @7@)! since @ changes for every pass !the statement

"ill e%ecute forever in Kero simulation time("hich is not useful).• As sho"n in the second part of synta%! the sensitivity list in al"ays bloc is

optional .an al"ays bloc "ithout a sensitivity list starts running at Kero

simulation time and eeps looping forever.• here are different types of procedural statement that can appear "ith in an

al"ays bloc. hey are blocing&assignment statement! non blocing&

assignment statement! begin&end blocs !if! case! "hile and repeat.

B$,(i)g A) N)&*$,(i)g Aig)#e)!:

All assignment "ithin an initial or an al"ays bloc considered so far are

done through an euality (T7U) operator. hese are e%ecuted seuentially W that is! one

statement is e%ecuted! and only then the follo"ing one is e%ecuted. Such assignments bloc

the e%ecution of the follo"ing lot of assignments at any time step. >ence they are called

Tblocing assignmentsU.

*urther! "hen such a blocing assignment has time delays associated

"ith it! the delay is applicable to the follo"ing assignment or activity also. Differente%amples of groups of blocing assignments have been considered in the preceding sections.


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$locing assignment statements are e%ecuted in the order they are specified in a

seuential bloc. A blocing assignment "ill not bloc e%ecution of statements that follo" in

a parallel bloc

S)!':

Bariable&name7e%pressionG//blocing statements.

Bariable&nameQ7e%pressionG//0on&blocing statements.

A blocing assignment loos lie an assignment statements! in any other

procedural language (such as c).0on blocing assignment loos and acts a little different! it

evaluates its right hand side !but it doesn?t assign the resulting value to the left hand side

until an infinitesimal delay after the entire al"ays bloc has been e%ecuted.

/.13.BE7IN& END BLOC>:

$egin&end bloc statements are used to group several statements for use "here one

statement is syntactically allo"ed. Such places include functions! al"ays and initial blocs!

if! case and for statements. $locs can optional.

. S)!':

begin begin 6 blocOname

procedural statements reg Lmsb6lsb regOvariableOlistG

: : integer Lmsb6lsb integerOlistG

: : parameter Lmsb6lsb

parameterOlistG

procedural statements ... statements ...

end end

• the synta% of a begin&end bloc !simply a list of one or more procedural statements

enclosed by the ey"ord begin&end.


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• As sho"n in the second part of the synta% !the begin&end bloc can have its o"n local

parameters or variable declaration.• 5n the second synta% !the bloc must be named !so that these terms can be traced

during simulation and synthesis.

• 0ote that the procedural statements "ithin a begin&end bloc e%ecutes seuentially!not concurrently lie the instance !continuous Wassignment and other Tal"ays U

statements in the module.

/.1-.IF AND IF&ELSE BLOC>:

he if construct checs a specific condition and decides e%ecution based on the

result. *igure sho"s the structure of a segment of a module "ith an if statement.

After e%ecution of assignment-! the condition specified is checed. 5f it is satisfied!assignment is e%ecutedG if not! it is sipped. 5n either case the e%ecution continues

through assignment=! assignment,! etc. F%ecution of assignment alone is dependent

on the condition. he rest of the seuence remains. he flo"chart euivalent of the

e%ecution is sho"n in *igure.

synta%6

5f (condition)

. . .

assignment-G

if (condition) assignmentG

assignment=G

assignment,G

. . .


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5f the number of assignments associated "ith the if condition is more

than -! the "hole set of them can be grouped "ithin a begin&end bloc. *igure .=

sho"s a segment of a design using the if construct. 5t is a ring counter! "hich shifts

one bit right at every cloc pulse. he shift operation shifts the a byte right by one bit

and fills the vacated bit W aLY W "ith a Kero. 5t is set to - if the bit shifted out last W

aL W "as a -. he same is carried out through the if statement. he ifelse constructis more common and turns out to be more useful than the if construct taen alone.

*igure sho"s the use in a typical design description. *igure sho"s the same in

flo"chart form. he design description has t"o branchesG the alternative taen is

decided by the condition6

. . .


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Fig ./.1.*lo" chart of e%ecution of the i 9e$e loop

• After the e%ecution of assignment-! if the condition is satisfied! alternative- is

follo"ed and assignment and assignment= are e%ecuted. Assignment, and

assignment 1 are sipped and e%ecution proceeds "ith assignment+.• 5f the condition is not satisfied! assignment and assignment= are sipped and

assignment, and assignment1 are e%ecuted. hen e%ecution continues "ith

assignment+.

r L%

Similar to for loops in C/C;;! they are used to repeatedly e%ecute a statement or

bloc of statements. 5f the loop contains only one statement! the begin ... end statements may

be omitted.

S)!':

for (count 7 value-G

count Q/Q7/]/]7 valueG


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count 7 count ;/& step)

begin

... statements ...

Fnd

E'#%$e

for (I 7 G I Q7 YG I 7 I ; -)

begin

cLI 7 aLI bLIG

dLI 7 aLI bLIG

end

Fig ./.2.*lo" chart of e%ecution of the r loop

@"i$e L%:

he "hile loop repeatedly e%ecutes a statement or bloc of statements until the

e%pression in the "hile statement evaluates to false. o avoid combinational feedbac during

synthesis! a "hile loop must be broen "ith an _(posedge/negedge cloc) statement . *or

simulation a delay inside the loop "ill suffice. 5f the loop contains only one statement! the

begin ... end statements may be omitted.


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S)!':

"hile (e%pression)

begin

... statements ...

Fnd

Fig ./.3.*lo" chart of e%ecution of the @"i$e loop

E'#%$e

"hile (overflo") begin

_(posedge cl)Ga 7 a ; -G

end

#henever the "hile construct is used! event or time&based activity flo" "ithin the bloc has

to be ensured.

• #ith the "hile construct the e%pression associated "ith the ey"ord "hile must

become false through the e%ecution of assignments inside the bloc.


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CASE:

he case statement allo"s a multipath branch based on comparing the e%pression

"ith a list of case choices. Statements in the default bloc e%ecutes "hen none of the case

choice comparisons are true. #ith no default! if no comparisons are true! synthesiKers "ill

generate un"anted latches. Jood practice says to mae a habit of puting in a default "hether

you need it or not.

5f the defaults are dont cares! define them as R%? and the logic minimiKer "ill treat

them as don?t cares and dsave area. Case choices may be a simple constant! e%pression! or a

comma&separated list of same.

S)!'

case (e%pression)

caseOchoice-6 begin

... statements ...

end

caseOchoice6

begin

... statements ...

end

... more case choices blocs ...

default6

begin

... statements ...

end

endcase

,'e:

5n case%(a) the case choices constant TaU may contain K! % or "hich are used as

don?t cares for comparison. #ith case the corresponding simulation variable "ould have to

match a tri&state! unno"n! or either signal. 5n short! case uses % to compare "ith an

unno"n signal. Case% uses % as a don?t care "hich can be used to minimiKe logic.


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C'e:

CaseK is the same as case% e%cept only and K (not %) are used in the case choice

constants as don?t cares. CaseK is favored over case% since in simulation! an inadvertent %

signal! "ill not be matched by a or - in the case choice

/.1/.FOREVER LOOPS:

he forever statement e%ecutes an infinite loop of a statement or bloc of statements.

o avoid combinational feedbac during synthesis! a forever loop must be broen "ith

an_(posedge/negedge cloc) statement. *or simulation a delay inside the loop "ill suffice. 5f

the loop contains only one statement! the begin ... end statements may be omitted. 5t is

S)!'

forever

begin

... statements ...

Fnd

F%ample

forever begin

_(posedge cl)G // or use a7 : a;-G

a 7 a ; -Gend

REPEAT :

he repeat statement e%ecutes a statement or bloc of statements a fi%ed number of

times. repeat C


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S)!':

repeat (numberOofOtimes)

begin

... statements ...

Fnd


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CHAPTER

.SOFT+ARE USED


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.0.i$i):

@ilin% soft"are is used by the B>D4/BFE54D4 code into gate level net list. 5t is an integral part of current design

flo"s.

A$gri!"#

S!'r! !"e ISE S!@'re * ,$i,(i)g !"e ILIN ISE i,).

Create a 0e" ProIect and find the follo"ing properties displayed.

Create a B>D4 Source formatting all inputs! outputs and buffers if reuired. "hich provides

a "indo" to "rite the B>D4 code! to be synthesiKed.


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Chec Synta% after finally editing the B>D4 source for any errors.

After that perform the E4 and FC>0


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CHAPTER J


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J.APPLICATION

-. Digital Signal Processing (DSP)applications.

a. Signal filtering. b. Convolution.

c. Decreasing number of inner products.

.


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CHAPTER K


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K.CONCLUSION

5n this paper implementation +, bit MAC is done using the ne" architecture of MAC

unit and different parameters lie delay! no. of 4's! memory usage is found out. Since!multipliers are used in most of the applications "e can select the best multiplier "ith the

above parameters and get better results.

>ence! using this ne" architecture of MAC unit "ith the suitable multiplier in most

of the DSP applications leads to better results and performance. he Performance analysis!

result and comparison are reported above.


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CHAPTER


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.REFERANCE

L-P.Iagadeesh Design ofHigh Performance 64 bit MAC Unit U -= 5nternational Conference

on Circuits! Po"er and Computing echnologies L5CCPC&-=.

L #.\. o"nsend! F.F. S"artKlander \r.! and \.A. Abraham! T A Comparison of Dadda and

Wallace Multiplier Delays! UProc. SP5F! Advanced Signal Processing

Algorithms! Architectures! and 5mplementations @555! pp. 11&1+! =.

L= M.>. Eais! M.>. Al MiIalli! T Brauns multipliers! "partan#$A% based design and

implementationU! \. Comput. Sci.! vo. Y! no. (--)! pp.-+:&-+=! --.

L, 4. Dadda! T"ome "chemes for Parallel Multipliers!U Alta *reuenKa!vol. =,! pp. =,:&=1+!

-:+1.

L1 C.S. #allace! T A "uggestion for a &ast Multiplier !U 5FFF rans.Flectronic Computers!

vol. -=! no. -! pp. -,&-Y! *eb. -:+,.

L+ Eon S. #aters and Farl F. S"artKlander! \r.! Z A 'educed Comple(ity Wallace Multiplier

'eduction! Z 5FFF ransactions .! :a. &P)A design and implementation of fi(ed *idth standard and

truncated 6+6#bitmultipliers! A comparati,e study. Proceedings of the ,th 5FFF 5nternational

Design and est#orshop! 0ov. -1&-Y! 5FFF @plore Press!Eiyadh! Saudi Arabia! pp6 -&

,.D.! -a. Hard*are implementation of truncated multipliers using "partan

$A%- .irte(#4and .irte(#/ de,ices. Am. \. Fng. Applied Sci.! =6-&+. D

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