612507 Electrical Characteristics

7/30/2019 612507 Electrical Characteristics

1/18

Dr.Ashraf Armoush

2010 Dr.Ashraf Armoush

Outline

TTLversions

ElectricalCharacteristics

Averagemaximumpowerdissipation

SwitchingCharacteristics

DCNoiseImmunity(NoiseMargin)

DCandACFanout

pee ower

CMOSVersions

LogicGateBuffers

2 2010 Dr.AshrafArmoush,AnNajahNationalUniversity


2/18

TTL

TTL :TransistorTransistorLogic

Twotransistorsareuse to riveeac outputo eac c ip

Basedonbipolarnpn orpnp transistors

TTLcompatible:meansthattheinputsandoutputsofthe

equipmentfollowthecommonrulesthatapplytotheinputs

andoutputsofallTTLgates

TTLFamily:

74XX: commercialversion [0 70C]

54XX: militaryversion [55 125C]

3 2010 Dr.Ashraf Armoush ,AnNajahNationalUniversity

TTLVersions (subfamilies)

1. StandardTTL (74xx)[obsolete] Theoldeststandardversion(late1960s)

PropagationDelay=10ns

2. LowPowerTTL(74Lxx) Lowpower(comparedtotheoriginalTTLlogicfamily),

Veryslow (PropagationDelay=33ns)

3. SchottkyTTL (74Sxx)[obsolete] Introducedintheearly1970s.

Highspeedapplications(PropagationDelay=3ns) Switchingspeedimprovement300%overstandardTTL

UseSchottky diod betweenthebaseandcollectorofeach

transistor(preventthetransistorfromgoingintodeepsaturation)

. Lowpower(1/5supplycurrent).

SwitchingspeediscomparabletothestandardTTL(PropagationDela =10ns



3/18

TTLVersions (subfamilies)

5. AdvancedSchotky (74ASxx)

Introducedinthemid1980s.

Smallertransistorswithlessinternalcapacitance.

PropagationDelay 1.7

ns Powerconsumption


4/18

ElectricalCharacteristic

Highlevel output voltage (VOH): the minimum voltage on the outputpin when the input condition establish logic HIGH at the output.

LOW eve output vo tage VOL : the maximum voltage on theoutput pin when the input condition establish logic LOW at the output.

Lowlevel input voltage (VIL): the maximum voltage applied at theinput that is recognized as a legal LOW level.

HIGHlevel input voltage (VIH): the minimum voltage that needs to.

Out ut short circuit current IOS : It is a troubleshootin techni ueto short a high level output to ground temporarily to verify that a circuit is

working correctly


ElectricalCharacteristic



5/18


Averagemaximumpowerdissipation

Supply Current HIGH and LOW (ICCH ICCL): The supply current when the

output is HIIGH and LOW respectively.

Ex:

2

I (avg)CCCCHCCL=

4.4= mAICCL

3mA

4.46.1

I

6.1

(avg)CC=

+

=

= mAICCH

Average maximum power dissipation = ICC(avg) * VCC(max)

mWVmAVI CCavCC 75.1525.5*3* max ==

gatesmW /94.3gates4

mW15.75gateoneBy ==



6/18


tr (waveform rise time): time for a waveform to increase from 10% to 90%of its maximum voltage level.

tf waveform fail time : time for a waveform to decrease from 90% to 10%of its maximum voltage level.



tpHL (propagation delay high to low): time delay between a specified level onthe input waveform and a specified level on the output waveform going low.

tpLH (propagation delay low to low): time delay between a specified level onthe input waveform and a specified level on the output waveform going high.

Propagationtimedelay(tD ortPD) tt +

2Dt =



7/18

DCNoiseImmunity(NoiseMargin)

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL ILOL

IHOH

VV

===


voltVVV OLILNL

IHOHNH

3.05.08.0

..

===

DCFanout

DCfanout=

= OLOHI

I

I

I,minn



8/18

Ex:

8

.

==

=

mAI

m

OL

OH

20

.

= AIIH

IL

801.0

8=== gates

mA

mA

I

In

IL

OL

2020

4.0=== gates

A

mA

I

In

IH

OH


gates20min{20,80}out-FanDC ==

ACFanout

Each gate adds 1.5 pF of capacitance per gate input + 5 pF straycapacitance

propagation delay

Each 10pfadd 1ns to the tPD

(#ofgates ) (loadcapacitance ) (medelay )

Ex: findthetimepropagationdelayfor20gatesfanout?

Given(tPD=9nsandCL =15pf)Eachgateadds6.5pF20gates*(6.5pF/gate)=130pF

Additionalload=130 15=115pF

Additionaltimedelay=115pF/(10pF/ns)=11.5ns

tPD(total) =9+11.5=20.ns



9/18

Speed PowerPRODUCT

It is a method to rate the performance of a logic gate.

The two most important factors are speed and power.

The speedpower product is found by multiplying the gate

propagation delay by the gate power dissipation.S eedPower roduct= tPD Power Dissi ation.

Thelowerthisvalue betterperformance

Ex: 74ALS00(tPD =5nsandPowerconsumption=1.25mW )

S P=1.25mW 4ns =5pJ

Ex: 7400(tPD =9nsandPowerconsumption=10mW )

S P=10mW 9ns =90 J


Open(floating)Pins

If you leave a pin (floating), the gate will respond as if that pin were

connected to a logic 1.

ro em: w ac e a ra o an enna. any rece ve no se can

easily cause plussensitive circuits (such as flipflops) to operate

incorrectly.

Solutions:

1. Connect two pins together.

Increases the load current which will decrease the fanout.

Doubles the capacitive

.

3. Connect them to Vcc through a pullup resistor

4. Connect the unused input to an inverter output biased high.



10/18

Open(floating)Pins


ICC

SwitchingNoise:

AsmallbypasscapacitorisusedneartheVcc pinfortwo

reasons:

1. Anyhighfrequencyinthepowersupply(Vcc)willberemoved

1=CX

circuit)shorta(like0:frequencyhighAt CX

.

Thereisaninductanceinthewire:

dio agesp e

dt=

.



11/18

ComplementaryMetalOxideSemiconductor(CMOS)

LogicCircuits CMOS gates uses voltagecontrolled complementary n and pchannel MOS

transistor.

TheimportantcharacteristicsofCMOSdevicesare: hi h noiseimmunit

NMOS PMOS CMOSInverter

lowstatic powerconsumption.

SlowerthanTTLbutwithsmallerarea(highdensity)

thevastmajorityofmodernintegratedcircuitmanufacturingisonCMOSprocesses.

CMOS Families: MetalgateCMOS (CD40XX)hasaratedworkingvoltageof3 15

SilicongateCMOS (74CXX)logichasaworkingvoltagerangeof2 6V


CMOSVersions (subfamilies)

1. CD4000Series TheoldestCMOSversion(1968)

OperateoverawiderangeofVCC [315V]

Thepoorest performance

2. CMOS(74Cxx)[obsolete] ThefirstofCMOStobepincompatiblewithTTL(inthemid1970s),

Twiceas astasCD4000series

3. HighSpeedCMOS(74HC/HCTxx/)

Introducedinthe

early

1980s. anou or

74HCThaselectricalcharacteristiccompatibletoTTL(74LS)

74HCxxis5timesfasterthana74Cxx(tPD = 9ns) tPD for74LSxx

. Designedtobecompetitivewith74ASand74ALS(late1980s)

DevicesinthisseriesarenotpincompatiblewiththeirTTLcounterparts.

=

74ACTxxisdesignedtohaveTTLcompatibleVIH andVIL



12/18

RecommendedOperatingConditions

CMOScanoperateoverawiderangeofVCC [2to6V]

ManyofthedatasheettestsarespecifiedatthreevaluesofVCC [2,

. an

Ex: ForV =4.7V(standard)

74HC00has:

VIH =3.15V (problemwithTTLinterface)

IL .

74HCT00has:

VIH =2.1V TTL compati e

VIL =0.9V


NoiseImmunity

74HCwithVCC =4.7V

VOH =4.1V

VOL =0.1V

VIH =3.15V

IL .

V =V V =4.4 3.15=1.75V VNL =VIL VOL =0.9 0.1=0.8V

BothVNH andVNL aregreter thanthoseofitsTTLcounterpart.



13/18

PowerConsumption

ICC provided in the datasheet represents the static power supply

current which can be used to compute the static power

.

There are 3 sources of power consumption in a CMOS gate:

1. Transient current required to charge to load capacitance.

2. Transient current required to charge internal capacitance.

3. Current spikes that occur when both n and pchannel transistor conduct

momentarily as the gate switches states.

These 3 quantities depend on the operating frequency ( )

VIVCCP ++= 2

CPD

: the equivalent internal capacitance

C : the load ca acitance


Ex:

Calculate the static power consumed by one 74HC00 at room temperature.

Compare it to the power consumed when the gate output is switching at

1MHz and driving 10 additional 74HC00 loads.

Solution: From the data sheet:

VCC = 5 V, ICC = 2A, CPD = 20 pFand Ci = 10 pF

Each input adds 10pF (the input capacitance from the data sheet) + 5pF

gateWgatesn

P CCCCstaticD /5.24

)( ===

Stray capacitance.

With 10 loads CL = 10 X (10+5) = 150 pF

WMHzvpFpFP

VIfVCCP

MHzD

CCCCCCLPDMHzD

5.21)5()15020(

)(

2

)1(

)1(

++=

++=


mWWP MHzD 25.45.4252)1( ==


14/18

InterfacingTTLandCMOS

Conditionsforinterfacing:

VOH VIH

VOL VIL

|IOH|>|IIH|

|IOL|>|IIL|


CMOSdrivingTTL

Ex:

a cu a e emax mum num ero npu s a a

candrive.

74ALS00: 0.1mAI,A20I ILIH

==

==

II

, OLOH


gates40200,40minI

,I

minnILIH

==

=


15/18

TTLdrivingCMOS

Satisfied)(VV:conditionFirst ILOL

Therearetwomethodstosolvethisproblem:


TTLdrivingCMOS(cont.)

1. Pullupresistor

2. The74HC00isreplacedbytheequivalentTTLcompatible

74HCT00



16/18

LogicGateBuffers

Thesegateshavespecialoutputcapabilities.Theytypicallyhavelarge

outputtransistorsthatallowthemtosupplyhighcurrent.

Someversionshaveopencollectorthatcanswitchvoltageashighas50V.

Otherversionshavetristateoutput.


ModelofConventionalBuffers



17/18

OpenCollectorBuffer

Advantage:allowsthelogicgatetocontrolhighvoltagedevices

suchasrelaycoils,lamps,dcmotors,etc..

33 2010 Dr.Ashraf Armoush ,AnNajahNationalUniversity

OpenCollectorBuffer(cont.)

Conventional logic gates cannot be wired with their outputs shorted. (oneoutput in the low state would act as a short circuit to ground to another output in the

high state Both gates could possibly be damaged) This thing can be done with open collector buffers. (This is because an open

collector gate does not have an activehigh transistor and thus cannot be damaged).


CBAC.B.AOUT ++==


18/18

OpenCollectorBuffer(cont.)


CalculatingtheValueofthePullupResistor

g a e:

ThevoltagedropinRmustbelessthan(VCC VOH)

=

2.7V5VVV

)V(VIR OHCCR

IHOHR

LowState:

.0.02mA0.3mAII3 IHOH

=+

=+

VVIR

III ILOLR

=

9250.04mAmA8

0.5V5V

II

VVR

ILOL

OHCC =

=

Asmall valueismorepreferabletohaveashorttimeconstant(RC)forcharginganddischargingtheinputandoutputcapacitances. (R=620)

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612507 Electrical Characteristics