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Writing Testbenches:

Functiona l Verification of HDL Models

Second Edition

Janick Bergeron

Synopsys, Inc.

Kluwer Academic Publishers

Boston/DordrechtA.ondon

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T A B L E OF CONTENTS

About the Cover

XV

Foreword

xvii

C HA P T E R 1

Preface ^^

Why This Book Is Important

^ix

What This Book Is About ' ^x

W hat Prior Know ledge You Should Have xxi

Reading Paths ,̂ 1̂1

Choosing a Language xxiii

VHDL

vs. Verilog _ ^

j

Hardwa re Verification Languages xxiv

And the Winner Is

xxv

For M ore Information xxvi

Acknowledgements

xxvi

What is Verification? 1

What is a Testbench? 1

The Importance of Verification 2

Reconvergence Model 5

Writing Testbenches: Functional Verification of HDL Models

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Table of Contents

The Human Factor 6

Automation

7

Poka-Yoke 7

Redundancy

7

What Is Being Verified? 8

Form al Verification 8

Equivalence Checking 9

Model Checking 10

Functional Verification II

Functional Verification A pp roa che s 12

Black-Box Verification 12

White-Box Verification 13

Grey-B ox Verification 15

Testing Versus Verification 16

Scan-Ba sed Testing 17

Design for Verification 18

Design and Verification Reuse 19

Reuse Is About Trust 19

Verification fi}r Reuse 20

Verification Reuse 20

The Cost of Verification 21

Summary 23

CHAPTER 2

Verification Tools 25

Linting Tools 26

The Limitations of Linting Tools 27

Linting Verilog Source Code 29

Linting VHD L Source Code 30

Linting O penVera and e Source Code 32

Code Reviews 32

Simulators 33

Stimulus and Response 34

Event-Driven Simulation 34

Cycle-Based Simulation 37

Co-Simulators 39

Verification Intellectual Property 42

Hardware Modelers 43

Waveform Viewers . 44

Writing Testbenches: Functional Verification of

HDL

Models

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Cod e Coverage

Statement Coverage

Path Coverage ^^

Expression Coverage

FSM Coverage

What Does 100 Code Coverage Mean? .[,, '.'''. 53

Funct ional Coverage

Item Coverage

Cross Coverage ^Q

Transition Coverage ^«

Wha t Does 100 Functional Coverage Mean? 61

Verification Languages ^2

Asser t ions ^

Simulation Assertions ^5

Formal Assertion Proving

57

Revis ion Control 68

The Software E ngineering Experience 69

Configuration Mana gement 71

Working with Releases 72

Issu e Track ing 74

Wha t Is an Issue? 74

The Grapevine System 75

The Post-It System 76

The Procedural System 76

Computerized System 77

Metr ics

'^

Code-Related Metrics 79

Quality-Related Metrics

*^

Interpreting Metrics ^^

83

Sununary

CHAPTER 3 The Verification Plan ^^

The Role of the Verification Plan ^

Specifying the Verification

Defining First-Time Success

Levels of Verification ^^

Unit-Level Verification ^^

Reusable Components Verification

^^

ASIC and FPGA Verification

Writing

vii

Testbenches: Functional Verification of HDL Models

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Table of Contents

CHAPTER 4

System-L evel Verification 92

Board -Level Verification 93

Verification Strate gies 94

Verifying the Response 95

From Specification to Features 96

Com ponent-Level Features 99

System-Level Features 99

Error Types to Look For

100

Prioritize

101

Design for Verification

702

Directed Testbenches Approach 104

Group into Testcases

105

From Testcases to Testbenches 106

Verifying Testbenches

107

Measuring Progress

108

Coverage-Driven Random -Based Approach 109

Measuring Progress

109

From Features to Functional Coverage 7//

From F eatures to Testbench 775

From F eatures to Generators 775

Directed Testcases

778

Sununary 120

High-Level M odeling 121

Behavioral versus RTL Th inking 121

Contrasting the Approaches i^3

You Gotta Hav e Sty le 125

A Q uestion of Discipline 125

Optimize the Right Thing 126

Good C omm ents Improve Maintainability 129

Structure of Behavioral Code

l- O

Encapsulation H ides Implementation Details 131

Encapsulating Useful Subprograms

1^^

Encapsulating Bus-Functional Models 1^^

Data Abstraction 145

Records

^ < J

Variant Records 1^1

Arrays

755

Usts . . . .

757

vin


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Files

163

Mapping High-Level Data

Types

to Physical

Interfaces

165

Objec t -Or i en t ed

Programm ing 166

Classes

766

Inheritance

773

Polymorphism

777

Limitations of OpenVera

andes

OOP

Implementation . 780

Aspect-Oriented Programming 181

The Problem w ith O bject-Oriented P rogramming

.,,181

Variant Data with V ariant Code

783

Limitations

ofe's

AOP Implementation 786

The Parallel Simulation Engine 189

Connectivity.

Time

and Concurrency

1S9

Connectivity,

Time

and C oncurrency in HD Ls and

HVLs

^ ^

The Problems with Concurrency

1^1

Emulating Parallelism on a Sequential Processor

,.,192

The

Simulation C\cle

196

The Co-Simulation

Cxcle

797

Parallel vs. Sequeniial

Fork/Join Statement

The Difference

Between Driving

an d Assigning

-C^

208

Race Condit ions ^ ^

Read/Write Race Conditions

^^^

Write/\^rite

Race Conditions

'^^

Initialization Races ^

Guidelines

for Avoiding R ace Co nditions

• - - • ^^^

Seme^^res

^jg

Ver i los Portabilitv Issues •

Events

from

0^er.ri„en

Scheduled

Values • -^^

Disabled Scheduled Values „ ^

Output Arguments

on D isabled

Tasks • — -••-•• .^l

Non Re Entrant Tasks ^

Summary

229

CHAPTER

S

Stimulus

a ui

Response

^

Reference Signals

231

TmeftesoUaion

Issues

...233

.Migning S ignals in Delta T one

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Table of Contents

Clock Multipliers 235

Asynchronous Reference Signals 23A

Random Generation of Reference Signal Parameters 239

Applying Reset 24/

Simple Stimulus

246

Applying Synchronous Data Values 246

Encapsulating Waveform Generation 247

Abstracting Waveform Generation 248

Simple Output

252

Visual Inspection of Response 252

Producing Simulation Results 252

Minimizing Sampling

254

X^sual Inspection of Waveforms 255

Self-Checking Testbenches 256

Input and Output Vectors 257

Golden Vectors

258

Self-Checking Operations 260

Complex Stimulus 262

Feedback Between Stimulus and Design 263

Recovering from Deadlocks 264

Asynchronous Interfaces 267

Bus-Functional Models 269

CPU Transactions

269

From Bus-Functional Procedures to Bus-Functional

Model

272

OpenVera's Interface Model 274

Bus-Functional Models in OpenVera 276

Asynchronous Signals in OpenVera 287

Synchronous Bus-Functional Models ine 282

Asynchronous Bus-Functional Models ine 287

Configurable Bus-Functional Models 289

Response Monitors 290

Autonomous Monitors

295

Slave Generators

299

Multiple Possible Transactions

^^

Transaction-Level Interface

^^

Variable-Length Transactions ^^

Split Transactions ^^^

Retries and C ompletion Status ^^^

Symbol-Level

Control

^^^

Summary 317


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CHAPTER 6 Architecting Testbenches

sjg

Test Harness

^2^

V H D L

Test Harness

325

Bus-Functional Entity ^27

Abstracting the Client/Server Protocol J29

Test Harness jj2

Multiple Server instances 334

Design Configuration

335

Abstracting Design Configuration 336

Configuring the Design 338

Random Design Configuration 340

Self-Checking Testbenches 341

Hard Coded Response 342

Data Tagging 343

Reference Models 345

Transfer Function 347

Scoreboarding

348

Integration with the Transaction Layer 350

Directed Stimulus 352

Random Stimulus

354

Atomic Generation '^

Adding Constramts me • -'̂ ^

Adding Constraints in OpenVera ^^^

364

Constraining Sequences

Defining' Scenarios in OpenVera

^ 377

Defining Scenarios me

374

Summary

375

CHAPTER 7 Simulation Management

• • • • • • ^

Behavioral Models

•••• ^7^

Behavioral versus Synthesizable Models ^^^

Example of Behavioral Mod eling ^^^

Characteristics of a Beha vioral Mod el • •• •• •• ; ^ ^^^

Modeling Reset •

...390

Writing Good Behavioral Models ^^^

Behavioral Models Are Faster 395

The C ost of Behavioral Models

. . . .

595

The Benefits of B ehavioral Models

^^;;;r:^^^::^::: ̂^^^

x

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Table of Contents

Demonstrating Equivalence

Pass or Fail?

Managing Simulations

Configuration Management

Verilog Configuration Mana gement

VHD L Configuration Manag ement

OpenV era Configuration Mana gement

e Configuration Management

SDF Sack-Annotation

Output File Management

Seed M anagement

R e g re s s io n

Running Regressions

Regression Management

S u m m a r y

APPENDIX A Coding Guidelines ^^9

Directory Structure

VHDL Specific ....[[ [

.'.*.'.

^^

Verilof-

Spec,fie

^^^

' ^^2

General

CVxJmg

Guidelines

. ^

Comments

iMyout

Syntax . . . . . . . . . . \ . \ ' ' ^^^

Debugging ^^^

Naming

Guidelines

.....^ ̂ ^ ^

Capitali7xition

Identifiers ^^

^

AAA

Constants , , .

l''<^HVLSperifir \\

^

f'tlenamex

' ^'^

Coding Guidelines

Z

Structure ^^^

tjiytiut , ^^^

^m^LSperifir ^

^^'-'log Specific . '^^

455

xij

Writing Tcufbcnchc*: F

unctional Vcrifitation of HDl. Modcli

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APPENDIX

B

Glossary 461

Afterwords 465

Index 467

^ ^ — ^ r ; ; ; ; ; ^ ^ verification of

HDU ModCs

xiu

Documents

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