LAB 7 REPORT (FINAL PROJECT)

CS152, FALL 1999

Section 102T.A. Kelvin Lwin

Group BACH

BRIAN OH cs152obrian 12937577ALAN CHOU cs152alchou 13226233CHRIS SPITZER cs152spitzer 13127587HENRY KANG cs152hkang 13292885

Online Submission: Thursday, December 9, 1999

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Table of Contents1. Introduction

a) Datapath Architectureb) Performance Comparisons

2. Featuresa) Two-Way Super-Scalarb) Victim Cachec) Stream Buffer [Note: Not integrated into datapath]d) CAM-Based Cachee) Optimized Memory Controller

3. Performance Summarya) Critical Pathb) Overall

4. Testing Philosophya) Component-Level Design & Testingb) Incremental Design & Testingc) Regression Testing

5. Conclusion

Appendix

SchematicsTest programs [Please see supplementary submission]VHDL [Please see supplementary submission]Online Logs [Please see supplementary submission]

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1. IntroductionAn overture to our beloved Suzy Q, the BACH team composes a delightful new 2-way super-scalar 5-stage processor, with a nifty victim cache and an instruction stream buffer. We only hope that our design will faithfully reproduce the enthusiasm and dedication we have for our angelic Suzy Q.

folle et sage Blurb from the website

For this project, we enhanced the standard five-stage pipeline of lab 6 for potentially improved performance. The most radical of these was the conversion of the datapath to a two-way super-scalar pipeline, which allows up to a pair instructions to be executed simultaneously. This entailed several subprojects, including an instruction decider to determine whether two instructions could run together, an instruction router to place instructions in the correct pipeline (one must ensure that memory instructions only run through the pipeline with a memory stage), a new instruction cache to fetch two words per instruction fetch, new forwarding paths, and updated hazard stall logic.

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Second, we enhanced the cache systems. Namely, we include a stream buffer for instructions and a victim cache for data. Furthermore, the memory controller was optimized to allow a burst mode retrieval of blocks for the stream buffer. Finally, to improve cache access time, we modified the caches to a CAM-based implementation of a fully associative array.

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b) Datapath Architecture:A two-way super-scalar, pipelined MIPS processor.

c) Performance Comparisons

Lab 5 mystery program observations:Clock period < 44ns (stepsize 22ns)Fails on clock cycle time of 40ns (stepsize 20ns)

_____Lab 6 mystery program--Performance by architecture/features-OLD Lab 6 datapath:

47.5ns clock period (stepsize 23.75ns), to nearest 0.1ns6075 cycles288,562.5ns

-w/new memory controller:29.0ns clock period (stepsize 14.50ns), to nearest 0.1ns6275 cycles181,975ns

-NEW Lab 7 super-scalar:910,000ns = 200ns clock period (stepsize 100ns), 4550 cycles268,650ns = 54.0ns clock period (stepsize 27.0ns), 4975 cycles237,600ns = 44.0ns clock period (stepsize 22.0ns), 5400 cycles196,200ns = 36.0ns clock period (stepsize 18.0ns), 5450 cycles

* 189,000ns = 35.0ns clock period (stepsize 17.5ns), 5400 cycles210,540ns = 34.8ns clock period (stepszize17.4ns), 6050 cycles

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209,330ns = 34.6ns clock period (stepsize 17.3ns), 6050 cycles205,700ns = 34.0ns clock period (stepsize 17.0ns), 6050 cycles

*** 181,500ns = 30.0ns clock period (stepsize 15.0ns), 6050 cyclesfail: >298,000ns = 29.8ns (14.90ns), >10,000 cycles [virtual inf loop]_____Final Lab 7 sample program "final_1.s"

2,970,000ns = 200ns period (step 100ns); 14,850 cycles842,400ns = 48.0ns period (step 24.0ns); 17,550 cycles807,300ns = 46.0ns period (step 23.0ns); 17,550 cycles

>>> 789,750ns = 45.0ns period (step 22.5ns); 17,550 cyclesfail: >1,120,000ns = 44.8ns period (step 22.4ns); >25,000 cycles

2. FeaturesSeveral new features were added to enhance performance.

a) Two-Way Super-Scalar

Single fetch stage, two decode, execute and memory stages. Allows increased instruction throughput with minimal increase in cycle time. Required the following subprojects:

Instruction Decider: Combination logic in stage 1, examines the two fetched instruction and decides if they can be run simultaneously, and if they need to be swapped (to ensure that memory operations always run in the first pipeline, even if run simultaneously with another instruction). The instruction decider follows this basic rule set:

Allow two instruction to run simultaneously unless:1) They are both memory operations.2) They write to the same destination (greatly simplifies the forwarding).3) The destination from the first is a source for the second (would need to

forward from stage 3 of one pipeline to stage 3 of second pipeline – a big increase in cycle time).

4) The first instruction is a branch.5) The instruction issued on the previous cycle was a branch (needed to keep a

single delay slot).

Two-word Instruction Cache: Modified standard cache to fetch two words at a time. Implemented this by splitting the instruction cache into two smaller 8-word caches, then adding the arbitration logic necessary to handle requests to memory and cache-line integration (to form a single cache line from the two cache lines of the sub-caches). End result is a cache that can fetch two words across any word boundary and integrates seamlessly into the old instruction fetch stage. The offset the penalty of calculating the current PC + 4, this arithmetic is done in parallel with the other PC determinations in stage 2.

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Updated forwarding and hazard logic: The number of possible forwarding paths increases by four for each ID stage in a 2-way super-scalar pipeline:

1) Pipeline 1 Stg 3, Pipeline 1 Stg 42) Pipeline 1 Stg 3, Pipeline 2 Stg 43) Pipeline 2 Stg 3, Pipeline 1 Stg 44) Pipeline 2 Stg 3, Pipeline 2 Stg 4

Each of these paths needs to be checked when fetching operands. We implemented by using the same hazard detection as in lab 5, but having four units in each ID stage, each checking one of the above paths. With this information, it is simply a matter of determining which of the resulting forward values is the correct one. Because of the restrictions implemented in the instruction decider, if any forwarding is to be done, precisely two of the four forwarding detectors agree on where to forward from. Determining agreement is an AND operation, and determines where to forward from.

The updated hazard logic follows a similar implementation, checking for possible hazard on the two possible hazard paths leading to this ID stage. We made the design decision to stall both pipelines on a hazard stall. This is reasonable because if we allowed one of the pipelines to keep running, we would might have out-of-order commit on instructions, which would not be a good thing.

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b) Victim CacheA four-word cache that sits underneath the data cache and serves as “scratch

space”. To make the block as efficient as possible, hits in the victim cache are checked in parallel with hits in the regular cache. If a hit is found in the victim cache but not in the data cache, the two lines are swapped by simultaneously performing write operations on the memory elements. We stall the pipeline by a single cycle, with saves us 2-3 cycles over going out to memory for a given cache line.

The victim cache is essentially a dumb piece, with no little internal control (there is a pointer to the next line to fill, but that’s it). All control of the victim cache is done with some minimal pieces of logic in the data cache that indicate with that cache is kicking out a line.

c) Stream BufferThe intent of the stream buffer is to minimize the amount of time spent waiting to fetch instructions from the memory. In lab 6, we saw big delays resulting from a memory access on every other instruction. The stream buffer, by fetching multiple instructions in burst mode, decreases the overall instruction fetch latency decay. It works as following: when a cache miss occurs, it makes a request to stream buffer controller. If the stream buffer is empty, stream buffer make a request to memory with the missed address. It is a burst mode of three line of instructions. When memory acknowledges the first data line is ready, it will route to cache by stream buffer controller. When the second line of data is ready it will send to stream buffer. It send shift in to the end of the stream buffer.

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When the 3rd line of data is ready, it just feeds in the front of the stream buffer and write in stream buffer. When cache miss occurs, and make request to stream buffer. If hit in stream buffer, stream buffer sends the line of data to cache and also move up data line. Any time there is a miss occurred in the stream buffer, it will make request to cache with the address that cache was miss on. Since memory won’t give the tag of data line, the stream buffer controller has to give a right tag when the data is ready to store in stream buffer. Supportive components, a counter inside the stream buffer keep status of the stream buffer. It tells if empty, and full. And a comparators tells whether the missed data line can find in stream buffer.

d) CAM-Based CacheIn order to improve the cache delay resulting from external comparators, we implemented CAM-based cache. This is simply done by combining the register file and the comparator via VHDL. The result is that a combined function set of both the comparators and the register file.

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e) Optimized Memory ControllerIn order to procure optimal performance from our processor architectures, a major overhaul of the memory controller was forthcoming. Previously, our datapath (Lab 6) suffered an unnecessarily long cycle time due to our original specification that exactly one state hold each RAS_L/CAS_L transition and that exactly one clock cycle elapse per state. However, the RAS_L precharge, RAS_L cycle, and CAS_L cycle times for the DRAM components were prohibitively long and thus severely limited our processor’s performance. Consequently, the memory controller has been refined with several notable improvements…

Memory controller optimizations:(1) Internally generate state transitions on every clock edge—whether falling or

rising.This enables the memory controller to minimize the time required per r/w request, while allowing the same number of state transitions to occur.

(2) Capability for handling a variable number of clock transitions per state.By dynamically timing RAS_L and CAS_L transitions, the clock period may be varied to virtually any value, thus removing the memory controller from all minimum clock cycle time considerations. Also, each state takes the exact minimum number clock transitions required.

(3) Minimize the number of states required per read/write operation.Previously, our memory controller (Lab 6) implemented a conservative four-state read/write finite state machine scheme. This has been optimized to the theoretical minimum of three states per r/w request: RAS_L high precharge time, RAS_L strobe, CAS_L strobe.

(4) Provide a triple-burst memory transfer option.The BURST3 option facilitates loading of the 4-word stream buffer and a cache block/line. Each transfer from our interleaved DRAM memory is 64-bits wide. This ad hoc, pseudo-triple burst, data retrieval is actually a dual burst—the maximum number of consecutive data read bursts allowed per atomic DRAM unit—followed immediately by a normal read cycle, all while holding the WAIT_H signal high. For the first burst pair, when data is ready, the DATA_RDY signal is held high until subsequent acknowledgement via a high DATA_ACK signal on a falling clock edge. The third data transfer proceeds as a normal read cycle, which indicates valid data by dropping WAIT_H; this final signaling scheme bypasses the overhead incurred by the asynchronous DATA_RDY/DATA_ACK protocol during the first burst pair and allows the memory controller to service any subsequent memory requests more quickly. Ultimately, this burst option reduces the impact of instruction memory access on total program execution time.

Note: Although internal state transitions may occur on any clock edge, signals to and from the external interface are validated only on the falling clock edge.

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3. Performance Summary

a) Critical Path1) (ID stage) From instruction sub cache -> instruction cache arbitration logic -> instruction

decider -> muxes =30ns2) (EXE stage) From mux -> ALU -> 6 muxes = 27.5ns3) (MEM stage) From memctrl -> data cache(cam + 6 muxes + logic gates) -> 2muxes = 22ns

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b) Overall

4. Testing PhilosophyThree basic testing principles are employed:

A. Component-level Design & TestingEach and every component is designed and tested individually for basic functionality.This isolation ensures that the external I/O interface behaves to specification.

B. Incremental Design & TestingThe BSQSP processor is built step-by-step—component-by-component. Upon each component’s integration into the processor, testing is allowed to proceed to completion and 100% unbridled confidence before the addition of the next component.

C. Regression TestingEvery major processor revision landmark is met with a completely regressive run of prior tests and programs.

Much akin to those well known, big chip companies, the confidence in the our Suzy Q overture is second to none, strongly punctuated by the fact that all encountered programs have executed flawlessly.

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5. Conclusion

After what seemed like a long and arduous journey, the hallmark of a great conductor’s persistence, our BSQSP processor promises to engross us all with unparalleled performances now and in the future. As with any other great musician, we now look to how we could improve ourselves for the next, great symphony.

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APPENDIXDATAPATH.1

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DATAPATH.2

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DATAPATH.3

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DATAPATH.4

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DATAPATH.5

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DATAPATH.6

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DATAPATH.7

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DATAPATH.8

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DATAPATH.9

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CAM_CACHE_ADRCOMP.1

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CAM_CACHE_COMP.1

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CAM_CACHE_COMP.2

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FORWARDER.1

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DOUBLEFORWARDING.1

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F_A_C.1

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F_A_C.2

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FAC_ADR_CHOOSER.1

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FAC_DATA.1

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FAC_INSTR.1

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FIFO.1

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FULLCACHE.1

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FULLCACHE.2

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FULLCACHE.3

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I_CACHE_ADR_REPLACE.1

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I_CACHE_COMP.1

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I_CACHE_COMP.2

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I_FAC.1

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I_FULLCACHE.1

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I_FULLCACHE.2

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INSTR_DECIDER.1

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INSTR_DECIDER.2

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INSTR_DECIDER.3

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INSTR_DECIDER.4

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INSTR_DECIDER.5

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INSTR_DECIDER.6

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INSTR_DECIDER.7

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MEM_Unit.1

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STG1_INSTR.1

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STG2_ID.1

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STG2_ID.2

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STG2_ID.3

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STG3_EX.1

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STRBUFFER.1 (not integrated)

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V_CACHE_ADR_REPLACE.1

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V_FAC.1—COMPLETE!

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V_FULLCACHE.1

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Draft version of the new Adaptive Memory Controller:

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