5KVA Inverter Boost H-Bridge

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    Bajopas Vol. 2 Number 1 June, 2009

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    Bayero Journal of Pure and Applied Sciences, 2(1): 6 - 13Received: November, 2008

    Accepted: February, 2009

    5KVA POWER INVERTER DESIGN AND SIMULATION BASED ON BOOSTCONVERTER AND H-BRIDGE INVERTER TOPOLOGY

    *Musa, A. and G.S.M. GaladanciDepartment of Physics, Bayero University, PMB 3011, Kano

    *Correspondence author

    ABSTRACTFive (5) kVA power inverter was designed and simulated base on two topologies; Boost converterand Half-bridge inverter topology. A 555 timer IC was used as the control at fixed frequencies of 25kHz and 50 Hz for the two stages. The results of the simulation were obtained. The graphs for bothstages were plotted and the results show a significant increase in the voltage and duty cycle. Thewave form of the output gives a square wave form.

    Keywords: Power inverter, Simulation, Topology, Converter

    INTRODUCTIONThe World demand for electrical energy is constantlyincreasing and conventional energy resources arediminishing and even threatened to be depleted. Withthe increasing popularity of alternative power sources,such as solar and wind, the need for static inverters toconvert dc energy stored in batteries to conventionalac form has increased substantially. This conversioncan either be achieved by transistors or by SCRs(silicon controlled rectifiers). For lower and mediumpower outputs, transistorised inverters are suitable butfor high power outputs, SCRs should be used.Transistor inverters are useful in wide variety ofapplications. They provide power to the complicated

    electronic systems of orbiting satellites and coolastronaut suits(http;//Guru/PEInverters/introduction/pdf/inv.pdf,2006).

    However, MOSFETs (Metal OxideSemiconductor Field Effect Transistor) and IGBTs(Insulated Gate Bipolar Transistor) are goodcandidates for the switches in dc to ac conventionaltechniques. With the development electronic devicesand circuits, newer equipment often have convertersthat allow the user to change the voltage andfrequency applied to the equipment .Power electronicsalso provides the industries with effective methods tosave energy and improve performance (Sen, 2002).

    Power electronic devices can be divided in totwo categories: Single component and hybrid

    component. The single component is composed of onesolid-state device, and hybrid component is acombination of several single componentsmanufactured as a single block. The single devices areloosely divided into three type :(1) the two layerdevices such as diode , (2) the three layer devicessuch as transistor , and (3) the four layer devices suchas the Thyristor . The hybrid components includewider range of devices such as the Insulated GateBipolar Transistor (IGBT), Static Insulated Transistor(SIT), and Darlington Transistor (DT). Solid statedevices are main building components of anyconverter. Their function is mainly to mimic themechanical switches by connecting and disconnecting

    electrical loads, but at very high speed. When themechanical switch is open (off), the current throughthe switch is zero and the voltage across its terminal isequal to the source voltage. When the switch is closed(on), its terminal voltage is zero and its current isdetermined by load impedance (Mukund, 2006) .

    Design Stage for fly Boost Converter and PowerInverterBoost converter designBased on the dc-dc converter topology; Boostconverter circuit design is shown with duty cycle (D),output input gain with pulse width modulation to drivethe converter at 25 kHz shown in Figure 1.0

    Figure 1.0: Boost converter schematic diagram

    PWM &

    V i

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    The output to the input voltage gain of the inverter is given by (Simon and Oliva, 2005).

    2.0

    and 2.1

    where , is the duty cycle of switching converter that is

    2.2

    where switched off time for the transistor

    switched on time for the transistor and

    which is define by the following relation

    2.3 a

    or 2.3 b

    However, with 555-timer ICs an inexpensive regulated SMPS is constructed, feedback and pulse widthmodulation were shown in Figure 2.0. If the desired inverter frequency and the voltage are known, the powerconsumed by the switching on and off of the converter can be estimated by the following equation(http://supertex.com/pdf/app.note/AN-36.pdf, 2008).

    2.4

    GND

    DI S

    OUT RST

    VCC

    THR

    CON

    TRI

    2

    0

    0

    3

    5

    0

    6

    7

    Fig. 2 DC-DC Converter

    0

    1

    0

    BatteryCin

    CTRD

    RC

    RFB

    555

    ZFB

    L

    Qsw

    D

    Cout

    0

    4 Vout

    Determine operating frequency, Duty cycle, and InductorNeglecting switch resistance, inductor losses, and other parasitic, the relationship between these

    parameters can be approximated by the following

    2.5

    Selection of a converter frequency is very important,since many applications require certain frequencies forEMI reasons. Higher switching frequencies allow theuse of smaller inductors but lead to high switching

    losses. Conversely, lower frequencies can reduceswitching losses but require large inductors. Converterin the range of 20 kHz-100 kHz are generally suitable.Duty cycle is calculated as follows.

    2.6

    The equation above yield duty cycles greater than 100%. For the inductor rating, peak inductor current can beapproximated using the following equation

    2.7

    Select Q sw and DFor switching transistor Q sw, the most importantparameters are break down voltage, on resistance,peak current, and power dissipation. For the diode,the important parameters are reverse break down

    voltage, peak repetitive current, and average forwardcurrent and reverse recovery time. Since peak inductorcurrent also flows through the switch and the diode, itmay be used to rate these components as well.

    2.8

    Maximum average current will occur at minimum input voltage

    2.9

    Figure 2.0 DC-DC Boost converter

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    Average power dissipation in the switch can be estimated from the following equation.

    3.0

    Where R sw = switch on resistance

    Select C in and C out Input capacitance C in functions as an input bypasscapacitor to reduce the effective source impedance

    and also EMI by restricting high frequency currentpaths to short loops.. For the best performance C in impedance should be less than 1 .

    3.1

    Where

    Output capacitance C out stores high voltage energyand also reduces EMI by restricting high frequencycurrent paths to stop short loops. The value of C out

    must largely dependent on the desired ripple voltageon Vout . Generally, ripple (as a fraction of outputvoltage) of about 10% is adequate.

    3.2

    Where I out = output current to the inverter,

    Ripple = and , both C in and C out should be high frequency

    types

    Select Timing Components ,

    Timing components , determine

    nominal converter frequency and maximum duty cycle.Selection of these components is an iterative process.

    The ratio sets the maximum possible duty

    cycle, while , together determine

    nominal output frequency. Maximum duty cycle canalso be calculated using the following equation.

    3.3

    The ratio must be greater than for proper operation of the 555 timer. If less, timing capacitor

    voltage will be unable to discharge to and output of the 555 will remain low. Nominal converter

    frequency can be calculated using the following equation.

    3.4

    Select Feedback components

    Output voltage is determine by the zener voltage plus an amount of bias voltage needed to vary duty cycle ofthe timing

    3.5

    The amount bias will vary depending on load and input voltage. The extreme limits of bias voltage are given inequations 3.6 and 3.7.

    3.6

    3.7

    and

    If is too low, it will prevent timing capacitor voltage from rising to as required for nominal

    operation of the 555, resulting in switch staying on and the current rising to destructive levels. To prevent

    this from occurring, the ratio of must always be greater than two.

    3.8

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    Power Inverter stage design However, in this part H-bridge inverter topology wasadopted. The half bridge inverter in the simplest formis shown is Figure 3.0 H-bridge inverter topology haslower number of switches and simplecontrol.(http://Guru/PEInverter/Half-bridge/pdf/inv.pdf, 2006). The duration of the deadband should be large enough to allow the switch that

    is turned off to close before the other switch, to startconducting. The advantage of H-bridge invertertopology has lower number of switches and simplecontrol (Emadi and Stoyan, 1992). The differential

    equation for the current from 0=t to 2T t = governing the current and voltage flows of half-bridgeinverter may be written as

    ( ) ( ) sV t Ridt

    t di L =+ 3.9

    Its general solution is of the form

    ( ) t s Ae R

    V t i += 4.0

    Where , the time constant for R-L load, is R

    L= , Applying the initial condition, that is

    ( ) maxmin0 I I i == when 0=t , we get max I RVs

    A = .

    Hence, the expression for the current in the circuit during 0=t and 2T t = is

    ( ) ( ) t t e I e R

    Vst i =

    max1 4.1

    The current attains its maximum value at 2T t = and is obtained from (4.1) as

    ( ) 2max2max 1 T e I e RV

    I T s =

    Rearranging the term we get

    +

    =

    2

    2

    max

    1

    1T

    T

    e

    e

    R

    Vs I 4.2

    Hence the current in the circuit during 0=t and 2T t = is

    ( ) ( )

    t

    T

    T st s e

    e

    e

    R

    V e

    R

    V t i

    +=

    2

    2

    11

    1 4.3

    Figure 3.0 (i) Half-bridge inverter with dual supply, and (ii) single supply

    MATERIALS AND METHODSTwo methods were employed for the inverter designedand simulation; the computer simulation with NIMultisim 10. Software and the circuit analysis using

    the above equations. The design topology which wasadopted is shown in Fig.4 with two stages; boostconverter and half-bridge inverter, and their controls.

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    Figure 4.0 DC-AC Inverter circuit designRESULTS:Based on the simulation and the equations above the results were plotted using origin 50 with the followinggraphs:

    0.0 0.2 0.4 0.6 0.8 1.0

    0

    2

    4

    6

    8

    10

    Buck Converter Boost Converter Buck-Boost Converter

    V out /V in

    Duty cycle(%)

    Figure 5.0 Graph of commonly converters compared analytically with equation 2.0 which shows the boost

    converter has high gain.

    0.88 0.89 0.90 0.91 0.92 0.93 0.94

    8

    10

    12

    14

    16

    18

    Boost Converter

    V out /V in

    Duty Cycle

    Figure 6.0 Graph of the gain to the duty cycle from the simulation result

    1 2 3 4 5 6 7 8 9 10

    0.0

    0.2

    0.4

    0.6

    0.8

    1.0

    B

    D ( d u t y c y c l e )

    RC

    /RD

    ratio

    Figure 7.0 Graph of maximum duty cycle with ratio of timing resistors

    Feedbac

    DC-DC (BoostConverter

    Control555-timer IC

    DC-AC (H-Bridge

    Control555-timer IC

    1st Stage 2 nd Stage

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    However, the nominal converter frequency waschosen to be 25 kHz which gave an inductor of 500 Hand inductor peak current I L(pk) using equations (2.6)and (2.7) with design power level of 700mW.Maximum duty is 70% at 6.0volt correspond to R C /R D

    ratio of 3.4 with equation 10; the R C value was 40.5k which indicated R D is 11.9k . For maximum regulation,R FB should be greater than 81.0k since R C was40.5k then R FB is slightly greater than 81.0k whichapproximately 90.0k

    0 20 40 60 80 100 120 140 160 1800

    10

    20

    30

    40

    50

    60

    70

    R C /R D =3 R C /R D =4 R C /R D =5 R C /R D =6 R C /R D =7 R C /R D =8 R C /R D =9 R C /R D =10

    F r e q e n c y (

    k H z )

    R C kohms

    Figure 8.0 Graph of nominal Converter frequency for C T = 1nF

    2 3 4 5 6

    20

    40

    60

    80

    100

    120

    140

    160

    180

    200

    R C /R D =3 R C /R D =4 R C /R D =5 R C /R D =6 R C /R D =7 R C /R D =8 R C /R D =9 R C /R D =10

    V B I A S

    ( v o l t )

    R FB /R C

    Figure 9.0 Graph of Bias voltages plot from equation (3.7)

    However, for maximum regulation R FB are slightly greater than two as equation (3.8). Since R C is 41.0k than R FB must be greater than 82 k but 90.0 k was selected.

    Figure 10.0 Converter output voltage from the simulation

    Figure 11.0 Output wave form for the two AND-gate

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    Figure 12.0 Inverter output voltage from the simulationTable 1.0 Requirement for Comparison

    12k

    90k

    41k

    7uF

    GND

    DI S

    OUT RST

    VCC

    THR

    CON

    TRI

    500uH

    2

    0

    0

    3

    5

    1nF0

    6

    702BZ2.2

    VN10LF

    4.7uF

    Fig. 2 DC-DC Converter

    0

    1

    6-12v Cin

    CTRD

    RCRFB

    555

    ZFB

    L

    Qsw

    D

    Cout

    VoutBAV21

    XSC1

    A B

    Ext Trig+

    +

    _

    _ + _

    0

    0

    8

    U1

    LM555CM

    GND

    1

    DI S7

    OUT 3RST 4

    VCC

    8

    THR6

    CON5

    TRI2

    R124k

    C2330nF

    R210k

    R3

    42k Key=A

    50%1

    0 0

    U3A74HC113D_4V

    1J3

    ~1Q 6

    1CLK 1

    1K 2

    1Q 5

    ~1PR

    4

    U4

    3554AM

    6

    5

    7

    2

    1

    2

    R4

    10k

    R5100k Key=A 50%

    6

    7

    00

    5

    8

    U2A

    7408NU2C

    7408N

    10

    11

    9

    U5A

    MCT62

    1

    8

    7

    U5B

    MCT64

    3

    5

    6

    R6

    7k

    R7

    7k

    3

    12

    0

    13

    14

    0

    XSC1

    A B

    Ext Trig+

    +

    _

    _ + _

    15

    16

    17

    18

    0

    0

    T1

    TS_POWER_25_TO_1

    12k

    90k

    41k

    7uF

    GND

    DI S

    OUT RST

    VCC

    THR

    CON

    TRI

    500uH

    1nF

    02BZ2.2

    VN10LF

    4.7uF6-12v Cin

    CTRD

    RC RFB

    555

    ZFB

    L

    Qsw

    D

    Cout

    VoutBAV21

    0

    22

    0

    27

    26

    0

    25

    24

    0

    0

    23

    0

    20

    4

    Q3

    IRFP250

    Q2

    IRFP250

    XMM1

    U7LM7812CT

    LI NEVREG

    COMMON

    VOLTAGE

    0 28

    2119

    S/no. Parameter Required Achieved1 Vout (converter) 48.0 V 100V2 Vout (inverter) 220V 220V3 P out (converter) 700mW 0.15W4 P out (inverter) 5kVA 2.09kVA5 Converter wave form Modulated Modulated6 Inverter wave form Modified Sine wave Square wave with

    distortion

    7 I out (inverter) 22.7 A 9.53A8 I Lpk 330mA 185.32mA9 Inverter Freq. 50Hz 48.6Hz10 Converter Freq. 25kHz 24.6kHz

    Figure 14. DC-DC/DC-AC power Inverter stage

    TS25T1 powerTransformer

    Figure. 13 DC-DC converter stages with the nominal calculated values

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    SUMMARY, DISCUSSION AND CONCLUSIONThe selection of the above topology simulated andworked with the nominal calculated values. It alsoshows that from table 1.0 the frequencies for bothconverter and inverter were close to the requiredvalues together with the wave forms.

    In conclusion, the circuits when simulatedperformed much better than the expected result dueto calculation assumptions and approximations. Itshows that the duty cycle of the converter changecompletely as seen from the Fig. 6 when comparedwith general topologies in Fig.5. It is also shown fromFig. 11 output voltage high than expected.

    REFERENCEShttp://Guru/PEInverters/introduction/pdf/inv.pdf 24th

    February, 2006PC Sen. (2002), Power Electronics . Tata McGraw-Hill

    publishing company limited, New Delhi, India,726p

    Mukund R. Patel (2006). Wind and Solar PowerSystem: Design, Analysis, and Operation (2 nd edition). CRC press, Taylor & Francis, U.S.A221-224pp

    Simon ANG and Alejandro Oliva (2005). PowerSwitching Converters, (2 nd edition) CRCpress, Taylor & Francis, 32-38pp

    http://supertex.com/pdf/app-note/AN-36.pdf 23thJanuary, 2008.

    http://Guru/PEInverte rs/Half-bridge/pdf/inv.pdf 24th February, 2006

    Ali Emadi Abdolhosein Nasiri and Stoyan B Bekiarou(1992). Uninterruptable Power Supplies& ActiveFilter .53p