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This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Diagnosis of MRAM Write Disturbance Fault

Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen,

Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen-Ching Wu,

Chien-Chung Hung, and Ming-Jer Kao

AbstractIn this paper, we propose a new test method to detect write dis-turbance fault (WDF) for magnetic RAM(MRAM). Furthermore, an adap-tive diagnosis algorithm (ADA) is also introduced to identify and diagnosethe WDF for MRAM. The proposed test method can evaluate process sta-

bility and uniformity. We also develop a built-in self-test (BIST) circuit thatsupports the proposed WDF diagnosis test method. A 1-Mb toggle MRAMprototype chip with the proposed BIST circuit has been designed and fab-ricated usinga special

0 1 5

- m CMOS technology. TheBISTcircuit over-head is only about 0.05% with respect to the 1-Mb MRAM. The test timeis reduced by about 30% as compared with the test method without usingthe decision write mechanism. The chip measurement results show the ef-ficiency of our proposed method.

Index TermsFault diagnosis, magnetic RAM (MRAM), memorytesting, nonvolatile memory, write disturbance fault (WDF).

I. INTRODUCTION

Many applications require a system-on-chip (SOC) to integrate

nonvolatile memories. Although flash memory is widely used today,

high voltage for program and erase operations, and some reliability

issues are hard to handle[1]. In recent years, the industry has tried

to find an appropriate nonvolatile memory that can replace flash

memory. MRAM is considered a good choice due to its high speed,

low operating voltage, and virtually unlimited read/write endurance

[2], [3]. We, therefore, see a growing need for MRAM testing and

diagnosis methodologies [4][8].

In recent years, there are two different types of MRAM that have

been proposed, i.e., the asteroid MRAM and the toggle MRAM. How-

ever, the asteroid MRAM devices have some problems such as the dis-turbance by half-selected cells and loss of data due to thermal agita-

tion [9]. The toggle MRAM has been proposed to solve that issue [10].

In general, compared with conventional asteroid MRAM, the toggle

MRAM hasbetter write andread margins,higherreliability, betterscal-

ability, etc. However, this does not mean the reliability andtest issuesof

toggleMRAM aresolved [11]. There are only a few technical paperson

MRAM testing so far. The authors in [4] propose some defect models

based on SPICE simulation forasteroid MRAM. Later, the write distur-

bance fault(WDF) model for toggleMRAM is proposed [5], [8], which

is a fault thataffects the datastoredin the MRAMcells due to excessive

magnetic field generated during the write operation. In general, March

test algorithms, which are widely used for memory testing, have linear

complexity and high coverage for conventional RAM faults; however,

it does not cover all WDFs. Also, the special quadruplet checker board

Manuscript received October 25, 2008; revised April05, 2009. This workwassupported in part by the National Science Council, Taiwan, under Grant NSC95-2221-E-007-258-MY3.

C.-L. Su and C.-W. Tsai are with the R&D Department, Skymedi Corpora-tion, Hsinchu 300, Taiwan (e-mail: [email protected]).

C.-Y. Chen, W.-Y. Lo, and C.-W. Wu are with the Department of ElectricalEngineering, National Tsing Hua University, Hsinchu 30013, Taiwan.

J.-J. Chen, W.-C. Wu, and C.-W. Wu are with the SOC Technology Center,Industrial Technology Research Institute, Hsinchu 31040, Taiwan.

C.-C. Hung and M.-J. Kao are with the Electronics and Opto-Electronics Re-search Laboratory, Industrial Technology Research Institute, Hsinchu 31040,Taiwan.

Digital Object Identifier 10.1109/TVLSI.2009.2026905

(QCKBD) pattern for asteroid MRAM [7] cannot detect all types of

WDF in the toggle MRAM. To improve quality and yield of MRAM,

BIST/diagnosis (BIST/D) also can be developed for MRAM, though so

far, it is widely used for RAM (and for some flash memory) products

to reduce test cost and failure analysis effort (see, e.g., [12][17]).

In this paper, which is extended from [6], we further improve the test

method, read previous, for MRAM WDF, and provide chip measure-

ment results to show the efficiency of our proposed test algorithm. Wealso develop a WDF test and diagnosis algorithm for toggle MRAM.

The authors in [14] propose a typical memory BIST circuit for SRAM

and DRAM. For a nonvolatile memory such as flash and MRAM, the

current-stress test method is widely used. Therefore, we combine the

RAM BIST design and the current-based test method to develop the

BIST/D circuit for toggle MRAM, which is able to test and diagnose

WDF. Since the decision write is an important feature for toggle

MRAM [6], our approach takes advantage of this feature to reduce

the total test time. A 1-Mb toggle MRAM prototype chip with the

proposed BIST circuit has been designed and fabricated using a special

0 : 1 5 - m CMOS technology. Results show that the area overhead of

the proposed BIST circuit for the 1-Mb toggle MRAM chip is only

about 0.05%. The test time is reduced by about 30% as compared with

the test method without using the decision write mechanism. Finally,

we discuss the test results of our MRAM test chips.

The rest of this paper is organized as follows. Section II introduces

the WDF for toggle MRAM and discusses our proposed test method.

In Section III, the diagnosis method for WDF is proposed. Simulation

and experimental results are shown in Sections IV and V, respectively.

Finally, Section VI concludes this paper.

II. TESTING FOR WDF

A. WDF Model

We proposed a new MRAM fault modelWDFin [8]. The data

storing/switching mechanism of MRAM is based on the resistancechange of the magnetic tunnel junction (MTJ) device in each cell.

The fan-shaped operating region of an MTJ cell defines the region

of the combined magnetic field for normal operation. Due to process

variation and other defects, the MTJ devices may not have uniform

operating regions. During the MRAM write operation, the magnetic

field may change the state of the MTJ cells. In Fig. 1, we illustrate the

magnetic field generated by a current on the bitline (BL) of the base

cell (the cell with a cross mark), assuming that the BL current flows

away from the eyes. By Amperes right-hand rule, the direction of

the magnetic field is clockwise. As shown in the figure, the magnetic

field affects all cells, except that the strength varies with respect to the

distance from the BL. A current on a write word line (WWL) has a

similar effect. These MTJ cells with significant operating region shift

may be easily disturbed by the magnetic field generated by the writeoperation of adjacent MTJ cells, i.e., the data stored in the bad cell

may be inverted (toggled) unexpectedly during the base cell operation.

Since the fault is activated due to the disturbance of the base-cell

magnetic field during the write operation, we call this fault the WDF.

The larger, the operating region shift of the victim cell, the more

aggressor cells may attack it. The strength of disturbance magnetic

field depends on the MRAM structure and the distance between the

base cell and the target one.

B. March-Like Test Method

To activate and observe WDF, we can toggle the data stored in the

aggressor cell, and then, read out the data stored in the victim cell to

verify it. March test algorithms are widely used for memory testing,

1063-8210/$26.00 2009 IEEE

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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 1. Magnetic field generated by BL current.

Fig. 2. Comparison between the traditional March test element and the pro-posed test method.

which is a class of linear-complexity tests with high coverage of con-

ventional RAMfaults. Under a March test, the entirememory cell array

is tested serially.

However, the number of write operations on aggressor cells before

reading the victim cell determines whether a WDF can be detected.

If even number of write operations have been performed, the fault in

the victim cell will be masked. Also, for an MRAM with cladding, the

WDF is most likely to occur in those four cells that are on the same

write lines with the base cell and most close to it. Accordingly, after a

write operation on a cell with WDF, an immediate read operation on

one of its adjacent cells is considered a solution to detect the WDF

before the fault is masked.

The test element ( r ; w ) is the shortest March test for some WDF in

[8], but it cannot cover all subsets of WDF. As March test algorithms

are widely used for memory testing, we combine the idea with March

test algorithm and propose a new test method for WDF in this paper.

Originally, ( r ; w ) applies a read operation anda write operation on each

cell in sequence. To avoid WDF masking, a read-previous operation

r

0 1

is proposed. It is appended to the write operation and results inthe test element ( r ; w ; r

0 1

) . The read-previous operation is applied on

the previous cell of the base cell, and thus, the test element ( r ; w ; r 0 1

)

can check the previous cell immediately after toggling a cell. Fig. 2

shows the comparison between the traditional March test element and

the proposed one. A typical March element * ( r ; w ; r ) is shown in

Fig. 2(a). We serially apply a read, a write, and another read operation

on cell i . Then, cell i + 1 experiences operations in the same sequence

and so on. Different from * ( r ; w ; r ) , the test element * ( r ; w ; r 0 1

)

applies a read and a write on cell i , and then, another read is applied

on cell i 0 1 instead. The subsequent read and write are applied on

cell i + 1 , and the next read jumps back again to cell i . The same

jumping sequence repeats. After each cell is written, their previous cell

is checked; therefore, this test element can detect WDF in MRAM.

Note that theproposed test method,read previous, can be applied in rowor column direction to test adjacent cells on the same row or column.

Furthermore, the read-previous test method can also be combined with

a typical test method to enhance testability for memory.

III. DIAGNOSIS FOR WDF

In this section, we discuss the diagnosis of WDF, which is done by

evaluating the shift amount of the operating region of a cell with WDF.

The proposed method is March-like test method. It can use logical test

method to evaluatethe process stability and uniformity of MTJdevices.

The proposed adaptive diagnosis algorithm (ADA) is composed of two

phasesthe detection phase and the current scan phase. In the detec-

tion phase, we run a 1 2 N test algorithm that is used for fault detection

and partial diagnosis. In the current scan phase, we use an adaptive al-

gorithm to simulate the aggressor behavior by scanning the WWL and

BL current levels (from low to high) on the faulty cells in MRAM. The

procedure is explained in detail as follows.

A. Phase 1: Detection Phase

The March C- test algorithm covers most conventional RAM faults

and WDF in [5], except for the subset WDF( e ; e )

[8]. We combine theread-previous operation with March C- and propose a new March-like

test algorithm, March RP, as follows:

m ( w 0 ) ; * ( r 0 ; w 1 ) ; * ( r 1 ; w 0 ; r

0 1

0 ) ;

+ ( r 0 ; w 1 ; r

0 1

1 ) ; + ( r 1 ; w 0 ) ; m ( r 0 ) ;

which is 1 2 N in time complexity, where N denotes the memory size.

The symbols * , + , and m indicate that the address sequence is in as-

cending order, descending order, and either of them, respectively. The

r and w characters denote the read and write operations, respectively.

The logic values 0 and 1 represent the solid (all 0 and all 1) data back-

grounds. The first w 0 operation initializes the whole memory to the 0

state.The proposed March RP can detect all conventional functional faults

and WDF. The addresses of faulty cells can also be located with the

proposed algorithm. Therefore, the Phase 2 test method can be applied

to these faulty cells only. Note that we stress the diagnosis of WDF in

this paper, though the proposed methodology is suitable for other faults

as well.

B. Phase 2: Current Scan Phase

In this phase, we perform the measurement of operating region shift.

To evaluate the shift of operating region, we use several different write

currents to test the MRAM faulty cells serially, and verify whether the

data are inverted or not. Therefore, we call the proposed method thecurrent-based testmethod. The algorithm is shown as follows:

m

v

( r ; w

1

B

1

; r B

1

; w

2

B

2

; r B

2

; . . . ; w

k

B

k

; r B

k

)

where v , wi

, and Bi

indicate the victim addresses, the i th write

operation with specific write currents, and the background of the i th

write operation, respectively. For our MRAM design, the disturbance

field strength for the WWL of the third adjacent cell is about 1% field

strength compared with the field of cell during normal write operation.

Therefore, we only choose three different test currents to simulate

disturbance field on WWL and BL. Note that we can use more test

currents to achieve a higher resolution when determining the operating

region shift. The current scan test may be not only for victim cells, but

also for all faulty cells to evaluate whole chip variation. However, itresults in higher area overhead and longer test time.

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Fig. 3. Die photograph of the 1-Mb toggle MRAM.

Fig. 4. Test time comparison for three test algorithms.

IV. SIMULATION RESULTS

A. Area Overhead

Fig. 3 shows the die photograph of our 1-Mb( 6 4 K 2 1 6 )

MRAMdesign. The MRAM chip is fabricated using a 0 : 1 5 - m CMOS tech-

nology. The total chip area is 1 1 : 5 mm 2 7 : 1 mm (including I/O

pads), and the memory core and BIST area are 1 0 : 2 mm 2 6 : 3 mm

and 0 : 1 9 mm 2 0 : 1 8 mm, respectively. The MRAM prototype chip

contains eight banks. To balance the delay from BIST to each block,

the BIST circuit is located in the center of this MRAM chip.

B. Test Time Evaluation

The proposed MRAM BIST integrates the decision write operation

[6], so the total test time is reduced. For the proposed ADA, phase 1

needs 1 2 N operations, where N denotes the memory size. In phase 2,

we assume that the algorithm scans nv

victims. Each victim has 13 op-

erations (six test points in phase 2), as described before. Therefore, thediagnosis time complexity of the proposed ADA is 1 2 N + 1 3 nv

. The

diagnosis time increases only slightly if N nv

. If we increase the

number of test points (currents), we have a higher diagnosis resolution,

but the total test time also increases. Three test algorithmsMarch C-,

March- 1 7 N [18], and ADAare experimented on the proposed BIST

circuit. The test time comparison is shown in Fig. 4. In the figure, nv

stands for the amount of MRAM cells with WDF for ADA. March C-

and March- 1 7 N have about 40% and 25% test time reduction, respec-

tively. Finally, the test time reduction for ADA are close to 30%.

V. EXPERIMENTAL RESULTS

A. Evidence of WDF

Considering WDF, we write only one MTJ cell before checking thedata stored in other MTJ cells to avoid fault masking. However, the in-

TABLE IPROBABILITIES OF DISTURBANCE FOR CELLS j d j ROWS

ANDj d j COLUMNS AWAY

fluence of magnetic field is proportional to the inverse of the square of

distance. Therefore, after a write operation, we check only its neigh-

borhood, i.e., a surrounding 9 2 9 subarray. For example, after writing

cell ( x ; y ) , we read cells ( x + dx

; y + d

y

) , where 0 4 dx

; d

y

4 .

The corresponding test algorithm is shown as follows:

* ( r 0 ) ; * ( w 0 ; *

v

( r 0 ) ) ; : (1)

The first read operation is to verify stored data in the whole memory.

Then, after each write operation, we read the surrounding 9 2 9

subarray ( *v

( r 0 ) ) to check whether the cells are disturbed or not.

Table I lists the probabilities of disturbance for cells j dx

j rows and

j d

y

j columns away from the cell being written. We can see that 90.2%

of the cells operate correctly from the entry (0,0). Furthermore, the

number of disturbed cells decreases with distance j dy

j ( j d

x

j ) . We

also see that in this particular MRAM chip, cells with j dx

j = 0 and

j d

y

j = 1 are much more likely to be disturbed than others (about

1.64%). And the disturbance is mainly between cells on the same row

or column, i.e., j dx

j = 0 or j dy

j = 0 .

B. March Test Result

To verify the test efficiency, we apply the proposed March RP test

algorithm to a real chip. The chip under test is a 64-kb MRAM pro-

totype, which has 8-k words and 8 bits in each word, and an Agilent

V4000 tester is used to perform the test. We apply both March C- and

theproposedMarch RP to compare their test strength.Moreover,a 1 2 N

March test, which replaces the read-previous operations in the March

RP by typical read operations, is also applied to prove test strength of

the read-previous operation. Three test algorithms applied are listed in

Table II.

Table III shows a comparison of test results from the three test al-

gorithms, where items word yield and bit yield denote percentage of

fault-free (FF) words and FF bits, respectively. For example, with the

March C- test, 22.17% of the words in the memory under test are FF

words, but 83.11% of the bits in it are FF. We can see that the MRAM

chip has high bit yield, but low word yield, which reveals that the faults

distributed uniformly in the memory. Furthermore, compared with theother two algorithms, it gets lower yield under March RP test, i.e.,

March RP can detect more faults. It shows that the read-previous oper-

ation in the proposed March RP test algorithm increases fault coverage

for MRAM.

We further analyze the test response from the tester. Table IV lists

the fault syndrome statistics of the MRAM chip under March C- and

March RP, respectively. We just list the top ten fault syndromes and

the corresponding fault types. From the table, about 83% of the cells

are FF, and among the faulty ones, SAF(0) appears most frequently,

where SAF denotes stuck-at-fault. Note that the WDF syndrome ap-

pears, which is the evidence for WDF. In addition, some of the ob-

served faults are unmodeled (denoted by a hyphen in the fault-type

entry). Since the process parameters are still being tuned, the device

is not stable enough, so there are small differences in the two test runsof the same chip.

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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE IITHREE APPLIED TEST ALGORITHMS

TABLE IIICOMPARISON OF THREE TEST ALGORITHMS

TABLE IVSTATISTICS OF FAULT SYNDROME

Fig. 5. Measured operating region distribution of a typical toggle MRAM.

C. Current-Based Test Result

Note that theeffect of magnetic disturbance is not very stable. There-

fore, we apply current-based test method on all cells in the MRAM.

Fig. 5 shows the distribution of MTJ-cell operating regions from thechip measurement results. Different colors in the figure represent dif-

ferent percentages of good MTJ cells under the corresponding write

currents. For example, there are 85% of the cells that operate correctly

under specific write currents (marked X in the figure). We can see that

the operating region variation is more significant on BL than on WWL,

and the optimal operating points on WWL and BL are both about 3000

mV. On the other hand, the cells are most likely disturbed when we are

writing the cell on the same WL. Note that this measurement result is

similar to that in Section V-A.

Tables V and VI list the percentages of cells under different BL

and WWL currents, respectively. The second rows of these two tables

show the number of operable cells under specific write currents, e.g., in

Table V, there are 13.3% cells that are operable under 1200 and 3000

mV on BL and WWL, respectively. Furthermore, we compare the lo-cations of operable cells with test results using March C- and March

TABLE VPERCENTAGE OF CELLS UNDER DIFFERENT BL CURRENTS( V = 3 0 0 0 mV)

TABLE VIPERCENTAGE OF CELLS UNDER DIFFERENT WWL CURRENTS

( V = 3 0 0 0 mV)

RP. The third and last rows of these tables list the number of faulty

cells that are identified by the corresponding test algorithms, but can

be operated correctly using specific write currents. For example, there

are 2.52% cells that are faulty as detected by March RP, and are op-

erable under 1200 and 3000 mV on BL and WWL, respectively. With

these test results, we can see that there are 1 3 : 3 % 0 2 : 5 2 % = 1 0 : 7 8 %

FF cells identified by March RP, but they can be operated correctly by

lower write voltages. Note that the number of operable cells is close

to the number of faulty cells detected by March algorithm as the write

currents decrease. In other words, the cells with significant operating

region shift may easily fail. Moreover, these results show that not all

cells with operating region shift are faulty, so it is not cost-effective toscan all cells.

VI. CONCLUSION

In this paper, we have discussed the test and diagnosis of WDF for

toggle MRAM. A special test method, the read-previous operation,

has been proposed to improve the coverage of WDF. Furthermore, an

adaptive diagnosis algorithm has been presented for diagnosis of the

WDF and evaluation of the shift amount of the operating region for an

MRAM cell. The proposed test algorithm has linear time complexity,

and can easily be implemented with BIST. We have presented a BIST

circuit that supports the proposed WDF diagnosis test method. We also

have integrated into the BIST scheme a test time reduction approach

based on the decision write mechanism of the toggle MRAM. A 1-Mbtoggle MRAM prototype chip with the proposed BIST circuit has been

designed and fabricated using a special 0 : 1 5 - m CMOS technology.

The BIST circuit overhead is only about 0.05%. The test time reduction

is about 30% for the three important test algorithms experimented, as

compared with the test method without using the decision write mech-

anism. Finally, the MRAM chip measurement results justify the effi-

ciency of our proposed test method and algorithm.

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