50Gb/s SiGe BiCMOS 4:1 Multiplexer and 1:4 Demultiplexer for Serial

Communication Systems

Mounir Meghelli, Alexander V. Rylyakov, Lei Shan

IBM T. J. Watson Research Center

OUTLINE

Motivation

4:1 Multiplexer Architecture

1:4 Demultiplexer Architecture

Measurement Results

Conclusion

Motivation

SONET OC-768: next generation for long-haul optical transmission systems at 40Gb/s data rate

Line rate can be as high as 50Gb/s when using FEC schemes

Cost effective, low power ICs still need to be demonstrated

SiGe BiCMOS technology good candidate?

Designs Overview

Data rate target: 50Gb/s

Half rate clocking

Low supply voltage: -3.6V

MUX/DMUX inputs/outputs data are unstaggered in time

0.18µm SiGe BiCMOS technology* with 120GHz FT and 100GHz Fmax NPNs

*A. Joseph, et. al., "A 0.18um BiCMOS Technology Featuring 120/100GHz (fT/fmax) HBT and ASIC-Compatible CMOS Using Copper Interconnect" Proc. BCTM, pp. 143-146, 2001

OUTLINE

Motivation

4:1 Multiplexer Architecture

1:4 Demultiplexer Architecture

Measurement Results

Conclusion

4:1 MultiplexerBlock Diagram

2:1

2:1

2:1/2

D0

D2

D1

D3

Clock Output

Clock/2

ECL Latch

Clock

Data

VCS

Out

-3.6V

Gnd

2:1 MultiplexerBlock Diagram

LatchLatch

LatchLatch Latch

SEL

D0D0BCCBD1D1B

C CB

DDB

QQB

C CB

DDB

QQB

C CB

DDB

QQB

C CB

DDB

QQB

C CB

DDB

QQB

QQB

D0

D1

CkOutput

FF1

FF2

2:1 Multiplexer Timing

FF1

FF2 L1

SEL

D1

D2

D3

D4 D5

Ck D6

tpd_FF < Tck / 2 = 25ps @ 40Gb/s

A1 A2 A3 A4 A5

B1 B2 B3 B4 B5

A1 A2 A3 A4 A5

B1 B2 B3 B4 B5

B1 B2 B3 B4 B5

A1 B1 A2B2 A3 B3 A4 B4 A5

D1

D2

Ck

D3

D4

D5

D6

tpd_FF

Tck

Stage to Stage Timing

tdiv+ tsel1 < Tck = 50ps @ 40Gb/s

tdiv

tsel1

Tck

Ck

D0

Ckdiv

FF1

FF2 L1

SEL1Ckdiv

DIV/2

FF3

FF4 L2

SEL2Ck

D01st 2:1 MUX 2nd 2:1 MUX

Data Input Buffer

50Ω

In

Out

-3.6V

Gnd

Ref

Clock Input Buffer

50Ω

TIS

TAS

InputBuffer Amp1 Amp2Ck_In Ck_Out

Data Output Buffer

50Ω 50ΩIn

Out

-3.6V

Gnd Inductive peaking

Shunt capacitor

OUTLINE

Motivation

4:1 Multiplexer Architecture

1:4 Demultiplexer Architecture

Measurement Results

Conclusion

1:4 DemultiplexerBlock Diagram

D00

D01

D10

D11

Data 1:2

1:2

1:2

bit skip

ClockClock/2

/2

1:2 DemultiplexerBlock Diagram

LatchLatch

LatchLatch Latch

CB C

DDB

QQB

CB C

DDB

QQB

C CB

DDB

QQB

C CB

DDB

QQB

C CB

DDB

QQB

Data

Clock

D1

D0

FF1

FF2

Chips Photographs

1:4 DMUX(1.7x1.7mm2)

4:1 MUX(1.7x1.7mm2)

OUTLINE

Motivation

4:1 Multiplexer Architecture

1:4 Demultiplexer Architecture

Measurement Results

Conclusion

MUX and DMUX Testing

On-waferPPG used limited to ~14Gb/sBERT used limited to ~13Gb/sBER of MUX / DMUX checked at low speedMUX switching behavior tested up to 56Gb/sDMUX BER checked at 12.5Gb/s with 25GHz clock (corresponds to 50Gb/s operation)

Packaged MUX and DMUX enabled BER testing at speed

On-Wafer 4:1 MUX Testing

2 ps/div

50 m

V/di

v

56 Gb/s: test equipment maximum speed

Vee = -3.3V231-1 PRBST = 25oC

Package Description

Chip

Ceramic

Aluminium/Graphite housing

Ground

GroundSignal

Gold ribbon bonds

12 mil

Alumina, εr=9.8Gold metalization

Package Photograph

V-connector

1.95 x 1.75 inch

Feed-through with internal cap

CPW transmission line

4:1 MUX Measurement Results

5 ps/div

100

mV/

div

20GHz input clock

40Gb/s eye-diagram (on wafer, 100oC)

40Gb/s eye-diagram (packaged sample)

Back-to-Back MUX/DMUX Test Setup

Packaged 4:1 MUX

Packaged 1:4 DMUXPPG

4x10Gb/s231-1 PRBS

1x40Gb/s231-1 PRBS

BERT

Clock Source

20GHz

10GHz

10GHz

Parallel Data Parallel DataDelay Line

4x10Gb/s231-1 PRBS

Back-to-Back MUX / DMUX TestingD00

D01

D10

D11

40Gb/s error free operation ( BER<10-15 )

Horz: 20ps/divVert: 100mV/div

1:4 DMUX outputsat 10Gb/s

Back-to-Back MUX / DMUX Testing

5 ps/div

20 ps/div

50 m

V/di

v10

0 m

V/di

v

50Gb/s 4:1 MUX output

12.5Gb/s 1:4 DMUX output

50Gb/s error free operation ( BER<10-15 )

Measurement Summary

4:1MUX 1:4DMUX

Nominal supply voltage -3.6V -3.6V

Power consumption 1.47W 1.55W

Core power consumption 0.93W 0.93W

Max speed (BER<10-15) 52.2Gb/s 52.2Gb/s

Clock phase margin@40Gb/s 11ps (44%)

Clock phase margin@50Gb/s 6ps (31%)

Conclusion

Demonstrated up to 52.2Gb/s 4:1 Multiplexer and 1:4 Demultiplexer ICs (first pass success)

Successfully packaged ICs enabled bit error rate testing at speed

SiGe BiCMOS technology suited for high speed wired communication applications