4bit Parallel to Serial Data Stream Converter

By

Ronne Abat

Johnny Liu

Agenda•Specifications

•D Flip Flop

•Test Bench

•Timing Analysis

•Fabrication

•Conclusion

Specification•4bit Parallel to Serial Data Converter

-At 25Mhz, Period = 40ns

-Using Positive Edge Trigger Clock

-Registers reset when clear = 0

-Drive a 10pf load

-AM16 Process

-Power Consumptions lower than 500mW

-Area less than 40mm square

Top Level Schematic

D Flip Flop Schematic

D Flip Flop Transient Response

D Flip Flop H-L

D Flip Flop L-H

Write Mode Test Bench

Transient Response Write Mode

Shift Mode Test Bench

Transient Response Shift Mode

Layout

Conclusion

• All specs were met except for

• - extracted

• - power

• - timing on serial outputs