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EE 415: VLSI Design I

Lab 4: ASIC Design Flow I

Jacien Squires

291-84-0440

Mailbox # 561

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Introduction

Purpose of Lab 4

In the next two lab exercises, an 8-bit ripple adder will be designed using a traditional full-custom ASIC design flow. But first, two basic gates, two-input NAND and XORmust be

designed on transistor level and circuit level.

This lab uses Design Architect, QuickSim II, IC station,Lsim and AccusimII. Also, amore productive layout design method,Schematic Driven Layout (SDL), aprocedure in

ICStation, will be used. This lab covered:

1. Two-input Nand gate design.

2. Xor gate design.

3. Schematic driven layout design with IC Station.

4. Post simulation with AccuSim II and/or Lsim.

Design of VLSI Component

Two-input Nand gate design:

Using Design Manager and the techniques learned from lab1, a two-input NAND gatewas constructed according to the following diagram:

Figure 1: Schematic and Stick Diagram of a two input Nand gate

Once the schematic was completed, a symbol was created, followed by the design of the2-input NAND gate cell.

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Figure 2: Two-input Nand Cell

The techniques described in Lab 3 were used to DRC (ICRules) and LVS (ICTrace) the

nand2 device. Any rule violations were corrected and a Parasitic Extraction (PEX) was

performed upon the Nand2 device. The nand2.N and nand2_ascii files were created.

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Xor gate design:

Once again, design manager was used to create a schematic and symbol for the XOR

gate. Using the inverter designed in lab 1, the schematic was designed as shown:

Figure 3: XOR Schematic

Schematic driven layout design with IC Station:

ICstation was invoked and using the given instructions along with the SDL option, a cell

for the XOR gate was designed. The given diagrams were used to complete the design of thecell. The completed cell is shown below.

.

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Once again, the techniques described in Lab 3 were used to DRC (ICRules) and LVS (ICTrace)

the xor2 device. Any errors encountered were corrected and a Parasitic Extraction wasperformed upon the Xor2 device. The xor2.N and xor2_ascii files were both created.

Test Process

Post simulation with AccuSim II and/or Lsim

1. Design rules checking (DRC) with ICrules

The cells that were created were checked using the design rules in ICstation. Any

violations that where found where corrected and the cell was checked again. After passing all

tests, the cells were saved.

2. Layout versus schematic (LVS) with ICtrace

LVS compares the schematic connections created in Design Architect to the net

connections made in the IC Station. There are two types of layout versus schematic (LVS)

verification, Direct and Mask.

Direct mode compares the electrical connectivity at the current hierarchy and stores theconnectivity information directly within the cell. This mode allows for top down design where

subcomponents may not be implemented yet. Direct mode views subcomponents from a "Black

Box" perspective.

Maskmode compares electrical connectivity of the entire ICgraph hierarchical layoutwith the connectivity of the source circuit. Mask mode is the most complete connectivity

checking but on large designs it requires excessive time to extract at every hierarchy.

ICtrace was used to set up the LVS (Mask) test. The test passed for the Nand gate and

passed with errors for the Xor gate.

3. Parasitic extraction (PEX) with ICextract

ICextractpermits a parasitic extraction (PEX) from the device cell and schematic layout.You can either have a netlist forLsim orHSPICE and /or a back annotation file attached to your

schematic or both. In this lab, Lsim netlist and ASCII BA (Back annotation) files were createdforAccusim II. Both AccusimII and Lsim allow the designer to simulate the analog

performance of the device. This process was completed successfully.

4. Post simulation with Lsim

Lsimis a comprehensive mixed-signal, multi-level simulator. The program was loadedand run, producing the following results:

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NAND Gate

XOR Gate

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5. Post simulation with Accusim

AccuSimII shows rise/fall times and effects caused by different lengths and widths oftransistors. Simulators such as QuickSim may show that the circuit works digitally but the

analog simulatorAccuSimII might show that it does not due to delay through the transistors.

AccuSimII was setup and the analysis was run, resulting in the following output:

NAND Gate

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XOR Gate

Troubleshooting

This lab was very difficult and time consuming. The AccuSim results seem to be correctfor both gates and the Lsim results for the NAND gate appear correct as well. The Lsim results

for the XOR gate, however, do not appear to be correct. The lab was done per the instructions

given and all testing produced no errors. There was a slight error in the XOR gate lvs

simulation. The test reported no errors except for a naming error. This may be what caused thelsim simulations to be incorrect. The lvs report is given at the end of this report.

Conclusions

The nand gate appears to be designed correctly. There seems to be a problem with thecell diagram of the Xor gate. The problem did not halt the simulation process, but may haveaffected the output of the simulation. I was unsure as to how to fix the naming error.