40G Daughtercard Functional Debug Manual 00-03

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Metro Ethernet Networks

Issue Date: 23 December 2009 Stream 00

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40G Daughtercard Functional Test

DEBUG MANUAL ________________________________________________________________

Originator / site: Will Leckie / CARFunction: Electro-Optic Hardware DesignerContributor(s): Yves BeaulieuDesign Manager: Doug McGhan

________________________________________________________________

Applicable Products:

Product Engineering Code Common Product CodeNTK53950E5

Nortel NetworksMetro Ethernet Networks3500 Carling Ave. Ottawa, OntarioK2H 8E9CANADA

2009 Nortel Networks All rights reserved.UNCONTROLLED COPY: The master of this document is stored on an electronic database and is writeprotected; it may be altered only by authorized persons. While copies may be printed, it is not

recommended. Viewing of the master electronically ensures access to the current issue. Any hardcopiestaken must be regarded as uncontrolled copies.NORTEL NETWORKS CONFIDENTIAL: The information con tained in this document is the prop ertyof Nortel Networks. Except as specifically authorized in wri ting b y Nortel Networks, the hold er ofthis d ocument sh all: (1) keep all inform ation contained herein confi dential and shall protect samein whol e or in part from dis closur e and diss emination to all third parties and (2) use same foroperating and maintenance purposes only.


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NORTEL NETWORKS CONFIDENTIAL Page 2 of 57

Revision HistoryRevision date Description of changes Changes by23 June 2009 First version Will Leckie10 September 2009 Added detail throughout Will Leckie4 December 2009 Updated the manual Tx provisioning procedure to

capture EOC infoWill Leckie

23 December 2009 Updated RF driver debug procedure Will Leckie


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ContentsRevision History ............................................................................................................................. 2Contents .......................................................................................................................................... 31. General.................................................................................................................................... 5

1.1. Scope............................................................................................................................... 51.2. Related Documents ......................................................................................................... 5

2. oAGC Pre-VOA Sanity Test................................................................................................... 62.1. Example: healthy unit ..................................................................................................... 62.2. Example: ADC readings ok but measured input power wrong ...................................... 62.3. Example: both ADC readings too low ............................................................................ 72.4. Example: both ADC readings too high........................................................................... 82.5. Manual debug.................................................................................................................. 8

3. oAGC VOA Functional Test .................................................................................................. 93.1. Example: healthy unit ..................................................................................................... 93.2. Example: post-VOA power/ADC readings are all low................................................. 103.3. Example: post-VOA power/ADC readings are all high ............................................... 11

4. oAGC Closed Loop Sanity Test ........................................................................................... 124.1. Example: healthy unit ................................................................................................... 124.2. Example: failed unit ...................................................................................................... 13

5. oAGC Post-VOA Tz Oscillation Test................................................................................... 145.1. Example: healthy unit ................................................................................................... 145.2. Example: power delta is ok but RIN is high for all VGA DAC ................................... 15

6. oAGC Dynamic Test............................................................................................................. 17

7. Rx Signal Path Insertion Loss Test....................................................................................... 187.1. Example: healthy unit ................................................................................................... 188. Rx LO Path Insertion Loss Test............................................................................................ 20

8.1. Example: healthy unit ................................................................................................... 209. Beat Efficiency Test.............................................................................................................. 22

9.1. Example: healthy unit ................................................................................................... 2210. Tx Startup.......................................................................................................................... 25

10.1. Overview................................................................................................................... 2510.2. -21V Test etc............................................................................................................. 2610.3. Laser Comms Test .................................................................................................... 2710.4. Drv Self Test ............................................................................................................. 28

10.4.1. Initial checks ......................................................................................................... 2810.4.2. Example: same driver always fails ...................................................................... 2810.4.3. Example: intermittent driver failures .................................................................... 29

10.5. PIN DC ADC Test .................................................................................................... 3110.5.1. Initial sanity checks............................................................................................... 3110.5.2. Example: voltages measured on a good unit......................................................... 3110.5.3. Example: Unstable signal input at mux (U50)...................................................... 3210.5.4. Example: High voltage at first stage Tz input ...................................................... 32


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10.6. PIN AC ADC Test .................................................................................................... 3310.6.1. Initial sanity checks............................................................................................... 3310.6.2. Example voltages measured on a good unit.......................................................... 33

10.7. PIN DC ADC Out Test ............................................................................................. 3410.7.1. Initial sanity checks............................................................................................... 3410.7.2. Example voltages measured on a good unit.......................................................... 3410.7.3. Example: High voltage at first stage Tz input ...................................................... 34

10.8. Laser Tuning Test ..................................................................................................... 3510.9. MaxMaxMax Test; Max Photo Test ......................................................................... 3610.10. MZ1/2/3 DAC Test; Optic Path Test ........................................................................ 3710.11. MZ1/2/3 AC Sweep Test; MZ1/2/3 MDAC Test ..................................................... 3810.12. Tz Test ...................................................................................................................... 3910.13. SecHarmShift Test, Ref Shift Test, Phase Err Test .................................................. 4010.14. 25KHz Gen Test ....................................................................................................... 4110.15. Extinct Rat Test......................................................................................................... 4210.16. Trew Test .................................................................................................................. 4310.17. Driver Tests: Vg Lo Drv Test/Vg Hi Drv Test; Vc Lo Drv Test/Vc Hi Drv Test; ElEff Lo Test/El Eff Hi Test; Eff Rat Lo Test/Eff Rat Hi Test.................................................... 44

10.17.1. Example: driver electrical efficiency is bad, with no ADC clipping............... 4510.17.2. Example: driver electrical efficiency is bad, but has ADC clipping................ 4610.17.3. Example: Manual driver debug online............................................................. 47

10.18. ModLoss LoDrv Test/ ModLoss HiDrv Test............................................................ 4910.19. Opt Dith Out Test...................................................................................................... 5010.20. Power Margin Test.................................................................................................... 5110.21. Manual Tx Debug Instructions ................................................................................. 52

10.21.1. Firmware applicability ...................................................................................... 5210.21.2. Starting the Tx manually................................................................................... 5210.21.3. Dump EOC Info................................................................................................ 5310.21.4. Manually inspecting NRZ optical eye on DCA................................................ 53

11. Tx Insertion Loss Test ...................................................................................................... 5411.1. Example: healthy unit ............................................................................................... 5411.2. Example: both X-pol and Y-pol losses are too high ................................................. 5411.3. Example: XY loss difference too high...................................................................... 55

12. Tx VOA Functional Test .................................................................................................. 5613. Tx EO Connectivity Test .................................................................................................. 57


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1. General

1.1. Scope

This document gives debug guidelines for 40G Daughtercard Functional Test failures.

1.2. Related Documents

[1] 40G Tx Application Self Testing by Yves Beaulieu. This document referencesIssue 0.03 dated July 11, 2008 for Firmware Version 5.15

[2] 43GB NGM-DPC OCLD LINE CARD OPTICAL DAUGHTER CARDSchematic


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2. oAGC Pre-VOA Sanity Test

Open the .log file and scroll to the very bottom to the latest log info. Scroll back up tofind the latest entry for the oAGC Pre-VOA Sanity Test:

DBfunc_OagcPreVoaSanityTest: oAGC pre-VOA sanity test:

2.1. Example: healthy uni t

An example of a good result is shown below:

checkLaserUutPower: checking Laser-UUT power: measureUutInputPower: checking UUT input power: measureUutInputPower: pre-VOA ADC reading: 7419 lsb measureUutInputPower: Expected input power: 0.000 dBm measureUutInputPower: Measured input power: -0.131 dBm measureUutInputPower: Input power delta: -0.131 dB

DBfunc_OagcPreVoaSanityTest: pre-VOA sanity test:DBfunc_OagcPreVoaSanityTest: High power...DBfunc_OagcPreVoaSanityTest: ADC high= 7431 lsbDBfunc_OagcPreVoaSanityTest: Low power...DBfunc_OagcPreVoaSanityTest: ADC low= 741 lsb

Notes about the healthy unit:

The pre-VOA ADC reading in the measureUutInputPower section is ~7000

The ADC high reading is roughly the same as the pre-VOA ADC reading in the measureUutInputPower section. The ADC low reading is about 1/10 th the valueof ADC high (since the optical power is 10 dB lower).

The Measured input power is very close to the Expected input power

2.2. Example: ADC readings ok but measured inpu t power wrong

In the example below the raw ADC readings make sense but the Measured input power is wrong:


DBfunc_OagcPreVoaSanityTest: pre-VOA sanity test:DBfunc_OagcPreVoaSanityTest: High power...DBfunc_OagcPreVoaSanityTest: ADC high= 7431 lsbDBfunc_OagcPreVoaSanityTest: Low power...


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DBfunc_OagcPreVoaSanityTest: ADC low= 741 lsb

If the Input power delta fails spec, the Measured input power is too far fromthe Expected input power . The Measured input power is calculated from theADC reading, prefunc cal data, and Rx pre-VOA tap (tap1) EDT data fromEEPROM/Proligent database.

Compare the raw ADC high and ADC low readings to those of the healthy unit in Section2.1. In this case, since the raw ADC readings make sense compared to the healthy unit,the hardware (tap1, Tz circuit and ADC) are all working correctly. The problem must bewith the prefunc cal data and/or EDT data from the EEPROM/Proligent database. Checkthe values for prefunc cal data and/or EDT data that retrieved from theEEPROM/Proligent database.

A similar example is shown below, where the ADC reading makes sense but the input power is calculated as + infinity. The root cause in this case was invalid prefunc cal dataand EDT data in the EEPROM/Proligent database.

checkLaserUutPower: checking Laser-UUT power: measureUutInputPower: checking UUT input power: measureUutInputPower: pre-VOA ADC reading: 7354 lsb measureUutInputPower: Expected input power: 0.000 dBm measureUutInputPower: Measured input power: +Inf dBm measureUutInputPower: Input power delta: +Inf dB

2.3. Example: both ADC readings too low

In the example below the ADC readings for both the High power and Low power caseare close to zero:


If the ADC reading is close to zero, the voltage at the ADC is close to zero. Either no

light was detected by the Rx pre-VOA tap (tap1), or there is a problem in the Tz circuitry between tap1 and the ADC.

1. Double check that tap1 is soldered to the correct holes on the PCB.2. Double-check that the tap1 input pigtail does in fact go out to the UUT Rx input

connector. The tap1 package shows an arrow in the direction light is supposed totravel from input to output. The pigtail exiting the package of tap1 on the input sideshould go out to the UUT Rx input connector. Its possible the tap1 supplier put the


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connector on the output pigtail instead of the input pigtail, so that the light is goingthrough tap1 backwards.

3. The tap1 photodiode may be faulty or the tap1 Tz/ADC circuitry may be faulty. Goto Section 2.5 to manually debug the circuitry.

2.4. Example: both ADC readings too high

In the example below the high power and low power ADC readings are both higher thanexpected, and the low power reading is not about 10% of the high power reading:


If both ADC readings are much higher than expected, and the low power ADC reading isnot ~10% of the high power reading, then the problem most likely is with in Tz/ADCcircuitry. In this case the mux or ADC is the likely culprit. Go to Section 2.5 tomanually debug.

2.5. Manual debug

1. First verify that the tap1 electrical connection to the Tz input is ok: use themultimeter to do a continuity test between pin 2 of tap1, and pin 2 of U49. If there is

no continuity, either the tap1 pins are not soldered into the board, or there is a breakin the PCB track.2. If continuity is ok, power up the card and run the OCLD init script. After the script

finishes measure the voltage at pin1 of tap1; the voltage should be ~-3V. If not, thereis a problem somewhere between the source of the -3V supply and pin1 of tap1; focusattention there.

3. Probe the supply voltages at U49 and U168 (Tz op-amps for Rx pre-VOA tap), and atU50 and U54 (mux and ADC). These supply voltages should be as expectedaccording to the circuit schematic [2]; if not focus attention on the supply circuits.

4. If the supplies are ok, inject 0 dBm of optical power into the UUT Rx port. Probe thesignal voltage through U49 and U168 (Tz op-amps for Rx pre-VOA tap) up to U50and U54 (mux and ADC). Pay special attention to any difference between the voltageat the output of the Tz stages (U168 pin 1) and the voltage at the input to the mux(U50 pin 6).

5. If all the supply and signal voltages are ok, replace tap1.


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3. oAGC VOA Functional Test

Open the .log file and scroll to the very bottom to the latest log info. Scroll back up tofind the latest entry for the oAGC VOA Functional Test:

DBfunc_OagcVoaFunctionalTest: oAGC VOA functional test:


Below is an example of a healthy unit:


VOA current (mA) Power (dBm) TzGain TzAdcCountsDBfunc_OagcVoaFunctionalTest: 0.00 -2.41 0 34039DBfunc_OagcVoaFunctionalTest: 1.00 -2.92 0 30258DBfunc_OagcVoaFunctionalTest: 2.00 -3.53 0 26334DBfunc_OagcVoaFunctionalTest: 3.00 -4.15 0 22800DBfunc_OagcVoaFunctionalTest: 4.00 -4.87 0 19337DBfunc_OagcVoaFunctionalTest: 5.00 -5.68 0 16038DBfunc_OagcVoaFunctionalTest: 6.00 -6.54 0 13146

DBfunc_OagcVoaFunctionalTest: 7.00 -7.40 1 26405DBfunc_OagcVoaFunctionalTest: 8.00 -8.24 1 21783DBfunc_OagcVoaFunctionalTest: 9.00 -9.07 1 17999DBfunc_OagcVoaFunctionalTest: 10.00 -9.87 1 14974DBfunc_OagcVoaFunctionalTest: 11.00 -10.64 1 12527DBfunc_OagcVoaFunctionalTest: 12.00 -11.39 2 26870DBfunc_OagcVoaFunctionalTest: 13.00 -12.13 2 22640DBfunc_OagcVoaFunctionalTest: 14.00 -12.85 2 19222DBfunc_OagcVoaFunctionalTest: 15.00 -13.54 2 16377DBfunc_OagcVoaFunctionalTest: 16.00 -14.22 2 14011DBfunc_OagcVoaFunctionalTest: 17.00 -14.90 2 12007DBfunc_OagcVoaFunctionalTest: 18.00 -15.55 3 25877

DBfunc_OagcVoaFunctionalTest: 19.00 -16.19 3 22369DBfunc_OagcVoaFunctionalTest: 20.00 -16.82 3 19393DBfunc_OagcVoaFunctionalTest: 21.00 -17.45 3 16784DBfunc_OagcVoaFunctionalTest: 22.00 -18.05 3 14634DBfunc_OagcVoaFunctionalTest: 23.00 -18.65 3 12762DBfunc_OagcVoaFunctionalTest: 24.00 -19.24 3 11165DBfunc_OagcVoaFunctionalTest: 25.00 -19.83 3 9778DBfunc_OagcVoaFunctionalTest: 26.00 -20.40 3 8591DBfunc_OagcVoaFunctionalTest: 27.00 -20.96 3 7579


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DBfunc_OagcVoaFunctionalTest: 28.00 -21.52 3 6688DBfunc_OagcVoaFunctionalTest: 29.00 -22.07 3 5917DBfunc_OagcVoaFunctionalTest: 30.00 -22.60 3 5255DBfunc_OagcVoaFunctionalTest: 31.00 -23.13 3 4679DBfunc_OagcVoaFunctionalTest: 32.00 -23.64 3 4175DBfunc_OagcVoaFunctionalTest: 33.00 -24.17 3 3722DBfunc_OagcVoaFunctionalTest: 34.00 -24.68 3 3329DBfunc_OagcVoaFunctionalTest: 35.00 -25.18 3 2988DBfunc_OagcVoaFunctionalTest: 36.00 -25.69 3 2677DBfunc_OagcVoaFunctionalTest: 37.00 -26.18 3 2410DBfunc_OagcVoaFunctionalTest: 38.00 -26.66 3 2179DBfunc_OagcVoaFunctionalTest: 39.00 -27.13 3 1972

DBfunc_OagcVoaFunctionalTest: VOA loss at 0mA= 1.96 dBDBfunc_OagcVoaFunctionalTest: VOA loss at mid-range= 16.37 dB


VOA loss at 0mA is about 2 dB

VOA loss at mid-range (20 mA) is about 15 dB

As the VOA current increases, the post-VOA power and the TzAdcCounts decrease

As the VOA current increases, the post-VOA Tz gain increases

3.2. Example: post-VOA power/ADC readings are all lowIn the example below the post-VOA power at all VOA currents is very small and the Tzgain is railed to 3:

VOA current (mA) Power (dBm) TzGain TzAdcCountsDBfunc_OagcVoaFunctionalTest: 0.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 1.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 2.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 3.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 4.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 5.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 6.00 -27.13 3 1972DBfunc_OagcVoaFunctionalTest: 7.00 -27.13 3 1972

There is either an optical problem between Rx input and tap2, or there is a problem withthe tap2 Tz/ADC circuit.

1. First check the result of the Rx Signal Path Insertion Loss Test. If the Rx Signal PathInsertion Loss Test also failed, there is probably a splicing problem between the Rxinput and tap2. Focus attention on the optical path double check splices 1,2,3 etc.


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2. If the Rx Signal Path Insertion Loss Test passed, then the optical path from Rx inputthrough tap1, VOA and tap2 out to the mixer output should be ok. Focus attention onthe tap2 Tz/ADC circuit.

3. First verify that the tap2 electrical connection to the Tz input is ok: use themultimeter to do a continuity test between pin2 of tap2, and pin4 of U48. If there isno continuity, either the tap2 pins are not soldered into the board, or there is a breakin the PCB track.

4. If continuity is ok, power up the card and run the OCLD init script. After the scriptfinishes measure the voltage at pin1 of tap2; the voltage should be ~-3V. If not, thereis a problem somewhere between the source of the -3V supply and pin1 of tap2; focusattention there.

5. Probe the supply voltages at U48 and SW3 (post-VOA Tz and gain switch), and atU50 and U54 (mux and ADC). These supply voltages should be as expectedaccording to the circuit schematic [2]; if not focus attention on the supply circuits.

6. If the supplies are ok, inject 0 dBm of optical power into the UUT Rx port. Probe thesignal voltage through U48 and SW3 (post-VOA Tz and gain switch), and at U50 andU54 (mux and ADC). Pay special attention to any difference between the voltage atthe output of the Tz stage (U48 pin 1) and the voltage at the input to the mux (U50

pin 13).7. If all the supply and signal voltages are ok, replace tap2.

3.3. Example: post-VOA power/ADC readings are all high

In the example below the post-VOA power and Tz gain both seem reasonable at 0mAVOA current, but they dont decrease as the VOA current increases:

VOA current (mA) Power (dBm) TzGain TzAdcCountsDBfunc_OagcVoaFunctionalTest: 0.00 -2.41 0 34039DBfunc_OagcVoaFunctionalTest: 1.00 -2.41 0 34039DBfunc_OagcVoaFunctionalTest: 2.00 -2.41 0 34039DBfunc_OagcVoaFunctionalTest: 3.00 -2.41 0 34039DBfunc_OagcVoaFunctionalTest: 4.00 -2.41 0 34039

There is either a problem with the VOA current source circuit, or with the VOA itself.

Check to make sure the VOA leads are correctly soldered. Probe the voltage across the

VOA leads as the test runs. The voltage across the VOA should be roughly proportionalto the current through it; if the voltage doesnt change, theres a problem with the VOAcurrent source circuit. If the voltage does change, the current source circuit is probablyworking ok and the problem is probably with the VOA itself; replace the VOA.


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difference between the actual Rx input power and the power measured by the pre-VOA tap (tap1)

The post-VOA Power target is -15 dBm. This is used together with the prefunccal data in the EEPROM to calculate the Power target DAC , the Target

photocurrent , and the TV22 target . If any of these values are significantlydifferent (more than 10% different for example) than the healthy values above, itcould indicate a problem with the pre-func cal data retrieved from the EEPROM orProligent database.

The Controlled power 1 and 2 and corresponding Closed loop error showhow accurately the oAGC circuit is able to control the post-VOA power to the Powertarget . The Tracking error shows the difference between the Closed looperror for the two different input powers tested. All of the errors should be small,


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5. oAGC Post-VOA Tz Osci llation Test

Open the .log file and scroll to the very bottom to the latest log info. Scroll back up tofind the latest entry for the oAGC Post-VOA Tz Oscillation Test:

DBfunc_OagcPostVoaTzOscillationTest:


DBfunc_OagcPostVoaTzOscillationTest: Equipment init...checkLaserUutPower: checking Laser-UUT power:

measureUutInputPower: checking UUT input power:

measureUutInputPower: pre-VOA ADC reading: 285 lsb measureUutInputPower: Expected input power: -14.000 dBm measureUutInputPower: Measured input power: -14.130 dBm measureUutInputPower: Input power delta: -0.130 dB

...: Init complete.

...: Post-VOA Tz oscillation test:

...: VGA DAC Power (dBm) RIN (dB) VOA current (mA)

...: 1024 -21.266720 -107.121974 8.548646

...: 1224 -21.271098 -107.795804 8.649964

...: 1424 -21.219204 -108.323685 8.618948

...: 1624 -21.181583 -108.574792 8.581730

...: 1824 -21.170023 -108.727112 8.584831

...: 2024 -21.156691 -108.874572 8.581730

...: 2224 -21.153559 -109.837611 8.576560

...: 2424 -21.155440 -109.948265 8.583797

...: 2624 -21.149432 -110.495215 8.572425

...: 2824 -21.145737 -110.807580 8.567256

...: 3024 -21.145597 -110.592975 8.580696

...: 3224 -21.142054 -110.065129 8.558985

...: 3424 -21.138840 -109.770428 8.553816

...: 3624 -21.138280 -110.771825 8.554850

...: 3824 -21.136350 -112.168260 8.553816

...: 4024 -21.134121 -110.816331 8.561053

...: 4095 -21.133346 -111.012255 8.558985

...: Power delta (dB)= 0.137752

...: Max RIN (dB)= -107.121971

...: Power target= -21.00 dBm

...: Power target DAC= 2530 lsb

...: Target photocurrent= -7.15 dBuA

...: TV22 target= 0.24

...: Input power= -14.00 dBm


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...: Controlled power= -21.27 dBm

...: Closed loop error= 0.266668 dB

...: Tz= 7090

...: gain= 3

...: Shutting down...

...: oAGC post-VOA Tz oscillation test complete.


At the start of the test the Input power delta is measured. The result should besimilar to the result from the oAGC pre-VOA Sanity Test. This number is thedifference between the actual Rx input power and the power measured by the pre-VOA tap (tap1)

The post-VOA Power target is -21 dBm. This is used together with the prefunc

cal data in the EEPROM to calculate the Power target DAC , the Target photocurrent , and the TV22 target . If any of these values are significantly

different (more than 10% different for example) than the healthy values above, itcould indicate a problem with the pre-func cal data retrieved from the EEPROM orProligent database.

The Controlled power 1 and corresponding Closed loop error show howaccurately the oAGC circuit is able to control the post-VOA power to the Powertarget . The values above are good.

The Power delta (dB) and Max RIN (dB) are both within spec. If either ofthese is outside the spec the test will fail. The Max RIN (dB) indicates how noisythe post-VOA power readings are, and the Power delta (dB) indicates how wellthe oAGC circuit tracks to the Power target as a function of the loop bandwidth asset by the VGA DAC .

5.2. Example: power delta is ok but RIN is high for all VGA DAC

In the example below, the post-VOA power of ~-21.15 dBm is close to the target of -21dBm for all VGA DAC settings, but the RIN of ~-72 dB is consistently high for all VGADAC settings.

...: Equipment init...

...: Polarization controller...

...: VOA...

...: Laser...

...: oAGC init...

...: Init complete.

...: Post-VOA Tz oscillation test:

...: VGA DAC Power (dBm) RIN (dB) VOA current (mA)

...: 1024 -21.155687 -71.964142 9.759324

...: 1224 -21.163777 -72.050285 9.636309


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...: 1424 -21.131775 -72.607110 9.628039

...: 1624 -21.124729 -72.015395 9.495720

...: 1824 -21.120317 -73.656502 9.431627

...: 2024 -21.116092 -73.743813 9.403716

...: 2224 -21.115979 -72.964090 9.350995

...: 2424 -21.115358 -73.612421 9.338590

...: 2624 -21.116754 -73.066595 9.288971

...: 2824 -21.113251 -73.517768 9.276566

...: 3024 -21.123383 -72.588312 9.257958

...: 3224 -21.122795 -72.753822 9.306544

...: 3424 -21.111178 -73.290321 9.216609

...: 3624 -21.112896 -72.915676 9.198001

...: 3824 -21.113117 -72.446551 9.178360

...: 4024 -21.113235 -72.807736 9.216609

...: 4095 -21.117280 -72.290619 9.154584

...: Power delta (dB)= 0.052600

...: Max RIN (dB)= -71.964142

...: Power target= -21.00 dBm

...: Power target DAC= 2450 lsb

...: Target photocurrent= -6.96 dBuA

...: TV22 target= 0.20

...: Input power= -14.00 dBm

...: Controlled power= -21.15 dBm

...: Closed loop error= 0.151138 dB

...: Tz= 7504

...: gain= 3...: Shutting down...

...: oAGC post-VOA Tz oscillation test complete.

Notes from this failed unit:

The Power delta is small and the Closed loop error is small these look ok

The Max RIN is too high, and the RIN is consistently high for all VGA DAC

The Power target DAC , the Target photocurrent , and the TV22 target areall very close to the healthy values above, which indicates the correct pre-func caldata was retrieved from the EEPROM or Proligent database to use in calculations.

The only failure appears to be that the post-VOA power readings are too noisy.Everything else about the functionality of the oAGC circuit seems ok. In this case thecard should be referred to the PCB designer at Nortel to investigate the high noise.For this particular unit the PCB designer discovered that the log amp U42 had moreoutput noise than on healthy units. Upon replacing the log amp U42 the RIN improved to better than -100 dB.


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6. oAGC Dynamic Test

To be added when the test case is added.


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7. Rx Signal Path Insertion Loss Test

Open the .log file and scroll to the very bottom to the latest log info. Scroll back up tofind the latest entry for the Rx Signal Path Insertion Loss Test:

DBfunc_RxSignalPathLossTest: Rx Signal path loss:


DBfunc_RxSignalPathLossTest: Rx Signal path loss:DBfunc_RxSignalPathLossTest: Init complete.checkLaserUutPower: checking Laser-UUT power:

measureUutInputPower: checking UUT input power: measureUutInputPower: pre-VOA ADC reading: 7434 lsb measureUutInputPower: Expected input power: 0.000 dBm measureUutInputPower: Measured input power: -0.129 dBm measureUutInputPower: Input power delta: -0.129 dB

DBfunc_RxSignalPathLossTest: Measuring loss...DBfunc_RxSignalPathLossTest: Channel 1 . . . . . . . .DBfunc_RxSignalPathLossTest: Channel 2 . . . . . . . .DBfunc_RxSignalPathLossTest: Channel 3 . . . . . . . .DBfunc_RxSignalPathLossTest: Channel 4 . . . . . . . .DBfunc_RxSignalPathLossTest: Measurement complete.DBfunc_RxSignalPathLossTest: Min power channel 1= -22.74 dBmDBfunc_RxSignalPathLossTest: Max power channel 1= -9.77 dBmDBfunc_RxSignalPathLossTest: Insertion loss channel 1= 9.77 dBDBfunc_RxSignalPathLossTest: Min power channel 2= -38.66 dBmDBfunc_RxSignalPathLossTest: Max power channel 2= -9.80 dBmDBfunc_RxSignalPathLossTest: Insertion loss channel 2= 9.80 dBDBfunc_RxSignalPathLossTest: Min power channel 3= -22.58 dBmDBfunc_RxSignalPathLossTest: Max power channel 3= -9.80 dBmDBfunc_RxSignalPathLossTest: Insertion loss channel 3= 9.80 dBDBfunc_RxSignalPathLossTest: Min power channel 4= -20.96 dBmDBfunc_RxSignalPathLossTest: Max power channel 4= -9.78 dBmDBfunc_RxSignalPathLossTest: Insertion loss channel 4= 9.78 dBDBfunc_RxSignalPathLossTest: Shutting down...DBfunc_RxSignalPathLossTest: Done.DBfunc_RxSignalPathLossTest: measurement complete.




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The Insertion loss for all four channels is roughly equal (0.2 dB) The Max power is at least 10 dB higher than the Min power for each channel.

(During the test the power at the output of the coherent mixer is sampled continuouslyon the Power Sensor as the state of polarization at the UUT Rx input is scanned; the power varies between a Max and Min value because of the PDL of the polarization beam splitter in the Rx optical path)

General debugging ideas:

If three of the channels have good insertion loss but one of the four channels hasmuch higher insertion loss than the other three, try cleaning both sides of the Molexconnector for the failed channel and retesting. If the failure persists, try swapping the connections at the Molex connectors at the

coherent mixer output and retesting. Does the high insertion loss appear on adifferent channel now? If the high insertion loss appears on a different channel now, then the problem

is with the UUT (with that particular coherent mixer output fiber). Replacethe coherent mixer and retest.

If the high insertion loss stays on the same channel as before, then the problem is with the Molex-LC patchcord between the UUT and the PowerSensor. Clean or replace this patchcord, recalibrate the station as necessary,and retest.

If all four channels have high insertion loss, check the result of the Rx LO PathInsertion Loss test. Do all four channels fail in that test as well?

If all four channels also failed the Rx LO Path Loss Test, replace the coherentmixer (the only optical component common to the Signal and LO Path) and retest. If all four channels passed the Rx LO Path Insertion Loss Test, then the coherent

mixer is not the problem. Check the result of the oAGC tests. Did the oAGCtests pass? If the oAGC tests failed, the problem is somewhere between the UUT Rx

input and the Rx post-VOA tap (tap2). Focus debugging attention on thefailed oAGC tests.

If the oAGC tests passed, then the optical path up to the Rx post-VOA tap(tap2) must be ok. Inspect the splices around the Rx PMBC (PMBC1). Ifthey look ok, replace PMBC1 and retest. If the failure persists, replace tap2

and retest.


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8. Rx LO Path Insertion Loss Test


DBfunc_RxLOPathLossTest: Rx LO path loss:


DBfunc_RxLOPathLossTest: Rx LO path loss:DBfunc_RxLOPathLossTest: Equipment init...DBfunc_RxLOPathLossTest: Power meter...DBfunc_RxLOPathLossTest: Init complete.DBfunc_RxLOPathLossTest: Initialising ITLA laser...DBfunc_RxLOPathLossTest: Enabling ITLA laser...DBfunc_RxLOPathLossTest: Measuring loss...DBfunc_RxLOPathLossTest: Channel 1DBfunc_RxLOPathLossTest: Channel 2DBfunc_RxLOPathLossTest: Channel 3DBfunc_RxLOPathLossTest: Channel 4DBfunc_RxLOPathLossTest: Measurement complete.DBfunc_RxLOPathLossTest: Rx LO path loss measurement results:DBfunc_RxLOPathLossTest: Insertion loss channel 1= 21.93 dBDBfunc_RxLOPathLossTest: Insertion loss channel 2= 21.81 dBDBfunc_RxLOPathLossTest: Insertion loss channel 3= 21.46 dB

DBfunc_RxLOPathLossTest: Insertion loss channel 4= 21.57 dBDBfunc_RxLOPathLossTest: Shutting down...DBfunc_RxLOPathLossTest: Done.DBfunc_RxLOPathLossTest: measurement complete.



The Insertion loss for all four channels is roughly equal (0.2 dB)


If three of the channels have good insertion loss but one of the four channels hasmuch higher insertion loss than the other three, try cleaning both sides of the Molexconnector for the failed channel and retesting. (This particular channel also probablyfailed in the Rx Signal Path Insertion Loss Test).


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If the failure persists, try swapping the connections at the Molex connectors at thecoherent mixer output and retesting. Does the high insertion loss appear on adifferent channel now? If the high insertion loss appears on a different channel now, then the problem

is with the UUT (with that particular coherent mixer output fiber). Replacethe coherent mixer and retest.

If the high insertion loss stays on the same channel as before, then the problem is with the Molex-LC patchcord between the UUT and the PowerSensor. Clean or replace this patchcord, recalibrate the station as necessary,and retest.

If all four channels have high insertion loss, check the result of the Rx Signal PathInsertion Loss test. Do all four channels fail in that test as well? If all four channels also failed the Rx Signal Path Loss Test, replace the coherent

mixer (the only optical component common to the Signal and LO Path) and retest. If all four channels passed the Rx Signal Path Insertion Loss Test, then thecoherent mixer is not the problem. Check the result of the Tx Startup test. Didthe Tx Startup Test pass? If the Tx Startup Test passed, then the optical path from the output of the

ITLA laser through the 1090 PM splitter (PMTC1) to the 90% output going tothe PM5050 splitter (PMTC2) is must be ok. Suspect the splice between the10% output of PMTC1 and the input of the coherent mixer (splice 6). Redothis splice and retest. If the problem persists then replace PMTC1 and retest.

If the Tx Startup Test failed, then the problem is very likely common to both paths: the ITLA laser or the 1090 PM splitter (PMTC1). Check the result of

the Laser Comms Test as part of the Tx Startup Test Did the Laser CommsTest pass? If the Laser Comms Test failed then the ITLA laser is not properly

connected to the daughtercard. Inspect the connection and/or replace theITLA laser, and retest.

If the Laser Comms Test passed then the ITLA laser is properly connectedto the daughtercard and communications are working properly. Check theresult of the Bias2.Max Photo Test X and Y from the Tx Startup Test. If the Max Photo Tests failed, then no light got from the 90% output of

PMTC1 to the PM taps in the Tx path (taps 3,4). The problem is likelywith PMTC1 or the splice between the ITLA laser and the PMTC1

input (splice 16). First redo the splice 16 and retest. If the failure persists then replace PMTC1 and retest.

If the Max Photo Tests passed, then light got from the 90% output ofPMTC1 to the Tx portion of the optics. Therefore the problem cannot

be PMTC1 or the splice between the ITLA and PMTC1 (splice 16).Focus attention on the 10% output of PMTC1 and splice 6 leading tothe coherent mixer.


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9. Beat Efficiency Test


DBfunc_BeatEfficiencyTest: Beat efficiency test:


DBfunc_BeatEfficiencyTest: Beat efficiency test:DBfunc_BeatEfficiencyTest: Measuring dark noise:DBfunc_BeatEfficiencyTest: Enabling signal:

checkLaserUutPower: checking Laser-UUT power: measureUutInputPower: checking UUT input power: measureUutInputPower: pre-VOA ADC reading: 1617 lsb measureUutInputPower: Expected input power: -6.500 dBm measureUutInputPower: Measured input power: -6.745 dBm measureUutInputPower: Input power delta: -0.245 dB

DBfunc_BeatEfficiencyTest: Measuring X-pol signal power:DBfunc_BeatEfficiencyTest: Summary of beat efficiency results:DBfunc_BeatEfficiencyTest: dark mean= 0.000000 WDBfunc_BeatEfficiencyTest: dark ampl= 0.000117 WppDBfunc_BeatEfficiencyTest: X sig mean= 0.000015 WDBfunc_BeatEfficiencyTest: X sig ampl= 0.000118 WppDBfunc_BeatEfficiencyTest: X sig power= -15.917960 dBmDBfunc_BeatEfficiencyTest: X LO mean= 0.000212 WDBfunc_BeatEfficiencyTest: X LO ampl= 0.000117 WppDBfunc_BeatEfficiencyTest: X LO power= -6.338757 dBmDBfunc_BeatEfficiencyTest: X beat mean= 0.000225 WDBfunc_BeatEfficiencyTest: X beat ampl= 0.000361 WppDBfunc_BeatEfficiencyTest: X beat mod depth= 1.085531DBfunc_BeatEfficiencyTest: X beat power= -6.254851 dBmDBfunc_BeatEfficiencyTest: Y sig mean= 0.000011 WDBfunc_BeatEfficiencyTest: Y sig ampl= 0.000125 WppDBfunc_BeatEfficiencyTest: Y sig power= -16.210699 dBmDBfunc_BeatEfficiencyTest: Y LO mean= 0.000203 WDBfunc_BeatEfficiencyTest: Y LO ampl= 0.000115 WppDBfunc_BeatEfficiencyTest: Y LO power= -6.634492 dBmDBfunc_BeatEfficiencyTest: Y beat mean= 0.000212 WDBfunc_BeatEfficiencyTest: Y beat ampl= 0.000333 WppDBfunc_BeatEfficiencyTest: Y beat mod depth= 1.023476DBfunc_BeatEfficiencyTest: Y beat power= -6.221770 dBmDBfunc_BeatEfficiencyTest: Beat efficiency test complete.


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At the start of the test the Input power delta is measured. The result should be

similar to the result from the oAGC pre-VOA Sanity Test. This number is thedifference between the actual Rx input power and the power measured by the pre-VOA tap (tap1)

First examining the DCA dark characteristics: The dark mean is the average value of the DCA waveform when no light is

present at the DCA optical input. This value is about zero. The dark ampl is the peak-to-peak value of the DCA waveform when no light is

present at the DCA optical input. This value varies from DCA to DCA but should be significantly less than the value of X beat ampl or Y beat ampl .

Next examining the results for X (similarly for Y): The sig power and LO power are the signal and LO optical powers measured

on the Power Sensor with only the signal or LO present, respectively. The LO power should be about 10 dB greater than the sig power . If not, optical powers were not set or measured correctly during the measurement. Try retesting.

The sig mean and sig ampl are the mean and peak-to-peak values of the DCAwaveform when only the signal is present at the DCA optical input. The LO

mean and LO ampl are the mean and peak-to-peak values of the DCA waveformwhen only the LO is present at the DCA optical input. The LO ampl and sigampl are very close to the dark ampl . The LO mean is about 10 times greaterthan the sig mean .

The beat power is the optical power measured at the Power Sensor with both

signal and LO present. The beat power is about 10 dB greater than the sig power and slightly higher than the LO power ; this makes sense because with both signal and LO present the optical power is higher than with the LO alone.

The beat mean is the mean value of the DCA waveform when both signal andLO are present. The beat mean is about 10 times greater than the sig mean and slightly higher than the LO mean ; this makes sense because with both signaland LO present the optical power and hence the DCA waveform mean is a bithigher than with the LO alone.

The beat ampl is the peak-to-peak value of the DCA waveform measured with both the signal and LO present. This is a raw representation of how well thesignal and LO are mixed by the coherent mixer. The beat ampl should be twoto three times greater than the signal ampl and LO ampl .

The beat mod depth is a more accurate measure of how well the signal and LOare mixed by the coherent mixer. It is the modulation depth (peak-to-peakdivided by average) of the DCA beat waveform, corrected to remove the dark

mean and dark ampl of the DCA.



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1. Did all the oAGC tests, Rx Signal Path Loss tests pass? If any of these tests failed, focusattention on those failures first since that functionality is required for the Beat EfficiencyTest.

2. Did the Rx LO Path Loss Test pass? If not, focus attention on that failure first since thatfunctionality is required for the Beat Efficiency Test.

3. Did both X-pol and Y-pol fail beat efficiency? If so, first redo splices 4 and 5, and retest.If the failure persists, replace PMBC1 and retest.

4. If only one of X or Y-pol failed, first redo either splice 4 (X-pol) or splice 5 (Y-pol) andretest. If the failure persists, replace PMBC1 and retest.


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10. Tx Startup

10.1. Overview

The entire Tx Startup Test is run by the EOC firmware. The EOC firmware starts variousfirmware/hardware features one at a time and in a certain order. Tx EOC featuresinclude Laser, Bias loops, Crossing Control loops, IQ Power Balance loops, XY PowerBalance loops, and Tx VOA.

Some firmware/hardware features depend on the correct operation of others. For thisreason, when debugging Tx Startup failures it is very important to focus on the first TxSelf Test that failed. Other later failures may have occurred simply because they dependon the first failure.

In general it should be possible to debug most Tx Startup failures offline using the station.log file, EOC log file, Tx snapshot file, and UUT snapshot file.

In general start by looking at the Tx Self Test results in the Tx snapshot file. The Tx SelfTest results are listed in the order they are tested. Take note of the first failure and focusattention there. The following sections give debug advice about each of the Tx Self Testsin the order they are performed by the firmware.

In some cases it may be necessary to debug the card while its powered up on the station.A procedure for this is given in Section 10.21.


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10.2. -21V Test etc

For failure of any of the following Tx Self Tests:Tx Seq.-21V TestTx Seq.-12V TestTx Seq.-5.2V TestTx Seq.+3.3VPup1 TestTx Seq.+5.4V TestTx Seq.+9V TestTx Seq.+13V TestTx Seq.+21V Test

These tests are run when the EOC firmware starts up, before a wavelength is provisioned.

These tests are described in Section 2.0 of reference [1].

Failure of any of these tests indicates a power supply problem.

Start debugging by powering up the card and running the FW init script. After the scriptfinishes probe the voltages at the source of each of the failed supplies on the captivemotherboard. Work towards the termination of the failed supplies on the daughtercard,until the failure is found.


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10.3. Laser Comms Test

For failure of any of the following Tx Self Tests:Tx Seq.Laser Comms Test



Failure of the Laser Comms Test indicates a communications problem with the ITLAlaser module.

Start debugging by checking that the ITLA ribbon cable is installed in the correctorientation.

If the ribbon cable is correctly installed, power up the card and run the FW init script.After the script finishes, probe the voltages on both sides of the captive motherboard-daughtercard interface (J15) and the daughtercard-ITLA interface (J14) to make sure thesupply voltages are correct. Use the circuit schematic [2] to know what voltages toexpect for each pin.

If any of the supply voltages are incorrect, work your way back through the power supplycircuitry towards the daughtercard and then the motherboard to find where the supplyvoltage is incorrect.

If the supply voltages are ok, there may be a problem with the mother-daughter laserconnector header (J15) or the ITLA ribbon cable (J14). Power off the card and carefullyinspect the header at J15 and the ribbon cable at J14 for damaged or missing pins. Tryreplacing the header and the ribbon cable and retesting.

If the test still fails there may be a problem with the ITLA laser module itself. Tryreplacing the ITLA laser module and retesting.


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10.4. Drv Self Test

For failure of any of the following Tx Self Tests:Tx IQ Pwr Bal.Drv Self Test[XI]Tx IQ Pwr Bal.Drv Self Test[XQ]Tx IQ Pwr Bal.Drv Self Test[YI]Tx IQ Pwr Bal.Drv Self Test[YQ]



Failure of any this indicates a problem with the driver and/or its support circuitry.

10.4.1. Initi al checksDo a resistance check on the driver and do a visual inspection for damage to the driversupport circuitry. If the resistance check fails, remove the optics, replace the faileddriver, and retest at prefunc.

If the resistance check passes, the problem could be due to: the driver itself; the drivercurrent sense circuitry; the driver support circuitry calibration data.

Try several consecutive Tx Startups either manually or with the test software. Does thesame driver consistently fail, or is there any intermittency?

10.4.2. Example: same driver always failsIn the three examples below the same driver always fails with result 2.

Tx IQ Pwr Bal.Drv Self Test[XI] (0x00001C89) = 2Tx IQ Pwr Bal.Drv Self Test[XQ] (0x00001C8A) = 1Tx IQ Pwr Bal.Drv Self Test[YI] (0x00001C8B) = 1Tx IQ Pwr Bal.Drv Self Test[YQ] (0x00001C8C) = 1



If the same driver consistently fails, while the others consistently pass, suspect a problemwith that particular driver and/or its support circuitry.


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Open the UUT snapshot file and look at the following variables used for the Drv SelfTest:

Tx IQ Pwr Bal.Zero Gain Id (A)[0][0] (0x00001C8D) = 0.000407Tx IQ Pwr Bal.Zero Gain Id (A)[0][1] (0x00011C8D) = 0.002035Tx IQ Pwr Bal.Zero Gain Id (A)[0][2] (0x00021C8D) = 0.000814Tx IQ Pwr Bal.Zero Gain Id (A)[0][3] (0x00031C8D) = 0.001357Tx IQ Pwr Bal.Low Gain Id (A)[0][0] (0x00001C8E) = 0.016276Tx IQ Pwr Bal.Low Gain Id (A)[0][1] (0x00011C8E) = 0.017293Tx IQ Pwr Bal.Low Gain Id (A)[0][2] (0x00021C8E) = 0.015666Tx IQ Pwr Bal.Low Gain Id (A)[0][3] (0x00031C8E) = 0.015934Tx IQ Pwr Bal.Vc ON Volts (V)[0][0] (0x00001C8F) = 0.6Tx IQ Pwr Bal.Vc ON Volts (V)[0][1] (0x00011C8F) = 0.5Tx IQ Pwr Bal.Vc ON Volts (V)[0][2] (0x00021C8F) = 0.6Tx IQ Pwr Bal.Vc ON Volts (V)[0][3] (0x00031C8F) = 0.5

Tx IQ Pwr Bal.Vg ON Volts (V)[0][0] (0x00001C90) = -0.425Tx IQ Pwr Bal.Vg ON Volts (V)[0][1] (0x00011C90) = -0.425Tx IQ Pwr Bal.Vg ON Volts (V)[0][2] (0x00021C90) = -0.425Tx IQ Pwr Bal.Vg ON Volts (V)[0][3] (0x00031C90) = -0.425

Typical values are shown in the table above.

Sanity check the prefunc cal data for the driver Vg and Vc slopes and offsets: in MCEmon read the EEPROM (E 1 2 9) and look at the prefunc cal data forastDriverVgSlopeOffset and astDriverVctrlSlopeOffset. Compare theseto the prefunc test specs as a sanity check.

If these calibration values do not meet the prefunc test specs, the Drv Self Test will not pass. Get the correct calibration data into the EEPROM before retesting.

If these calibration values meet the prefunc test steps, the problem is either with thedriver itself or with the current sense circuitry.

If the Zero Gain Id and/or Low Gain Id values are reasonable but the corresponding Vcand/or Vg ON Volts values are much higher than the typical values above, the driver is

probably dying. Remove the optics, replace the driver, and retest at prefunc.

If the Zero Gain Id and/or Low Gain Id values are much higher than the expected valuesabove, or are negative, suspect a problem with the driver current sense circuitry. Go tothe Section 10.4.3 to investigate the driver current sense circuitry.

10.4.3. Example: intermit tent driver failuresIn the example below, there is some intermittency in the driver self test results.



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If the driver self test results are inconsistent or intermittent, the problem is more likelywith the common driver current sense circuitry including the common ADC.

Start the Tx using the manual Tx startup procedure, and probe the voltages around U75,the ADC that is common to the driver current sense circuitry. Make sure the voltagereferences are stable. Work your way back to the supply voltages to the current sensecircuitry for each of the intermittently failing drivers. Compare the voltages measuredaround U75 to those measured on a known good unit.


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10.5. PIN DC ADC Test

For failure of any of the following Tx Self Tests:Bias 2.PIN DC ADC Test XBias 2.PIN DC ADC Test Y



Failure of either of these tests indicates a problem with either:

ADC slope/offset calibration data from EEPROM for the DC ADC for tap3/4; Calibration data from the EEPROM for the DC offset DAC for tap3/4; A circuit problem between tap3/4 and the DC path from the Tz through the mux to

the DC ADC; Or, high dark current from the inner tap (tap3/4).

10.5.1. Initi al sanity checksFirst double check the value of the offset DAC slope and offset in the EEPROM: useMCE mon to read the EEPROM contents (E 1 2 9) and look in the prefunc cal datasection at the values of fXpolOffsetDacVoltage or fYpolOffsetDacVoltage.Compare these values to the prefunc specs to make sure they are ok.

Next use the multimeter to do a continuity test between pin2 of tap4 and pin4 of U41 (forX-pol); or between pin2 of tap3 and pin4 of U45 (for Y-pol). If the continuity test is ok,

power up the card and running the FW init script. After the script finishes, probe thevoltages at each pin of the DC-path circuitry between the tap itself and the ADC. For X-

pol, check U41, U34, U35; for Y-pol check U45, U39, U35.

10.5.2. Example: vol tages measured on a good unitFor example, for X-pol:

U41 pins 1-5: 38.3mV; -2.96V; 38.1mV; 38.3mV; 23.5V. These make sense: pins 2 and5 are the supplies; pins 1,3,4 are the inputs/output of the op-amp and should all beroughly equal to one another.

U34 pins 1-8: 38.3mV; floating; 1.8mV; 23.6V; 5.1V; 3.4V; 1.8mV; 38.3mV. Thesemake sense: pin 2 is floating; pins 4,5,6 are supplies; pins 1,8 are the input/output signalvoltage and should all be roughly equal to one another; pin3,7 are GND.U35 pins 1-8: 12.3mV; 14.7mV; 14.6mV; -3.1V; 14.7mV; 14.9mV; 12.5mV; 5.1V.These make sense: pins 4,8 are the supplies; pins 5,6,7 are the X-pol inputs/output of theop-amp and should all be roughly equal to one another.

Next probe the supplies and the appropriate signal input pin to the mux (U50), and probethe supplies to the ADC (U54). The supply voltages should be as per the circuit


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schematic [2], and the signal at the appropriate input pin of the mux should be the sameas the voltage at the output of U35 and should be stable in time.

10.5.3. Example: Unstable signal input at mux (U50)The signal at the input to the mux (U50) should be stable in time. If this signal fluctuatessignificantly in time (ie more than 20% fluctuations), remove optics and replace U50.

10.5.4. Example: High voltage at fir st stage Tz inputFor example for X-pol: the voltage at U41 pin 4 represents the dark current coming fromtap3. If all other voltages to the first stage Tz op-amp are ok, but the voltage at U41 pin 4is hundreds of mV or higher, the dark current of tap3 is too high and tap3 should bereplaced. This can be confirmed by comparing the voltages of pins 1,3,4 of U41. Pin 3should be about 30mV, from the offset DAC. If pin 4 is hundreds of mV or higher, pin 1

will also be hundreds of mV or higher, again indicating high dark current from the tap.


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10.6. PIN AC ADC Test

For failure of any of the following Tx Self Tests:Bias 2.PIN AC ADC Test XBias 2.PIN AC ADC Test Y



Failure of either of these tests indicates a circuit problem between the first stage Tz op-amp for tap3/4 and the AC ADC.

10.6.1. Initi al sanity checksPower up the card and run the FW init script. After the script finishes, probe the voltagesat each pin of the AC-path circuitry between the tap itself and the ADC.

For example for X-pol, check U41, U34, U37, U44 and supporting circuitry.

10.6.2. Example voltages measured on a good uni tTo be added


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10.7. PIN DC ADC Out Test

For failure of any of the following Tx Self Tests:Tx Voa.PIN DC ADC Out Test

This test is run when the EOC firmware starts up, before a wavelength is provisioned.

This test is described in Section 13.0 of reference [1].

Failure of either of this test indicates a problem with either:

ADC slope/offset calibration data from EEPROM for the DC ADC for tap5; Calibration data from EEPROM for the DC offset DAC for tap5; A circuit problem between tap5 and the DC path from the Tz through the mux to the

DC ADC; Or, high dark current from tap5.

10.7.1. Initi al sanity checksFirst double check the value of the offset DAC slope and offset in the EEPROM: useMCE mon to read the EEPROM contents (E 1 2 9) and look in the prefunc cal datasection at the value of fOutputOffsetDacVoltage. Compare this value to the

prefunc specs to make sure they are ok.

Next use the multimeter to do a continuity test between pin2 of tap5 and pin4 of U36. Ifthe continuity test is ok, power up the card and running the FW init script. After the

script finishes, probe the voltages at each pin of the circuitry between the tap itself andthe ADC: U36, U33, U32, U50, U54.

10.7.2. Example voltages measured on a good uni tTo be added

10.7.3. Example: High voltage at fir st stage Tz inputThe voltage at U36 pin 4 represents the dark current coming from tap5. If the voltage atU36 pin 4 is hundreds of mV or higher, the dark current of tap5 is too high and tap5should be replaced. This can be confirmed by comparing the voltages of pins 1,3,4 ofU36. Pin 3 should be about TBD mV, from the offset DAC. If pin 4 is hundreds of mV

or higher, pin 1 will also be hundreds of mV or higher, again indicating high dark currentfrom the tap.


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10.8. Laser Tuning Test

For failure of any of the following Tx Self Tests:Tx Seq.Laser Tuning Test

These tests are run when the EOC firmware starts up, after a wavelength is provisioned.


Failure of the Laser Tuning Test indicates a problem with the ITLA laser module itself.

Power up the card and run the FW init script. Go to the MCE mon window for LaserVariables and look at the Fatal Status and Warning Status indicators. If either of thoseare not zero or are toggling, replace the ITLA laser module.

Contact the Nortel design team immediately because this is a serious laser failure.


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10.9. MaxMaxMax Test; Max Photo Test

For failure of any of the following Tx Self Tests:Bias 2.MaxMaxMax Test XBias 2.MaxMaxMax Test YBias 2.Max Photo Test XBias 2.Max Photo Test Y

These tests are run after a wavelength is provisioned.

These tests are described in Sections 6.1 and 6.2 respectively in reference [1].

Failure of the MaxMaxMax Test indicates a problem with either:

Zephyr dither generation (captive Motherboard); MDAC circuitry; DC bias DAC circuitry; DPMZ bias pin continuity to the Daughterboard PCB; DPMZ output to tap3/4 optical path; Tap3/4 AC path Tz/ADC; Or, DPMZ Vpi EDT data from EEPROM.

The Max Photo Test depends on the MaxMaxMax Test result, as well as correct tap3/4EDT data from EEPROM.

First ensure that the DPMZ pins are soldered correctly to the PCB. Use a multimeter todo a continuity test between the insertion of each DPMZ pin into the DPMZ module, andits termination at the Daughtercard circuitry, for example U11 and U12 for X-pol.Carefully inspect the DPMZ pads on the PCB for damage.

Next sanity-check the EEPROM EDT data for DPMZ and tap3/4: in MCE mon inspectthe EEPROM contents (E 1 2 9) and make sure this EDT data was correctly programmed.

If these initial sanity-checks are ok, go to Section 10.10 to debug the DC sweep data.


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10.10. MZ1/2/3 DAC Test; Optic Path Test

For failure of any of the following Tx Self Tests:Bias 2.MZ1 DAC Test XBias 2.MZ2 DAC Test XBias 2.MZ1 DAC Test YBias 2.MZ2 DAC Test YBias 2.MZ3 DAC Test XBias 2.MZ3 DAC Test YBias 2.Optic Path Test XBias 2.Optic Path Test Y


These tests are described in Sections 7.2, 7.3 and 7.6 in reference [1].

These tests depend on the functionality tested by the MaxMaxMax Test and the MaxPhoto Test, as well as correct functioning of the 200 and 250 kHz bias dithers from theZephyr and the AC path from the tap3/4 Tz to the AC ADC.

Check the min and max value of the light detected at tap3 and 4 from the DC bias sweepsusing the UUT snapshot file. The example below shows a typical result:

Bias.Avg Adc Min X (0x0000111B) = 2Bias.Avg Adc Min Y (0x0000111C) = 0Bias.Avg Adc Max X (0x0000111D) = 5618Bias.Avg Adc Max Y (0x0000111E) = 6109

These values were captured by the DC path Tz/mux/ADC for the inner taps (tap3/4). Themax values should be around 5000-7000, and the min values should be around 0.

If both X-pol and Y-pol failed, and the Min values are greater than the Max values,suspect splices 13,15 are swapped, or tap3/4 are in the wrong holes on the PCB.

If only X-pol failed and Y-pol passed (or vice versa), the mux and ADC are probablyworking ok. Suspect a problem either with the optical path from the DPMZ output to theinner tap, or with the inner tap Tz/ADC circuitry.

If both max and min are close to zero, look at the result of the MDAC tests for the failed polarization. If they passed, the problem is probably in the circuitry between the outputof the first Tz stage (U45 pin1 for X-pol for example) and the DC path through to themux. If the MDAC tests failed, the problem is probably common to both the AC and DC

paths, so focus on the optical-electrical path from the DPMZ output to the first stage Tz(U45 for X-pol for example). It is probably worth powering up the card and running theinit scripts, then measuring the voltages around the first stage Tz, especially the supplies.


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10.11. MZ1/2/3 AC Sweep Test; MZ1/2/3 MDAC Test

For failure of any of the following Tx Self Tests:Bias 2.MZ1 AC Sweep Test XBias 2.MZ2 AC Sweep Test XBias 2.MZ3 AC Sweep Test XBias 2.MZ1 AC Sweep Test YBias 2.MZ2 AC Sweep Test YBias 2.MZ3 AC Sweep Test YBias 2.MZ1 MDAC Test XBias 2.MZ2 MDAC Test XBias 2.MZ3 MDAC Test XBias 2.MZ1 MDAC Test YBias 2.MZ2 MDAC Test Y

Bias 2.MZ3 MDAC Test Y


These tests are described in Section 7.4 and 7.5 of reference [1].

The MDAC Test results are calculated by applying logic to the AC Sweep Test results.

Its possible to fail some of the AC Sweep tests and still pass all MDAC tests, in whichcase the likely point of failure is in the AC path of the tap3/4 Tz/ADC circuitry.

However, if any of the MDAC tests fail, focus attention on the MDAC circuitry and theconnection to the DPMZ bias pin.

Open the UUT snapshot file and plot the AC sweep data for the failed polarization(Bias.Avg Sweep 1X[0][0] to Bias.Avg Sweep 1X[0][44], similarly for 2X, and Bias.Sweep 3X[0][0]to Bias.Sweep 3X[0][44]) . An example of a typical result is shown below:

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 10 20 30 40 50

Series1

Series2

Series3


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10.12. Tz Test

For failure of any of the following Tx Self Tests:Bias 2.Tz Test XBias 2.Tz Test Y



Failure of this test indicates a problem with either the prefunc cal data from EEPROM forthe inner tap ADC slopes; or, the Tz gain switch and supporting circuitry.

Start by using MCE mon to sanity-check the prefunc cal data from EEPROM (E 1 2 9)

for the inner tap ADC slopes for each gain setting. Next, power up the card and run the FW init script. Probe the voltages around the Tzgain switch (U34 for X-pol or U39 for Y-pol). If no fault is found, use the prefunc debugtool to examine the Tz and gain switch circuitry.


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10.13. SecHarmShif t Test, Ref Shift Test, Phase Err Test

For failure of any of the following Tx Self Tests:Bias.SecHarmShift Test XBias.SecHarmShift Test YBias.Ref Shift Test XBias.Ref Shift Test YBias.Phase Err Test XBias.Phase Err Test Y



If the Phase Err Test fails examine the Phase Error results from the UUT snapshot file:Bias.Phase Err 1X (0x0000116F) = -0.03389Bias.Phase Err 2X (0x00001170) = -0.033023Bias.Phase Err 3X (0x00001171) = -0.002006Bias.Phase Err 1Y (0x00001172) = -0.018419Bias.Phase Err 2Y (0x00001173) = -0.022235Bias.Phase Err 3Y (0x00001174) = -0.009297

Convert the phase err values from radians to degrees (multiply by 180 and divide by ).If any of the phase err values are around 20 , replace the MDAC chip for that failedchannel.

If the Phase Err Test passes but the other tests fail, check the circuitry around theMDACs and the inner tap Tz and AC path ADCs for physical damage. If no fault isfound, use the prefunc debug tool to examine these circuits.


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10.14. 25KHz Gen Test

For failure of any of the following Tx Self Tests:Bias.25KHz Gen Test XBias.25KHz Gen Test Y



Failure of this test indicates a problem with the MDAC chip or its supporting circuitry.Inspect the MDAC chip and supporting circuitry for physical damage or missingcomponents. If no fault is found, use the prefunc debug tool to examine these circuits.


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10.15. Extinct Rat Test

For failure of any of the following Tx Self Tests:Bias 2.Extinct Rat Test XBias 2.Extinct Rat Test Y



Failure of either of these tests, with all previous Tx Self Tests passing, indicates a problem with the DPMZ extinction ratio, or with the DC path of the inner tapTz/mux/ADC.


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10.16. Trew Test

For failure of any of the following Tx Self Tests:Tx Seq.Trew Test

This test is run after a wavelength is provisioned.

This test is described in Section 14 of reference [1].

Failure of this test indicates a problem with the captive Motherboards TREW ASIC.


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10.17. Driver Tests: Vg Lo Drv Test/Vg Hi Drv Test; Vc Lo DrvTest/Vc Hi Drv Test; El Eff Lo Test/El Eff Hi Test; Eff Rat Lo Test/EffRat Hi Test

For failure of any of the following Tx Self Tests:

Tx Seq.Vg Lo Drv Test XITx Seq.Vg Lo Drv Test XQTx Seq.Vg Lo Drv Test YITx Seq.Vg Lo Drv Test YQTx Seq.Vg Hi Drv Test XITx Seq.Vg Hi Drv Test XQTx Seq.Vg Hi Drv Test YITx Seq.Vg Hi Drv Test YQ

Tx Seq.Vc Lo Drv Test XITx Seq.Vc Lo Drv Test XQTx Seq.Vc Lo Drv Test YITx Seq.Vc Lo Drv Test YQTx Seq.Vc Hi Drv Test XITx Seq.Vc Hi Drv Test XQTx Seq.Vc Hi Drv Test YITx Seq.Vc Hi Drv Test YQTx Seq.El Eff Lo Test XITx Seq.El Eff Lo Test XQTx Seq.El Eff Lo Test YITx Seq.El Eff Lo Test YQ

Tx Seq.El Eff Hi Test XITx Seq.El Eff Hi Test XQTx Seq.El Eff Hi Test YITx Seq.El Eff Hi Test YQTx Seq.Eff Rat Lo Test XITx Seq.Eff Rat Lo Test XQTx Seq.Eff Rat Lo Test YITx Seq.Eff Rat Lo Test YQTx Seq.Eff Rat Hi Test XITx Seq.Eff Rat Hi Test XQTx Seq.Eff Rat Hi Test YITx Seq.Eff Rat Hi Test YQ



Failure of any of these tests indicates a problem in the RF path somewhere between theRF driver on the Daughtercard and the pk-pk/crossing ADC circuit for the RF peakdetectors.


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Chances are that if one of these tests fail for a given channel, several others will fail for agiven channel.

If the EOC log file has Electrical Efficiency Delta alarms, the RF driver for that channelis almost certainly dead and should be replaced. Remove optics, replace the driver, andretest at prefunc.

If there are no Electrical Efficiency Delta alarms in the EOC log file, it may be moredifficult to pinpoint the failure between the RF driver and the RF pk-pk/crossing ADCcircuitry.

Start debug by examining the RF driver-related data from the UUT snapshot file.

10.17.1. Example: driver electrical efficiency is bad, with no ADC clippingThe Tx snapshot file showed the following failures:

Tx Seq.Vc Hi Drv Test XI 2Tx Seq.El Eff Hi Test XI 2Tx Seq.Eff Rat Hi Test XI 2Tx Seq.ModLoss HiDrvTest X 2

The first failure is the Vc Hi Drv Test XI.

Start by looking at driver Vc DAC and Vc values from the UUT snapshot file:

Tx IQ Pwr Bal.Vc DAC [XI] 20403Tx IQ Pwr Bal.Vc DAC [XQ] 29009Tx IQ Pwr Bal.Vc DAC [YI] 30361

Tx IQ Pwr Bal.Vc DAC [YQ] 31040Tx IQ Pwr Bal.Vc [XI] 0.900387Tx IQ Pwr Bal.Vc [XQ] 0.379534Tx IQ Pwr Bal.Vc [YI] 0.1747Tx IQ Pwr Bal.Vc [YQ] 0.172934

The XI driver is working much harder than the others, evidenced by its much higher Vcvalue higher and much lower DAC setpoint relative to the other channels.

Next look at the RF peak detector Vpp readings:

Tx XY Bal.Vpp [XI] 9.391179

Tx XY Bal.Vpp [XQ] 9.478941Tx XY Bal.Vpp [YI] 8.258041Tx XY Bal.Vpp [YQ] 8.400044

These dont seem too bad, the XI channel is generating a reasonable Vpp, but its takingmuch more Vc to achieve it.

Next look at the ADC clipping indicators to make sure the ADC is not clipped:


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Tx XY Bal.Adc Clip XI 0Tx XY Bal.Adc Clip XQ 0Tx XY Bal.Adc Clip YI 0Tx XY Bal.Adc Clip YQ 0

The ADC is not clipped.

Next look at the electrical efficiency (roughly equal to the ratio of driver Vc to RF peakdetector Vpp):

Tx XY Bal.Electrical Effic XI 1.066426Tx XY Bal.Electrical Effic XQ 7.514203Tx XY Bal.Electrical Effic YI 7.625786Tx XY Bal.Electrical Effic YQ 8.171809

The electrical efficiency for the XI driver is much smaller than it should be. The XIdriver is effectively dead. It takes too much Vc to generate an acceptable Vpp. Replacethe XI driver.

10.17.2. Example: driver electrical efficiency is bad, but has ADC clippingThe Tx snapshot file showed the following failures:

Tx Seq.Vc Hi Drv Test XI 2Tx Seq.El Eff Hi Test XI 2Tx Seq.Eff Rat Hi Test XI 2Tx Seq.ModLoss HiDrvTest X 2

The first failure is the Vc Hi Drv Test XI.

Start by looking at driver Vc DAC and Vc values from the UUT snapshot file:

Tx IQ Pwr Bal.Vc DAC [XI] 20403Tx IQ Pwr Bal.Vc DAC [XQ] 29009Tx IQ Pwr Bal.Vc DAC [YI] 30361Tx IQ Pwr Bal.Vc DAC [YQ] 31040Tx IQ Pwr Bal.Vc [XI] 0.900387Tx IQ Pwr Bal.Vc [XQ] 0.379534Tx IQ Pwr Bal.Vc [YI] 0.1747Tx IQ Pwr Bal.Vc [YQ] 0.172934

The XI driver is working much harder than the others, evidenced by its much higher Vcvalue higher and much lower DAC setpoint relative to the other channels.

Next look at the RF peak detector Vpp readings:


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Tx XY Bal.Vpp [XI] 9.391179Tx XY Bal.Vpp [XQ] 9.478941Tx XY Bal.Vpp [YI] 8.258041Tx XY Bal.Vpp [YQ] 8.400044

These dont seem too bad, the XI channel is generating a reasonable Vpp, but its takingmuch more Vc to achieve it.

Next look at the ADC clipping indicators to make sure the ADC is not clipped:

Tx XY Bal.Adc Clip XI 1Tx XY Bal.Adc Clip XQ 0Tx XY Bal.Adc Clip YI 0Tx XY Bal.Adc Clip YQ 0

The XI ADC is clipped (sometimes the ADC reading was greater than or equal to themax, which it should never be by design).

The XI driver may not be faulty in this case. Remove the optics and retest at prefunctional test.

10.17.3. Example: Manual driver debug onl ineIn some cases a card without optics can pass prefunctional test, but fail with optics. Tonarrow in on the problem it may be necessary to manually debug the card with opticswhile its powered up on a bench.

1. Start by following the manual Tx Startup procedure in Section 10.21.

2. After the Tx starts up, and reaches Tx Init Fail, go to the Tx Loop Closure andStability menu (E 2 2 1). Go to the last page and work backwards, opening the Txloops until you have opened all loops after, and including, the crossing controlloops.

3. Check the health of a driver by adjusting Vc and checking the current drawn andthe Vpp created: in the IQ power balance menu (E 2 8 1) adjust a DC Vc value tosomething between -1.5 Volts and +1 Volts. Monitor the corresponding Vppreadings in that menu, and monitor the driver current sense reading in the ADC

values menu (E 1 3 6 1). As Vc increases, the Vpp should increase, and thecurrent drawn (represented by the ADC reading) should also increase.

4. Meanwhile, probe the +8.5V supply voltage, the driver overcurrent shutdownlogic, and the actual Vc being applied to the driver, using the schematic to knowwhich points to probe. If the driver overcurrent logic goes from 3.3V (driverenabled) to 0V (driver shutdown) then the +8.5V supply to the driver will be shutoff. This indicates a problem with the driver itself; its drawing too much currentfor a given Vc.


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10.18. ModLoss LoDrv Test/ ModLoss HiDrv Test

For failure of any of the following Tx Self Tests:Tx Seq.ModLoss LoDrvTest XTx Seq.ModLoss LoDrvTest YTx Seq.ModLoss HiDrvTest XTx Seq.ModLoss HiDrvTest Y



First check if the ITLA laser is behaving ok: follow the manual Tx startup procedure andgo to the MCE mon laser variables menu to look at the Fatal Status or Warning Statusindicators. If these are both zero and the statuses are not toggling, assume the ITLA laseris ok.

Redo the splices around the inner taps: 12/13 for Y-pol or 14/15 for X-pol. Redo thesplices for the failed channel and retest.

If the failure persists, replace PMBC2 and retest.

If the failure persists, remove the DPMZ for the failed polarization and examine the GPO bullets and connectors carefully for physical damage or foreign material. Clean/replacethe GPO bullets as necessary and retest.

If the failure persists, replace the DPMZ for the failed polarization and retest.


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10.19. Opt Dith Out Test

For failure of any of the following Tx Self Tests:Tx XY Bal.Opt Dith Out Test XTx XY Bal.Opt Dith Out Test Y



Failure of this test is most likely due to a PER problem between the inner taps (tap3/4)and the outer tap (tap5). Start by redoing the PM splices between the failed polarizationsinner tap and PMBC2. If the failure persists then redo the splice between PMBC2 andtap5. If the failure persists replace the PMBC2.


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10.20. Power Margin Test

For failure of the following Tx Self Test:Tx Voa.Power Margin Test

This test is run after a wavelength is provisioned.

This test is described in Section 17.0 of reference [1].

Redo splice 10 and retest. If the failure persists redo splice 11 and retest. If the failure persists replace tap5 and retest.


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10.21. Manual Tx Debug Instructions

10.21.1. Firmware applicabil ityThe following procedure works with 5.30 "CO" TCS / 02_27 EOC loads.

10.21.2. Starting the Tx manually

To start the Tx:

1. Power up the card2. Open serial port communication tool3. After TCS boots and loads FPGAs, run the FW init script:


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10.21.3. Dump EOC InfoAfter the Tx is provisioned, it is helpful to capture all EOC info and alarms. This makes

manual debugging easier.In the program you use to see MCE Mon (PuTTY, for example), start a log file so thatany output to the window will be logged to a file. Many lines of data will be sent fromthe card to the MCE Mon window, so you