44Linking the Components

Linking The ComponentsLinking The ComponentsA computer is a system with data and

instructions flowing between its components in response to processor commands.

In order to work, these components must be physically linked.

Linking the ComponentsLinking the ComponentsThe BusThe Bus

Internal components are:– linked by a bus

A ribbon-like set of parallel wires that can carry several bits at a time in parallel.

– Power

– Instructions

– Data

– Addresses

– Commands

Linking the ComponentsLinking the ComponentsThe BusThe Bus

Types of Bus– Processor Bus

Delivers information to and from the processor– Memory Bus

Carries information between memory and the processor.

– High-Speed I/O BusLinks high-speed peripherals to the system.

– Standard I/O BusLinks slower devices to the system.A ribbon-like

set of parallel wires that can carry several bits at a time in parallel.

Linking the ComponentsLinking the ComponentsWord SizeWord Size

Internal components are:– Designed around a common word size– Word size affects:

Processing Speed– 32-bit bus contains 32 parallel lines that can carry 32

bits at a time.

– 16-bit bus contains 16 parallel lines that can carry 16 bits at a time.

– The bigger the word size, the faster the computer.

Linking the ComponentsLinking the ComponentsWord SizeWord Size

Internal components are designed around a common word size:– Word size affects:

Memory Capacity

– 32 bit address – 4 billion memory locations

– 16 bit address – 64,000 memory locations

– The bigger the word size – the more memory a computer can address.

Linking the ComponentsLinking the ComponentsWord SizeWord Size

Internal components are designed around a common word size:– Word size affects:

Precision– The number of significant digits a machine can

address– Registers hold one word.

• The processors internal circuitry is usually more efficient when manipulating numbers one word in length.

• A 32 bit mainframe adds 32-bit numbers• A 16 bit machine adds 16-bit numbers

– The bigger the word size, the more precise.

Linking the ComponentsLinking the ComponentsWord SizeWord Size

Internal components are designed around a common word size:– Word size affects:

Instruction set size

– Instructions move from memory to the processor over a bus.

– A 32 bit bus can carry a bigger instruction than a 16 bit bus.

– The bigger instruction size means more bits are available for operation code.

Linking the ComponentsLinking the ComponentsWord SizeWord Size

Internal components are designed around a common word size:– Word size affects:

Cost– A bigger word size means:

• a faster, more precise machine with greater memory capacity,

• a larger, more varied instruction set,

• a higher price tag.

Linking the ComponentsLinking the ComponentsMachine CyclesMachine Cycles

Instruction Time (I-time)– The instruction control unit fetches the next

instruction from memory

– The address of the next instruction is found in the instruction counter

– The instruction control unit extracts this address and sends it over the bus to the memory controller

– The memory controller accepts the command, reads the requested memory location and copies its contents onto the bus.

Linking the ComponentsLinking the ComponentsMachine CyclesMachine Cycles

Instruction Time (I-time)– The current instruction moves over the

bus and into the instruction register.

Fig. 4.2a: Fig. 4.2a: A A machine cyclemachine cycle(I-Time).(I-Time).

P rocessor

M em ory

C lo ckIn stru c tio nco n tro l u n it

A r ith m etic a n dlo g ic u n it

In stru c tio nco u n ter

1 0 0 0

In stru c tio n reg is terW o rk reg is ter s

0 1

2 3

P ro g ra ma d d ress in stru c tio n

1 0 0 0 L O A D 2 ,2 0 0 0

D a taa d d ress co n ten ts

2 0 0 0 1 5

M em o ry co n tro ller

B u s

F etch

The instruction control unit sends a fetch command over the bus to memory.

Fig. 4.2b: Fig. 4.2b: A A machine cyclemachine cycle(I-Time).(I-Time).

P rocessor

M em ory

C lo ckIn stru c tio nco n tro l u n it

A r ith m etic a n dlo g ic u n it

In stru c tio nco u n ter

1 0 0 1

In stru c tio n reg is terW o rk reg is ter s

0 1

2 3

P ro g ra ma d d ress in stru c tio n

1 0 0 0 L O A D 2 ,2 0 0 0

D a taa d d ress co n ten ts

2 0 0 0 1 5

M em o ry co n tro ller

B u sL O A D 2 ,2 0 0 0

Memory responds by copying the contents of the requested memory location onto the bus.

Fig. 4.2c: Fig. 4.2c: A A machine cyclemachine cycle(I-Time).(I-Time).

P rocessor

M em ory

C lo ckIn stru c tio nco n tro l u n it

A r ith m etic a n dlo g ic u n it

In stru c tio nco u n ter

1 0 0 1

In stru c tio n reg is terW o rk reg is ters

0 1

2 3

P ro g ra ma d d ress in stru c tio n

1 0 0 0 L O A D 2 ,2 0 0 0

D a taa d d ress co n ten ts

2 0 0 0 1 5

M em o ry co n tro ller

B u s

L O A D 2 ,2 0 0 0

The instruction moves into the instruction register.

Linking the CoponentsLinking the CoponentsMachine CyclesMachine Cycles

Execution Time (E-time)– The ICU activates the arithmetic and

logic unit.– The ALU executes the instruction in the

instruction register.– The ALU issues, over the bus, a

command to fetch the contents of a specified memory location.

Linking The ComponentsLinking The ComponentsMachine CyclesMachine Cycles

Execution Time (E-time)– The memory controller reads the

requested word and copies the contents onto the bus.

– The data flow to a work register.

Fig. 4.2d: Fig. 4.2d: A A machine cyclemachine cycle(E-Time).(E-Time).

P rocessor

M em ory

C lo ckIn stru c tio nco n tro l u n it

A r ith m etic a n dlo g ic u n it

In stru c tio nco u n ter

1 0 0 1

In stru c tio n reg is terW o rk reg is ter s

0 1

2 3

P ro g ra ma d d ress in stru c tio n

1 0 0 0 L O A D 2 ,2 0 0 0

D a taa d d ress co n ten ts

2 0 0 0 1 5

M em o ry co n tro ller

B u s

L O A D 2 ,2 0 0 0

The arithmetic and logic unit executes the instruction in the instruction register.

Fig. 4.2e: Fig. 4.2e: A A machine cyclemachine cycle(E-Time).(E-Time).

P rocessor

M em ory

C lo ckIn stru c tio nco n tro l u n it

A r ith m etic a n dlo g ic u n it

In stru c tio nco u n ter

1 0 0 1

In stru c tio n reg is terW o rk reg is ter s

0 1

2 3

P ro g ra ma d d ress in stru c tio n

1 0 0 0 L O A D 2 ,2 0 0 0

D a taa d d ress co n ten ts

2 0 0 0 1 5

M em o ry co n tro ller

B u s

L O A D 2 ,2 0 0 0

F etch 2 0 0 0

The arithmetic and logic unit fetches the data.

Fig. 4.2f: Fig. 4.2f: A A machine cyclemachine cycle(E-Time).(E-Time).

P rocessor

M em ory

C lo ckIn stru c tio nco n tro l u n it

A r ith m etic a n dlo g ic u n it

In stru c tio nco u n ter

1 0 0 1

In stru c tio n reg is terW o rk reg is ters

0 1

2 15 3

P ro g ra ma d d ress in stru c tio n

1 0 0 0 L O A D 2 ,2 0 0 0

D a taa d d ress co n ten ts

2 0 0 0 1 5

M em o ry co n tro ller

B u s

L O A D 2 ,2 0 0 0

The data value flows over the bus and into a work register.

Linking The ComponentsLinking The ComponentsArchitectureArchitecture

Architecture– The interconnections that link a computer’s

components.– Single Bus Architecture

All components are linked to a common bus.

– Multiple-Bus ArchitectureProcessor and Channel processing

Fig. 4.3: Fig. 4.3: Microcomputers are Microcomputers are constructed around a metal constructed around a metal framework called a framework called a motherboard.motherboard.

P ro cesso ra n d re la tedco m p o n en ts

P o w ersu p p ly

B u s

S lo ts

Fig. 4.4: Fig. 4.4: The The bus links the bus links the processor to a processor to a number of number of slots into slots into which which components components can be can be plugged.plugged.

P ro cesso r

B u s

S lo t

S lo t

S lo t

S lo t

Fig. 4.5: Fig. 4.5: Memory and Memory and peripheral devices peripheral devices are added by are added by plugging a memory plugging a memory board or an board or an interface board into interface board into one of the open one of the open slots.slots.

P ro cesso r

B u s

S lo t

S lo t

S lo t

S lo t

M em o ry

D isp la yin ter fa ce

P r in terin ter fa ce

D isk e ttein ter fa ce

Linking the ComponentsLinking the ComponentsInterfacesInterfaces

Each peripheral device has its own interface– The basic function of the interface is

translation.One side of the interface communicates with the

computerThe other side is device dependent,

communicating with the external device in its own terms.

Fig. 4.7: Fig. 4.7: The function of an The function of an interface is to translate interface is to translate between internal and external between internal and external form.form.

T h e in ter fa cetra n s la te s

D a ta in th eco m p u ter 's

in tern a l fo rm

D a ta in th ep er ip h era l's

ex tern a l fo rm

Fig. 4.5: Fig. 4.5: With single-bus With single-bus architecture all the architecture all the components are linked to a components are linked to a common bus.common bus.

P ro cesso r B u s

M em o ry In ter fa ce

In ter fa ce In ter fa ce

Linking the ComponentsLinking the ComponentsChannels and Control UnitsChannels and Control Units

Microcomputers are designed for single users, so single-bus architecture is reasonable.

Channels and Control UnitsChannels and Control UnitsMainframes support multiple users

concurrently.– Unlike the microcomputer, the mainframe

processor is freed from controlling I/O.– Channel

A micro or minicomputer with its own processorCan perform logical functions in parallel with the

computer’s main processor.

Fig. 4.7: Fig. 4.7: Device-independent functions are Device-independent functions are assigned to a channel and device-assigned to a channel and device-dependent functions are assigned to an I/O dependent functions are assigned to an I/O control unit.control unit.

C o m p u ter C h a n n e lI /O co n tro l

u n it

I /O co n tro lu n it

I /O co n tro lu n it

D ev ice A

D ev ice B

D ev ice C

Multiple- Bus ArchitectureMultiple- Bus ArchitectureThe processor manipulates data in

memory.A channel moves data between memory

and a peripheral device.Because a single-bus architecture provides

only one physical data path, only one user can be supported at any one time.

Because a mainframe supports multiple users, a multiple-bus architecture is used.

Fig. 4.8a: Fig. 4.8a: Most mainframes Most mainframes use multiple-bus architecture.use multiple-bus architecture.

Processor

Memory

Channel

Command bus

Data bus

Internalbus

The processor starts an I/O operation by sending a signal to the channel.

Fig. 4.8b: Fig. 4.8b: Most mainframes Most mainframes use multiple-bus architecture.use multiple-bus architecture.

Processor

Memory

Channel

Command bus

Data bus

Internalbus Data

The channel handles the I/O operation and the processor turns to another program.

Fig. 4.8c: Fig. 4.8c: Most mainframes Most mainframes use multiple-bus architecture.use multiple-bus architecture.

Processor

Memory

Channel

Command bus

Data bus

Internalbus

The channel sends an interrupt to the processor to signal the end of the I/O operation.

Logical and Physical I/OLogical and Physical I/O

Primitive– A physical operation performed by an

interface or a peripheral device.Open

– The process of initially establishing a link to a peripheral device.

Logical and Physical I/OLogical and Physical I/O

Logical I/O– The programmer’s view of I/O.

Physical I/O– The act of physically transferring a unit of

data between memory and a peripheral device.Access Method

– A subroutine that performs application-dependent portions of an I/O operation.

Fig. 4.9: Fig. 4.9: A programmer’s logical I/O A programmer’s logical I/O request is converted to the appropriate request is converted to the appropriate physical I/O operation by the operating physical I/O operation by the operating system.system.

A p p lica tio np ro g ra m

L o g ica l I /Oreq u est

O p era tin gsy stem

H a rd w a re

P r im itiv ep h y s ica l

co m m a n d s

Fig. 4.10: Fig. 4.10: On some mainframes, On some mainframes, application-dependent portions of the application-dependent portions of the logical-to-physical translation are logical-to-physical translation are

assigned to access methods.assigned to access methods.

A p p lica tio np ro g ra m

L o g ica l I /Oreq u est

O p era tin gsy stem

H a rd w a re

P r im itiv ep h y s ica l

co m m a n d s

A ccess m eth o d

Fig. 4.11: Fig. 4.11: The linkage editor adds the The linkage editor adds the access method to the load module at load access method to the load module at load time.time.

Linkageeditor

Programobject

module

Accessmethod

Programobject

module

Accessmethod

Object modulelibrary

System library

Fig. 4.12: CFig. 4.12: Converting onverting a logical I/O request a logical I/O request to primitive physical to primitive physical commands.commands.

Application pgm

1. Issue logical I/Orequest.

Access method

2. Set up channelprogram.

Operating system

3. Start I/Ooperation.

7. Restartapplication program.

Channel

4. Get channelprogram.

5. Start device.

6 Interrupt operatingsystem.

Channel/control unit

Channelprogram

Peripheral device

Fig. 4.13: Fig. 4.13: A message consists A message consists of a header, a body, and a of a header, a body, and a trailer.trailer.

M essa g e

H ea d er B o d y T ra iler

NetworksNetworks

Network

– two or more computers linked by communication lines

Network types

– local area network (LAN)

– wide area network (WAN)

Fig. 4.14: Fig. 4.14: On a bus On a bus network server the, network server the, workstations, and workstations, and various peripheral various peripheral devices all share a devices all share a common bus.common bus.

N etw o rk serv er

W o rk sta tio n

W o rk sta tio n

W o rk sta tio n

W o rk sta tio n

Fig. 4.15: Fig. 4.15: In a hierarchical network the In a hierarchical network the

computers are linked to form a hierarchycomputers are linked to form a hierarchy. .

Fig. 4.16: Fig. 4.16: In a star In a star network each host network each host is linked to a central is linked to a central

star machine.star machine.

T h e " sta r"co m p u ter

Fig. 4.17: Fig. 4.17: In a In a ring network ring network the the connections connections

form a ring.form a ring.

Fig. 4.18: Fig. 4.18: A bridge A bridge links two or more links two or more similar networks. similar networks. A gateway links A gateway links dissimilar dissimilar networks.networks.

S erv er S erv er

B r id g e

S erv er

G a tew a y

Network ManagementNetwork Management A network operating system helps to manage the

system.– each computer is a node– Each node has a unique address– messages routed from node to node

Polling– When 2 or more computers try to transmit data at the

same time over the same line, their messages can interfere with each other.

– With Polling the network server sends a polling signal to each workstation.

– Messages are transmitted only in response to a polling signal.

Network ManagementNetwork Management

Collision detection– Allows the workstation to send messages

whenever they want.– If 2 messages are transmitted at the same time,

the signals interfere with each other.– The “collision” is detected electronically and

the affected messages are retransmitted.

Network ManagementNetwork Management

Token Passing– The signal (the token) moves continuously

around the network and a computer is allowed to transmit a message only when it holds the token.