3.IC&ECAD-MANUAL - Copy.docx

III B.TECH - I SEM (R09) ECE : IC APPLICATIONS & ECAD LAB __________________________________________________________________

III B.TECH - I SEM (R09) ECE : IC APPLICATIONS & ECAD LAB100

Exp.No. 1OP AMP APPLICATIONSADDER, SUBTRACTOR, COMPARATOR CIRCUITS

Exe.No.

Dt.

AIM:To construct an adder, subtractor and comparator using 741 Op-Amp and to verify their operation.

APPARATUS:

S.No.Name of the equipmentRangeNo.s

1IC 7411

2CRO20 MHz1

3Function generator20 MHz1

4Bread board1

5Dual Power Supply(-12V) 0 (+12V)1

6Regulated Power Supply0-5V2

7Resistors10 k5

8CRO probes2

9Connecting wires10

DESIGN:

Adder / Summing amplifier:

The output of Adder V0 = - (V1+V2)ChooseRf = R1 = 10 k thenV0 = - (V1+V2)

Subtractor:The output of Subtractor V0 = (Vb-Va)Choose Rf = R1 = 10 k thenV0 = Vb-Va

THEORY:

Summer/Adder:

Op-Amp can be used to design a circuit whose output is the sum of several input signals. Such a circuit is called summing amplifier or summer. Obtain either non-inverting (or) inverting summer. Fig.1 (a) shows the circuit diagram of two input inverting summer. It has two input voltages V1 and V2 which are applied to inverting terminal of Op-Amp. The Non-inverting terminal of Op-Amp is grounded.

In order to understand the operation of the circuit, assume the following conditions.

(i). Since input resistance of Op-Amp is very large,the current drawn by either of input terminals of Op-Amp is ZERO.i.e., IB1 = IB1 = 0(ii). Since Open loop gain of Op-Amp is very large,the difference input (Vp-Vn) is essentially ZERO for a finite output voltage.i.e., (Vp-Vn) = 0 Vp = Vn

In the circuit shown in Fig.1(a), Since Vp is connected to physical ground, Vn is also at ground potential. This is called Virtual ground. Due to virtual ground, Vp = Vn = 0.

Referring Fig.1(a), Apply KCL at node n , we have + + + IB1=0- ( + ) =( since Vn = Vp = 0 & IB1 = 0)If R1 = R2thenV0 = - (V1+V2)

Thus output is amplified and inverted sum of two inputs.

Note: For non-inverting summing amplifier, V0 = ( 1 + ) (V1+V2)

Subtractor :

A basic differential amplifier can be used as a subtractor. It has two input signals Va and Vb applied to inverting & non-inverting terminals respectively.

From the Fig.1(b),Vp = RfReferring Fig.1(b), Apply KCL at node n - we have++ IB1=0

(+) =+( since IB1 = 0)Vn( +) - = = Rf ( ) - ( since Vn = VpV0 = ( Vb Va)

Thus, the output voltage V0 is equal to the voltage Vb applied to the non inverting terminal minus voltage Va applied to inverting terminal.

.Comparator:

A comparator is a circuit which compares signal voltage applied at one input terminal of an op-amp with a known reference voltage at the other input terminal. It is basically an openloop op-amp with output Vsat as in the ideal transfer characteristics.

The output of comparator is given byInput to comparatorOutput of comparator

If Vp>VnVo = + Vsat

If Vp f L , the gain is constant and equal to AF(ii) At frequency f = f L, the gain is times of its maximum value.This frequency is called as Cut-off frequency/ Break frequency / 3-dB frequency.(iii) For Low frequencies f< f L, the gain changes at a rate of 20 dB/ decade.

CIRCUIT DIAGRAM:

MODEL GRAPH:

PROCEDURE:1. Connect the circuit as shown in Fig.2.22. Apply sine wave of amplitude 1 Vp-p to the non inverting input terminal.3. Vary the frequency of input signal from 10 Hz to 100 kHz.4. Note down the corresponding output voltage for each frequency.5. Tabulate the values and calculate the gain in dB.6. Plot a graph between frequency and gain.8. Calculate the 3-dB frequency and Identify stop band & pass band from the graph.

TABULAR COLUMN:Vin = 1 VS.No.Frequency(Hz)V0(volts)Gain in dB20 log (Vo / Vin )

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

RESULT:

VIVA QUESTIONS:

1. What is the function of the filter?2. What are the different types of filters?3. What are the advantages of Active filters?3. Define pass band and stop band of filters?4. Define cut off frequency of a filter?5. What is the difference between HPF & LPF?

Exp.No. 3FUNCTION GENERATOR USING OP-AMP

Exe.No.

Dt.

AIM:To design a function generator using Op-Amp to generate square wave, triangular wave & saw tooth waveforms at 1 kHz frequency.

APPARATUS:


1IC 7412

2CRO20 MHz1

3Bread board1


5Capacitor0.1 F1

6Resistor330 1

7Potentiometers1 k1

10 k1

47 k1

8CRO probes2

9Connecting wires10

DESIGN:Let Vsat = 10VThe amplitude of Triangular wave V01 = VsatFor a triangular wave of 5 V amplitude, = 0.25Use R2 = 330 standard resistor & R1 = 1 k POT.

Time Period of Triangular wave F = For output frequency of 1 kHz, T = 1 msChoose C = 0.1 F then R3 = 10 k .

THEORY:

The function generator generates different types of waveforms which are functions of time. The circuit shown in Fig.4.1. is a function generator which generates square and triangular wave. It consists of a comparator and an integrator. The output of comparator is a square wave of amplitude Vsat . This voltage is applied to the inverting of integrator A2 producing a triangular wave.

The operation of the function generator can be explained as follows:

Initially let us consider the o/p of comparator v01 = +Vsat.Since this +Vsat is applied to integrator, the o/p of integrator v02 is a -ve ramp.Since v02 is ve ramp, the node voltage Vp decreases.At time t= T1 , Vp decreases, crosses ZERO and goes in -ve direction.This switches the o/p of comparator from +Vsat to - Vsat.Now the o/p of integrator v02 is +ve ramp signal & Vp increases.This switches the o/p of comparator from -Vsat to + Vsat.This cycle repeats.

The amplitude of Square wave v01 = +VsatThe amplitude of Triangular wave v02 = VsatTime Period of Triangular wave F =

CIRCUIT DIAGRAM:

MODEL GRAPH:

OBSERVATIONS: ( for Triangular wave generator )

Peak-to-peakamplitude (V)T1 (ms)T2 (ms)T(ms)frequency (Hz)

Triangular waveform

Square wave o/p

CIRCUIT DIAGRAM:

MODEL GRAPH:

OBSERVATIONS: ( for Sawtooth waveform generator )

Peak-to-peakamplitude (V)T1 (ms)T2 (ms)T(ms)frequency (Hz)

Sawtooth waveform

Square wave o/p

PROCEDURE:

1. Connect the circuit as shown in the Fig.3.1.2. Observe the triangular waveform output at pin (6) of Op-Amp (A2) and square wave output at pin (6) of Op-Amp (A1).3. Note down the amplitude & time periods of square wave and triangular wave outputs4. Plot the waveforms on a graph sheet.5. To get the saw tooth waveform, connect the circuit as shown in fig.3.3.6. Repeat the steps 2, 3 & 4.

RESULT:

VIVA QUESTIONS:

1. What is a function generator?2. List some applications of function generator?3. What is the use of integrator circuit in function generator?4. Which circuit acts as a square wave generator?

WORKSPACE

Exp.No. 4(a)MONOSTABLE MULTIVIBRATORUSING IC 555 TIMER

Exe.No.

Dt.

AIM:To construct and study the operation of a monostable multivibrator using IC 555 timer.

APPARATUS:


1IC 555 Timer1

2CRO20 MHz1

3Function generator20 MHz1

4Bread board1

5Regulated Power Supply0 - 30 V1

6Capacitors0.01 F1

0.1 F2

7Electrolyte capacitor10 F1

8Resistors1 k1

10 k1

9Diode BY1271

10CRO probes2

11Connecting wires10

DESIGN:

Let the trigger input T = 4 ms ( f = 250 Hz )Output pulse width of monostable multi tp = 1.1 RCFor the pulse width of 1.1 ms, Choose C = 0.1 F then R = 10 k.

THEORY:

The monostable multi vibrator has one stable state and one quasi stable state. The circuit remains in its stable state until an external trigger pulse is applied. When the external trigger pulse is applied to monostable circuit, it switches to quasi-stable state and after a pre-defined time interval it will automatically comes back to its original stable state. This circuit is also called asone shot multivibrator.

This circuit is useful for generating a single output pulse of required period in response to a triggering signal. The width of the output pulse depends only on external components R & C. The negative triggering pulses are generated through input differentiator circuit & diode D.

Let us assume that the circuit is in stable state i.e., the output V0 is at +Vsat.

When the negative trigger is applied at pin (2), The output of internal comparator C2 goes to HIGH state and sets the flip-flop. Hence output V0 goes to HIGH state which is its quasi stable state Now the capacitor C starts charging towards +Vcc through R.When the capacitor voltage reaches Vcc which is the threshold voltage of comparator C1The output of internal comparator C1 goes to LOW state and resets the flip-flop.Hence output V0 goes to LOW state which is its stable state.Now internal transistor T1 will be ON and capacitor discharges through T1.

The duration of quasi stable state (or) output pulse duration of mono-stable multivibrator depends on the capacitor charging time constant i.e., the time required for the capacitor to charge up to Vcc. It is given bytp = 1.1 RC

The applications of 555 timer in mono-stable mode are (i) Missing pulse detector(ii) Frequency divider(iii) Linear ramp generator(iv) Pulse width modulator

CIRCUIT DIAGRAM:

INTERNAL DIAGRAM OF IC 555 :

MODEL GRAPH :

PROCEDURE:

1. Connect the circuit as shown in Fig.4.12. Apply a negative triggering at pin (2).3. Measure the output voltage at pin (3) by connecting it to the channel-1.4. Measure the output voltage across capacitor at pin (7) by connecting it to the channel-2 5. Note down the amplitude & time period of output pulse and compare with theoretical values.6. Plot the graph for input & output waveforms

RESULT :

VIVA QUESTIONS :

1. What is another name for mono stable multi?2. What is the purpose of pin reset?3. Define duty cycle?4. What are the various applications of one shot?5. How many external triggers are necessary in one shot?Exp.No. 4(b)ASTABLE MULTIVIBRATORUSING IC 555 TIMER

Exe.No.

Dt.

AIM:To construct and study the operation of the astable multivibrator using IC 555 timer.

APPARATUS:


1IC 555 Timer1

2CRO20 MHz1

3Bread board1


5Capacitors0.01 F1

0.1 F1

6Resistor6.8 k2

7Diode BY1271

8CRO probes2

9Connecting wires10

DESIGN:

Let Vcc = 10 V, T1 = 1 ms, T2 = 0.5 ms

For astable multivibrator using IC 555 timer, T1 = 0.693 (RA+RB) CT2 = 0.693 RB C

Let C = 0.01 F then, RB = 6.8 k & RA = 6.8 k.

THEORY :

The astable multivibrator has two quasi-stable states and it continuously switches between these two quasi-stable states. The duration of each quasi stable states depends only on external components RA , RB & C. It is also called as square wave generator / free running multivibrator.

The astable multivibrator is useful for generating a square wave of required time period & duty cycle. The circuit shown in Fig.4.5. is the astable multivibrator using 555 timer. The operation of this circuit can be explained as follows:

Consider an instant when the o/p is at HIGH state.When v0 is at HIGH, the o/p of internal Flip-flop Q =1 & Q1 = 0Since, Q1 = 0, The internal Transistor OFF & capacitor C starts charging towards + Vcc with time constant (RA+RB) C.

This capacitor voltage is applied as threshold input to comparator C1.At time t= T1 , the capacitor voltage reaches Vcc , the output of C1 becomes HIGH.This HIGH output from C1 resets the Flip-flop & Hence Q = 0 & Q1 = 1.Now output When v0 is LOW & Since Q1 = 1, the internal Transistor ON. & capacitor C starts discharging through transistor with time constant RBC.This capacitor voltage is applied as trigger input to comparator C2.At time t= T1 , the capacitor voltage reaches Vcc , the output of C2 becomes HIGH.This HIGH output from C2 sets the Flip-flop & Hence Q = 1 & Q1 = 0.This makes the transistor OFF and again capacitor C starts charging.

Thus the capacitor periodically charges and discharges between Vcc and Vcc. The time during which the capacitor charges from Vcc to Vcc is called as charging period (or) ON time and it is given by T1 = 0.693 (RA+RB) C.

The time during which the capacitor discharges from Vcc to Vcc is called as discharge period (or) OFF time and it is given by T2 = 0.693 RBC.

The time period of output square wave is T = ( T1 + T2 ) = 0.693 (RA+2RB) C.

The duty cycle D = =

CIRCUIT DIAGRAM:

INTERNAL DIAGRAM OF IC 555 :

MODEL GRAPH :

OBSERVATIONS :PRACTICAL VALUESTHEORITICAL VALUES

-ve peak(V)+ve peak(V)T1(ms)T2(ms)T (ms)-ve peak(V)+ve peak(V)T1(ms)T2(ms)T (ms)

Output at pin(3)

Output at pin(7)

PROCEDURE:

1. Connect the circuit as shown in Fig.4.32. Switch on the power supply Vcc (+10V)3. Measure the output voltage at pin (3) by connecting it to the channel-1.4. Measure the output voltage across capacitor at pin (7) by connecting it to the channel-2 5. Note down the amplitude & time period of output waves and compare with theoretical values.6. Plot the graph for output waveforms

RESULT :

VIVA QUESTIONS:

1. Define astable multi?2. What is the other name for astable multi?3. Mention the applications of free running oscillator?4. How many external triggers are necessary for astable?

WORKSPACE

Exp.No. 5(a)VOLTAGE REGULATOR USING IC 723 LOW VOLTAGE REGULATOR

Exe.No.

Dt.

AIM : (a) To design and verify a low voltage regulator for an output voltage of 6V. (b) To obtain load regulation characteristics.

APPARATUS:


1LM 723 IC1

2Bread board1


4dc ammeter0-2 A1

5dc voltmeter0-20 V1

6Digital multimeter1

7Capacitors0.1 F1

100 pF1

8Resistors1 k1

2.2 k1

5.6 k1

10 k1

15 k1

9Potentiometer22 k1


DESIGN :

The output of a low voltage regulator using IC723 is given by V0 = 7.15 *( )

For an output voltage of 6V,

Let R1 = 1 k then, R2 = 5.2 k (use R2 = 5.6 k )

Choose C = 100 pF & R3 = = 2.2 k.

THEORY:

A voltage regulator is a circuit that supplies constant voltage regardless of changes in load current,temperature ,power supply. Except for the switching regulators, all other types of regulators are linear regulators. LM 723 IC is general purpose linear voltage regulator.Input voltage of this 723 IC is 40 V maximum. Output voltage is adjustable from 2V to 30 V.

The functional block diagram of IC 723 has two sections.

(i) Reference constant voltage source: The zener diode and a constant current source produces a fixed voltage about 7.15V at terminal Vref.

(ii) Error Amplifier: A series pass transistor Q1 and a current limiting resistor Q2

Low Voltage Regulator:The Vref is applied to non-inverting input of error amplifier through a potential divider. The difference between VP and V0 is applied to the

The output of low voltage regulator is given by

V0 = 7.15 *( )

CIRCUIT DIAGRAM:

TABULAR COLUMN :

S.No.Input Voltage Vin (Volts)Output Voltage Vo (Volts)

1

2

3

4

5

6

7

8

9

10

11

12

Line Regulation

PROCEDURE:

1. Connect the circuit as shown in fig 5.1.2. Connect the power supply between 12 and 7 pins3. Connect the volt meter between 10 and 7 pins4. Vary the input voltage from 0V to 12V in steps and note down the correspondingOutput voltage.5. Draw the graph between input voltage and output voltage.

RESULT:

VIVA QUESTIONS:

1. What is regulator?2. What is meant by line regulation?3. What is meant by load regulation?4. Formula for % REGULATION?5. What is full load in voltage regulation?

Exp.No. 5(b)VOLTAGE REGULATOR USING IC 723 HIGH VOLTAGE REGULATOR

Exe.No.

Dt.

AIM: To design and set up a High voltage regulator for an output voltage of 12V.

APPARATUS:


1LM 723 IC1

2Bread board1


4dc ammeter0-2 A1

5dc voltmeter0-20 V1

6Digital multimeter1

7Capacitors0.1 F1

100 pF1

8Resistors1 k1

2.2 k1

5.6 k1

10 k1

15 k1

9Potentiometer22 k1


DESIGN :

The output of a high voltage regulator using IC732 is given by V0 = 7.15 *(1+ ) For an output voltage of 12V, Let R1 = 10 k then, R2 = 17.7 k (use R2 = 15 k).

Choose C = 100 pF & R3 = 6.8 k

CIRCUIT DIAGRAM:

TABULAR COLUMN :S.No.Input Voltage Vin (Volts)Output Voltage Vo (Volts)

1

2

3

4

5

6

7

8

9

10

11

12

Line Regulation

PROCEDURE:

LINE REGULATION

1. Connect the circuit as shown in fig 5.2.2. Connect the power supply between 12 and 7 pins3. Connect the volt meter between 10 and 7 pins4. Vary the input voltage from 0V to 15V in steps and note down the corresponding Output voltage.5. Draw the graph between input voltage and output voltage.

RESULT:

VIVA QUESTIONS:

1. What is regulator?2. What is meant by line regulation?3. What is meant by load regulation?4. Formula for % REGULATION?5. What is full load in voltage regulation?

WORKSPACE

Exp.No. 64 - BIT DAC USING OP AMP

Exe.No.

Dt.

AIM: To construct and verify 4-bit digital to analog converter.

APPARATUS:S.No.Name of the equipmentRangeNo.s

14-bit DAC trainer1


3Regulated Power Supply5V1

4Multimeter1

5Patch cards4

THEORY:The Digital to Analog Converter (DAC) converts n-bit binary word into equivalent analog voltage or current . The DAC uses an Op-Amp as current to voltage converter and a binary weighted resistor network (or) R-2R ladder network.

Weighted Resistor DAC:The weighted resistor DAC uses a binary weighted resistor network which consists of n- resistors with values 20R, 21R, 22R, 23R, 2n-1R. The input binary data ( b0b1b2b3 .) is applied to weighted resistor network through digitally controlled SPDT switches. If the binary input to a particular switch is 1, it connects resistance to the reference voltage (VR) and if the input is 0, the switch connects the resistor to the ground. The disadvantage of weighted resistor DAC is it requires wide range of resistors values (20R to 2n-1R). Also the fabrication of large values of resistors on IC is difficult. R-2R ladder DAC:In binary weighted resistor DAC, wide range of resistors values (20R to 2n-1R) are required. This can be avoided by using R-2R ladder type DAC where only 2 values of resistors are required ( R and 2R) . The input binary data ( b0b1b2b3) is applied through digitally controlled SPDT switches. Binary inputs can be high (+5V) or low(0V).

If the binary input to a particular switch is 1, it connects resistance to the reference voltage (VR) and if the input is 0, the switch connects the resistor to the ground.

The output current I0 is the binary weighted sum of all currents and it is given by

I0 = bn-1 + bn-2 + bn-3 + .+ b0

CIRCUIT DIAGRAM:

TABULAR COLUMN:Binary Input Equivalent Decimal NumberTheoretical Analog output (V)Practical Analog output (V)

0 0 0 00

0 0 0 11

0 0 1 02

0 0 1 13

0 1 0 04

0 1 0 15

0 1 1 06

0 1 1 17

1 0 0 08

1 0 0 19

1 0 1 010

1 0 1 111

1 1 0 012

1 1 0 113

1 1 1 014

1 1 1 115

PROCEDURE:

1. Connect the circuit as shown in figure 6.1.2. Pin7 is connected to +Vcc and Pin 4 is connected to -Vcc 3. Apply the Binary input ( b0b1b2b3).4. Output is taken between Pin 6 and ground5. Measure the corresponding output voltage using Multimeter and tabulate.6. Plot the graph between binary input and analog output.

RESULT:

VIVA QUESTIONS:

1. What is meant by resolution,linearity & accuracy of DAC?2. What are the disadvantages of weighted resistor DAC?3. What are the values of resistors required in weighted resistor DAC if LSB resistor value is 12K for a 4 bit DAC?4. What are the applications of DAC?

WORKSPACE

.No. 1LOGIC GATES

Exe.No.

Dt.

AIM: To Simulate all basic gates and universal gates using VHDL. TOOLS: VHDL software XILINX 9.2IMODELSIM simulator

PROCEDURE:

1. Write separate VHDL programs for all basic gates and universal gates.2. Simulate them by using MODELSIM simulator.3. Draw the wave forms separately.

AND GATE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AND2 is Port ( A : in std_logic; B : in std_logic; Y : out std_logic);end AND2;

architecture Behavioral of AND2 isbeginY

Documents

3.IC&ECAD-MANUAL - Copy.docx