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3D Simulation and Analysis of 3D Simulation and Analysis of the Radiation Tolerance of the Radiation Tolerance of

Voltage Scaled Digital CircuitsVoltage Scaled Digital Circuits

Rajesh GargRajesh GargSunil P. KhatriSunil P. Khatri

Department of ECEDepartment of ECETexas A&M UniversityTexas A&M University

College Station, TXCollege Station, TX

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OutlineOutline

Background and MotivationBackground and Motivation

Previous WorkPrevious Work

Simulation SetupSimulation Setup

Results and DiscussionsResults and Discussions Circuit-level hardening guidelinesCircuit-level hardening guidelines

Model for Charge collectedModel for Charge collected

ConclusionsConclusions

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n+

S

n+

p-substrate

G

D

VDD

Depletion Region

Radiation Particle

_ ++_

_ +_

+_

+ _+_+

E_+VDD - Vjn

E

Charge Deposition by a Charge Deposition by a Radiation ParticleRadiation Particle

Radiation particles - protons, neutrons, alpha particles and heavy Radiation particles - protons, neutrons, alpha particles and heavy ionsions

Reverse biased Reverse biased p-np-n junctions are most sensitive to particle strikes junctions are most sensitive to particle strikes Charge is collected at the Charge is collected at the

drain nodedrain node throughthrough drift drift and diffusionand diffusion

Results in a voltage glitch Results in a voltage glitch at the drain node at the drain node

System state may change System state may change if this voltage glitch is if this voltage glitch is capturedcaptured by at least one by at least one memory elementmemory element This is called an This is called an SEUSEU May causeMay cause system failure system failure

B

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Radiation Strike ModelRadiation Strike Model Charge deposited (Charge deposited (QQDD) by a radiation particle is given by) by a radiation particle is given by

where: where: LL is the Linear Energy Transfer (MeV-cmis the Linear Energy Transfer (MeV-cm22/mg)/mg)

tt is the depth of the collection volume (mm) is the depth of the collection volume (mm)

A radiation particle strike is modeled by a current A radiation particle strike is modeled by a current pulse aspulse as

wherewhere: : QQcollcoll is the amount of charge collected is the amount of charge collected

(assumed (assumed QQcollcoll = Q = QDD in worst case analysis) in worst case analysis)

is the collection time constantis the collection time constant

is the ion track establishment constantis the ion track establishment constant

The radiation induced current always flows from The radiation induced current always flows from nn-diffusion to -diffusion to pp--diffusiondiffusion

tLQD 01036.0

)()(

)( //

ttcoll

seu eeQ

ti

Q = 0.1pC = 150ps = 50ps

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Radiation Particle StrikesRadiation Particle Strikes Radiation particle strike at the output of INV1Radiation particle strike at the output of INV1 Implemented using 65nm PTM with VDD=1VImplemented using 65nm PTM with VDD=1V Radiation strike: Radiation strike: QQ=100fC, =100fC, =200ps & =200ps & =50ps=50ps

Models Radiation Particle Strike

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MotivationMotivation Modern VLSI DesignsModern VLSI Designs

Vulnerable to noise effects- crosstalk, SEU, etcVulnerable to noise effects- crosstalk, SEU, etc

Single Event Upsets Single Event Upsets (SEUs) or Soft Errors(SEUs) or Soft Errors Troublesome for both memories and Troublesome for both memories and

combinational logiccombinational logic Becoming increasingly problematic even for Becoming increasingly problematic even for

terrestrial designsterrestrial designs

Applications demand reliable systemsApplications demand reliable systems Need Need to efficiently to efficiently design design radiation tolerant radiation tolerant

circuitscircuits

MotivationMotivation Power is becoming a major issuePower is becoming a major issue

Low power/energy solutions are desired for SoCs, Low power/energy solutions are desired for SoCs, microprocessors, etcmicroprocessors, etc

Both Both PPdyndyn and and PPlkglkg decreasedecrease atleast atleast quadraticallyquadratically with with

decreasing supply voltagesdecreasing supply voltages DecreaseDecrease the supply voltage in the non-critical parts the supply voltage in the non-critical parts

Dynamic voltage scaling (DVS) is extensively Dynamic voltage scaling (DVS) is extensively usedused to meet to meet variable speed/power requirementsvariable speed/power requirements

Sub-threshold circuits are also becoming Sub-threshold circuits are also becoming popularpopular to to implement extremely low power systemsimplement extremely low power systems Useful for applications which can tolerate large delayUseful for applications which can tolerate large delay

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lkgdyn PPP

3D Simulations of Radiation Strikes3D Simulations of Radiation Strikes Reliability of DVS and sub-threshold circuits important for the Reliability of DVS and sub-threshold circuits important for the

reliability of VLSI systemsreliability of VLSI systems Need to Need to analyzeanalyze the effects of radiation strikes on such circuits the effects of radiation strikes on such circuits

Harden the circuits based on the results of this analysisHarden the circuits based on the results of this analysis

SPICE SPICE cannotcannot be used for this analysis be used for this analysis The The effect of a radiation particle strike effect of a radiation particle strike is modeled, not the radiation strike itselfis modeled, not the radiation strike itself

3D simulations of radiation particle strikes in DVS and sub-3D simulations of radiation particle strikes in DVS and sub-threshold circuits need to be performed for an accurate analysis threshold circuits need to be performed for an accurate analysis (for example, obtain the fraction of (for example, obtain the fraction of QQDD that is collected) that is collected)

We performed 3D simulations We performed 3D simulations of a radiation strike in an of a radiation strike in an inverterinverter implemented using a 65 nm technology for different supply implemented using a 65 nm technology for different supply voltages (from voltages (from nominal value nominal value to to <V<VTT))

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Previous WorkPrevious Work Palau et al. 2003 Palau et al. 2003 studied radiation-induced transients and studied radiation-induced transients and

SER in SRAMs using a 3-D device simulation toolSER in SRAMs using a 3-D device simulation tool Studied effects of different radiation particle tracks on SERStudied effects of different radiation particle tracks on SER Effect of voltage scaling on SER not studiedEffect of voltage scaling on SER not studied

Irom et al. 2002 Irom et al. 2002 performed an experimental study of the performed an experimental study of the effects of radiation strikes in PowerPC microprocessorseffects of radiation strikes in PowerPC microprocessors Processors were implemented using 0.18 Processors were implemented using 0.18 m and 0.13 m and 0.13 m technologiesm technologies Reduction of core voltage from 1.6 V to 1.3 V had little effect on SERReduction of core voltage from 1.6 V to 1.3 V had little effect on SER

Flament et al. 2004 Flament et al. 2004 experimentally evaluated the sensitivity experimentally evaluated the sensitivity of various commercial SRAMs to radiation strikes for of various commercial SRAMs to radiation strikes for different supply voltages (VDD)different supply voltages (VDD) SRAMs implemented using technologies ≥ 0.18 SRAMs implemented using technologies ≥ 0.18 m with VDD ≥ 1.5 Vm with VDD ≥ 1.5 V

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Previous WorkPrevious Work Hazucha et al. 2000 Hazucha et al. 2000 obtained an empirical model for obtained an empirical model for

estimation of SER for a 0.6 estimation of SER for a 0.6 m CMOS process as a m CMOS process as a function of the critical charge and VDD through function of the critical charge and VDD through experiments and simulationsexperiments and simulations A latch with diodes was used for SER measurements for VDD ≥ 2.2VA latch with diodes was used for SER measurements for VDD ≥ 2.2V 3D simulations of a radiation particle strike in diode were performed3D simulations of a radiation particle strike in diode were performed

The above work was conducted in The above work was conducted in olderolder technologies technologies No circuit level hardening No circuit level hardening guidelinesguidelines were proposed were proposed DSM technologies and voltage scaling exhibit DSM technologies and voltage scaling exhibit differentdifferent behavior behavior CannotCannot be used to be used to predictpredict susceptibility of DSM devices at lower susceptibility of DSM devices at lower

VDDVDD

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Simulation SetupSimulation Setup Implemented in a Implemented in a 65nm65nm bulk technology bulk technology A radiation particle strike at the drain ofA radiation particle strike at the drain of

the NMOS of INVthe NMOS of INV Simulated using Simulated using Sentaurus-DEVICESentaurus-DEVICE

Mixed-levelMixed-level device and circuit simulator device and circuit simulator

VariedVaried VDD from 0.35V to 1 V VDD from 0.35V to 1 V To simulate sub-threshold and DVS circuitsTo simulate sub-threshold and DVS circuits |V|VTT| of the PMOS transistor is 0.365V| of the PMOS transistor is 0.365V

3 different 3 different INV sizes were simulatedINV sizes were simulated 2X, 4X and 15X2X, 4X and 15X

LET of heavy ions considered are LET of heavy ions considered are 2, 10 and 202, 10 and 20 MeV-cm MeV-cm22/mg/mg To simulate low, medium and high energy particle strikesTo simulate low, medium and high energy particle strikes

Also simulated 4X INV with a radiation strike of LET = 2 & 10 MeV-cmAlso simulated 4X INV with a radiation strike of LET = 2 & 10 MeV-cm22/mg /mg (with (with different load capacitancesdifferent load capacitances) and ) and VDD = 1VVDD = 1V To analyze To analyze the effect of loading the effect of loading on the radiation susceptibility of the INVon the radiation susceptibility of the INV

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in out

INV

Cload

Set to GND

Radiation Particle

3D Device Model

SPICE Model

NMOS Device Modeling NMOS Device Modeling Constructed NMOS transistors using Constructed NMOS transistors using

Sentaurus-Structure editor toolSentaurus-Structure editor tool Gate length 35nm, TGate length 35nm, Toxox = 1.2nm = 1.2nm

spacer width = 30nmspacer width = 30nm A heavy ion strikes at the center of A heavy ion strikes at the center of

the drainthe drain

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in out1

INV

Cload

3D Device Model

SPICE Model

D S

G

Halo implants VT impantPunch through implant

Well Contact

Heavy Ion

NMOS Device CharacterizationNMOS Device Characterization

Characterized the Characterized the NMOS device using NMOS device using Sentaurus-DEVICESentaurus-DEVICE

Width = 1Width = 1mm Good MOSFET Good MOSFET

characteristicscharacteristics

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Results and DiscussionsResults and Discussions

Radiation strikes at the output of Radiation strikes at the output of 4X INV 4X INV for for VDD = 1VVDD = 1V Low energy particle is also Low energy particle is also capablecapable of producing significant voltage glitch of producing significant voltage glitch For LET = 2 the drain current looks like For LET = 2 the drain current looks like double exponentialdouble exponential

Most of the charge gets collected by drift processMost of the charge gets collected by drift process

For larger LET values, there is a For larger LET values, there is a plateauplateau Heavily doped substrates demonstrate charge collection due to both Heavily doped substrates demonstrate charge collection due to both drift and diffusion drift and diffusion

processesprocesses– in DSM processes, substrates are heavily doped– in DSM processes, substrates are heavily doped

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Results and DiscussionsResults and Discussions

O1 – O1 – Small devices collect Small devices collect lessless charge compared to large devices charge compared to large devices Reverse biased electric field is present for shorter duration in small devicesReverse biased electric field is present for shorter duration in small devices Lower drain area – less charge is collected through diffusionLower drain area – less charge is collected through diffusion

G1 – G1 – If we upsize a gate to harden it, a If we upsize a gate to harden it, a higherhigher value of value of QQcollcoll should be used should be used Extremely important for low voltage operationExtremely important for low voltage operation

O1.1 –O1.1 – For low energy strikes, For low energy strikes, QQcollcoll remains roughly remains roughly constantconstant across different gate sizes for nominal voltage operation across different gate sizes for nominal voltage operation

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1tt

NMOSDcoll dtIQ

1

))((tt

VG dtoutVVDDA

Results and DiscussionsResults and Discussions O2 – O2 – For low energy strikes, For low energy strikes,

wide devices collect almost thewide devices collect almost thesame same amount of charge acrossamount of charge acrossdifferent VDD valuesdifferent VDD values Reverse biased electric field is Reverse biased electric field is

present for a long durationpresent for a long duration Most of the charge gets collected Most of the charge gets collected

within a few picoseconds after within a few picoseconds after the strikethe strike

G2 – G2 – For SPICE simulations and circuit hardening against low energy strikes, For SPICE simulations and circuit hardening against low energy strikes, it is safe to assume that it is safe to assume that QQcollcoll remains remains constantconstant across different VDD values across different VDD values

for wide devicesfor wide devices O2.1 – O2.1 – QQcollcoll reducesreduces with decreasing VDD with decreasing VDD

At lower VDD, the electric field is At lower VDD, the electric field is weakerweaker than at higher VDD than at higher VDD At higher VDD, the PMOS device is stronger hence, reverse biased electric field At higher VDD, the PMOS device is stronger hence, reverse biased electric field

is present for a is present for a longlong duration duration

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Results and DiscussionsResults and Discussions O3 – O3 – The effect of radiation strikes The effect of radiation strikes

becomes becomes severesevere for VDD < 0.6V for VDD < 0.6V The PMOS which is primarily The PMOS which is primarily

responsible for recovery becomes responsible for recovery becomes weaker at lower VDD valuesweaker at lower VDD values

G3 – G3 – DVS should scale VDD to 2VDVS should scale VDD to 2VTT

(~60% of nominal value) (~60% of nominal value) A circuit should be hardened at the A circuit should be hardened at the

lowest operating voltagelowest operating voltage against charge collected at that voltage against charge collected at that voltage Sub-threshold circuits & circuits with VDD < 2VSub-threshold circuits & circuits with VDD < 2VTT need aggressive protection need aggressive protection

4X INV, VDD = 1V varying 4X INV, VDD = 1V varying CCloadload

O4.1 – O4.1 – For medium or high energyFor medium or high energystrikes, area of voltage glitch strikes, area of voltage glitch increasesincreases with increasing with increasing CCloadload

Voltage glitch magnitude roughly Voltage glitch magnitude roughly independent of independent of CCloadload

CCloadload ↑↑ => recovery time ↑ => recovery time ↑ Against common belief Against common belief

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Results and DiscussionsResults and Discussions O4.2 – O4.2 – For low energy strikes, For low energy strikes,

increasing increasing CCloadload improvesimproves the the

radiation tolerance of INVradiation tolerance of INV Magnitude of the voltage glitch Magnitude of the voltage glitch

reduces with increasing reduces with increasing CCloadload

Difference in magnitude is more Difference in magnitude is more for low energy strikesfor low energy strikes

PMOS has to recover a lower voltage swingPMOS has to recover a lower voltage swing

O4.3 – O4.3 – QQcollcoll increasesincreases with increasing with increasing CCloadload

G4 – G4 – CCloadload should be kept should be kept lowlow in circuits operating in high energy in circuits operating in high energy

radiation particle environmentsradiation particle environments Contrary to conventional wisdomContrary to conventional wisdom For low energy radiation environments, For low energy radiation environments, CCloadload should be kept should be kept highhigh

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Model for Charge CollectedModel for Charge Collected QQcollcoll heavily depends upon VDD, LET and gate size heavily depends upon VDD, LET and gate size

For SPICE level simulations and circuit hardening, For SPICE level simulations and circuit hardening, worst case worst case QQcoll coll is usually is usually

usedused May lead to May lead to pessimisticpessimistic designs if this approach is used for hardening DVS designs if this approach is used for hardening DVS

circuitscircuits

Need accurate models for Need accurate models for QQcollcoll to improve the accuracy of SPICE to improve the accuracy of SPICE

simulations simulations We propose one such modelWe propose one such model

KKMAX MAX ..LETLET – maximum amount of charge that can be collected. – maximum amount of charge that can be collected. KKMAXMAX is obtained is obtained

from 3D simulations at nominal VDDfrom 3D simulations at nominal VDD The second term is obtained by curve The second term is obtained by curve fittingfitting to the to the QQcollcoll obtained from 3D obtained from 3D

simulationssimulations Parameters of this model be Parameters of this model be addedadded to SPICE model cards for MOSFETs to SPICE model cards for MOSFETs

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),min( 321 LETVDDWKLETKQ QMAXMcoll

Model for Charge CollectedModel for Charge Collected Curve fitting was performed for VDD = 0.6V to 1VCurve fitting was performed for VDD = 0.6V to 1V

Applicable to circuits employing Applicable to circuits employing DVSDVS For medium and high energy particle strikes For medium and high energy particle strikes –– hardening needs to be performed hardening needs to be performed

against such particlesagainst such particles KKMAX MAX = 0.8, = 0.8, KKQQ = 16.54 fC, = 16.54 fC, 11 = 0.704, = 0.704, 22 = 0.9 and = 0.9 and 33 = 0.664 = 0.664 Avg. Error is just 6.3%Avg. Error is just 6.3%

For low energy strikes, For low energy strikes, Q Qcoll coll remains almost remains almost

constantconstant For sub-threshold For sub-threshold

circuits, it is difficult tocircuits, it is difficult tofind an accurate modelfind an accurate model Charge collection Charge collection

efficiency is very efficiency is very lowlow

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ConclusionsConclusions DVS and sub-threshold circuits are DVS and sub-threshold circuits are increasinglyincreasingly used in VLSI used in VLSI

systemssystems Important to Important to analyzeanalyze the effects of radiation particle strikes in the effects of radiation particle strikes in

these circuitsthese circuits Harden the circuits based on this analysisHarden the circuits based on this analysis

Performed 3D simulations of a radiation particle strike in an Performed 3D simulations of a radiation particle strike in an INV with DVS and for sub-threshold operationINV with DVS and for sub-threshold operation

Made several observations which are important to consider Made several observations which are important to consider during radiation hardening of these circuitsduring radiation hardening of these circuits Also proposed several guidelines for radiation hardeningAlso proposed several guidelines for radiation hardening

Proposed a Proposed a model for model for QQcollcoll to improve accuracy of SPICE to improve accuracy of SPICE

simulations – simulations – small error of 6.3%small error of 6.3%

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Thank YouThank You

Backup SlidesBackup Slides

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In DSM technologies, a In DSM technologies, a significant amount of charge is collected significant amount of charge is collected through diffusionthrough diffusion Depends upon the drain-substrate junction areaDepends upon the drain-substrate junction area

Reduce the drain-substrate junction areaReduce the drain-substrate junction area Share output diffusion nodeShare output diffusion node Not always possibleNot always possible

Split one big device into 2 smaller devices and connect them in Split one big device into 2 smaller devices and connect them in parallelparallel Place them a certain Place them a certain distance (distance (dd)) apart from each apart from each

otherother When one transistor get struck by a radiation strike, When one transistor get struck by a radiation strike,

the other collects very little charge the other collects very little charge Simulated INV of different sizes with Simulated INV of different sizes with

the NMOS transistor implemented inthe NMOS transistor implemented inthis mannerthis manner

D SG S SG D SGS SG1

D SG2

S SG1

D SG2

S SG2

D SG1

Layout GuidelinesLayout Guidelines

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D SG

D SG D SGd

D

G1 G2

S

Considered Considered vertical and angled strikes vertical and angled strikes – angled towards the – angled towards the second transistorsecond transistor

Vertical strike is the worst case strike for a single deviceVertical strike is the worst case strike for a single device QQcollcoll can be reduced by can be reduced by up to 14.5%up to 14.5%

If If dd is small (< 2 is small (< 2 m) then m) then QQcollcoll is higher for angled strikes compared is higher for angled strikes compared

to vertical strikes (not shown) – to vertical strikes (not shown) – use single deviceuse single device

Vertical Strike 45o Angled Strike

SingleDevice

d (m) % Redd = 4.2

SingleDevice

d (m) % Redd = 4.2

2.1 4.2 2.1 4.24X LET=10 33.2 30.1 30.0 9.75 29.6 30.1 27.9 5.74

4X LET=20 45.8 39.3 39.2 14.43 42.3 42.1 37.1 12.29

8X LET=10 53.7 48.9 48.5 9.65 45.7 47.2 43.5 4.81

8X LET=20 78.1 67.7 67.5 13.56 69.4 71.5 62.6 9.80

15X LET=10 70.7 60.9 60.3 14.72 54.6 58.7 53.1 2.75

15X LET=20 123.7 109.5 108.7 12.12 103.2 109.6 96.5 6.49

Layout GuidelinesLayout Guidelines

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Standard Cell Layout GuidelinesStandard Cell Layout Guidelines Preference 1 Preference 1 –– Reduce the output diffusion area by sharing if Reduce the output diffusion area by sharing if

possiblepossible Not applicable to devices connected in parallelNot applicable to devices connected in parallel

Preference 2Preference 2 –– Split devices, separate them Split devices, separate them by by dd ≥ 4 ≥ 4 mm and connect them in parallel and connect them in parallel

For a 65 nm n-well processFor a 65 nm n-well process PMOS devices collect less charge compared to PMOS devices collect less charge compared to

NMOS devices because NMOS devices because of lower collection of lower collection volumevolume

NMOS need to be NMOS need to be separated from separated from each other by ≥ 4 each other by ≥ 4 mm

This helps reduce This helps reduce QQcollcoll by 10-14% by 10-14%

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N Device

P Device

n-well

N Device

P Devicen-well

VSS

VDD

VSS

N Device

P Device

n-well

2.6 m

VDD

VSS