3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications

Darryl Kostka*, Taigon Song#, Sung Kyu Lim# * CST of America # School of Electrical and Computer Engineering

1400 Fashion Island Blvd., suite 300, San Mateo, CA 94404 Georgia Institute of Technology, Atlanta, GA 30332 darryl.kostka@cst.com taigon.song@gatech.edu, limsk@ece.gatech.edu

Abstract 3D IC based systems necessitate a chip-package co-design

approach since the TSV response in the chip stack can propagate into the package. In this work, we demonstrate a chip-interposer co-analysis methodology that includes the 3D CAD model of the 3D IC and compare this to the conventional analysis techniques. Our findings demonstrate that the coupling between signal TSV’s in the chip stack has a significant impact on the overall channel response and needs to be carefully modeled in order to obtain accurate results.

Background Over the past decade, the trend in the consumer electronics

industry has been to develop high performance multi-functional products with a compact size and reduced cost. Modern systems demand new technologies that can integrate RF, analog, digital and sensor functionalities while maintaining minimal interference among different systems. Multi-functional integration can be achieved by stacking multiple chips vertically (3D IC). 3D ICs promise more than Moore integration by packing many functions into a small form factor. To implement 3D IC technology, requires chip to chip interposers as well as through silicon vias (TSVs) [1]-[6].

For 3D IC technology, a chip-package co-design approach is necessary since the TSV response in the chip stack can propagate into the package. With respect to 3D ICs which are stacked using TSVs, crosstalk is a major concern especially in the case of dense TSV arrays, not only in signal nets, but also in the power delivery network (PDN) as well. It has been demonstrated that the crosstalk waveform exhibits a distinct RC behavior leading to a slow decay of the coupled waveform, which is unique to TSVs [1]-[2]. This RC effect can be quite detrimental since it can create inter symbol interference (ISI). Memory interfaces also require a co-design approach. These interfaces are currently designed to support single-ended data rates in the 1GHz-plus range, and serial links are running upwards of 10 Gb/s. This necessitates a precise design analysis and rules-based control of each of these signals at the die, package and PCB levels. However when chip, package and board power delivery components are designed separately, there is no opportunity to optimize the global PDN and once these are connected together, this could produce unexpected results.

In this work, we demonstrate a chip-package co-analysis methodology that includes the 3D CAD model of the 3D IC and compare this to the conventional analysis approach which is to represent the IC using either IBIS or SPICE equivalent models. To demonstrate the co-design methodology, we consider two realistic test cases for mobile applications in this work. The first is composed of a 2.5D silicon interposer

platform for multi-chip integration which consists of a high-speed chip-to-chip channel which is routed through the silicon interposer. Neighboring high-speed signal nets along with the complete PDN at the chip and interposer levels are all included in the model. The second test case is similar to first in that the chips are now 3-tier IC stacks which are mounted directly on the interposer.

Using actual benchmarks based on the 45nm digital CMOS technology library, we design complete test chips. Then we import the complete chip-to-chip channel models into a commercial 3D full-wave electromagnetic (EM) simulation tool which is used to calculate the eye diagrams along with the S-parameter channel response up to 20GHz. We compute and compare crosstalk to neighboring signal nets, and this will be used to study ISI and simultaneous switching noise (SSN) effects. Next, we monitor the propagation of the coupled noise through 3D field plots and the coupling effects between the IC and the interposer/package along with other return path discontinuity (RPD) effects.

We show that the silicon interposer test structure demonstrates significantly more pronounced coupling effects due to the semiconducting nature of the silicon substrate. This further necessitates the proposed chip-interposer-board co-design methodology. Finally, we compare our co-simulation results to the results of a common practice where the chip and interposer/package components are first decoupled and analyzed separately and then cascaded in order to obtain the overall channel response. From the comparison we demonstrate that the cascading analysis, if not performed carefully, may not capture the critical coupling mechanisms and therefore produces inaccurate results.

TSV Array Crosstalk Modeling The electromagnetic (EM) simulation of TSVs is a

challenging task due to multiple reasons. First, the dimensions involved are multi-scale with a high aspect ratio mainly due to the thin oxide liner which needs to be modeled. The EM wave propagation behavior is complex due to the lossy semiconducting substrate which is exacerbated in the presence of dense TSV arrays. Also although it is not accounted for in this work, the biasing of the silicon substrate can also change the TSV capacitance due to Metal-Oxide-Semiconductor capacitance behavior [1]-[2]. Therefore special care is required when building simulation models in order to ensure accurate results.

A microstrip line on a semiconductor substrate (Si) separated by an oxide layer (SiO2) supports three fundamental modes of propagation namely, slow-wave, quasi-TEM and skin-effect modes [7]. The TSV structure has a metal-SiO2-Si interface and therefore a similar set of propagating modes is

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expected. Factors including the frequency of operation, SiO2 layer thickness, Si substrate thickness and conductivity determine the mode spacing [7].

To study the complex EM wave propagation we first consider a simple signal and ground (return) TSV pair geometry as shown in Fig. 1. The model was built and simulated using a 3D EM full-wave tool [8] based on the following physical dimensions and material properties: D=100μm, R=15μm, L=100μm, dox=0.1μm, εSiO2=3.9, εSi=11.9, σSi=10S/m.

Figure 1. TSV signal-ground (SG) pair.

The simulated single-ended insertion loss for the SG TSV

pair is shown in Fig. 2. A sharp slope can be observed up to around 0.5GHz due to the transition from the slow wave to the quasi-TEM mode [5]. Above 0.5GHz, the slop of the curve decreases indicating that the displacement currents in the silicon substrate begin to contribute towards the loss.

Figure 2. Single-ended insertion loss response for SG

TSV pair.

An important effect that deserves special attention is the coupling between TSVs. For this analysis we consider the example of a 5x5 array of TSV’s as shown in Fig. 3. This mainly consists of an aggressor via along with neighboring victim vias and another victim via at the centre of the array which is shielded by a ring of return vias. The baseline TSV dimensions are as shown. A pulse with a risetime of 100ps and amplitude 2V is propagated through TSV1 using a 50Ωsource resistor. The far end of TSV1 and both sides of all other signal TSVs are terminated in 50Ω.

Figure 3. 5x5 TSV array.

From the results plotted in Figure 4(a) we can observe that

the oxide thickness plays a large role in increasing coupling in the transition region of the TSV. A larger oxide thickness would therefore help in reducing cross talk for low resistivity substrates. The high resistivity substrate acts as a low loss dielectric, which is desired.

If we look at the crosstalk waveforms in the time domain as shown in Figure 4(b), the 10S/m conductivity silicon substrate leads to a much larger peak voltage as compared to the 0.01S/m conductivity silicon substrate. Moreover, the low resistivity substrate results in a waveform that has a longer coupled noise duration, which can be a significant problem as it can create inter symbol interference (ISI).

(a)

(b)

Figure 4. Crosstalk waveforms for 5x5 TSV array in the (a) frequency domain (b) time domain.

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Return Path Discontinuity Modeling This section presents the modeling and simulation of

Silicon and glass (BSG) TPVs connected with redistribution layer (RDL) wiring on the interposer. The RDL wiring is modeled as microstrip lines on the top and bottom surfaces of the interposer. These lines are connected by TPVs as shown in Fig. 5. The microstrip lines on the top surface of the interposer are excited using discrete ports which are referenced to the adjacent ground plane. The various dimensions of the model which is based on the geometry are outlined in Fig. 5. A low resistivity Silicon interposer and BSG glass interposer are considered for the analysis. Additionally, a ZIF polymer with a relative permittivity of 6.7 and a loss tangent of 0.006, is used for lamination purposes as a build-up dielectric layer (between the metal planes and microstrip lines) as well as the via liner. A 1μm thick polymer liner is considered and the via radius is set as 30μm.

Figure 5. Double-sided interposer with microstrip-to-

microstrip signal transition.

Two simulations are performed using the model shown in Fig. 5. The first considers a Silicon interposer and the second replaces this layer with a glass interposer. The other layers in the stackup remain constant. A comparison between the insertion loss results for these two cases is presented in Fig. 6. The microstrip-to-microstrip transition results in a change in the reference plane thereby creating a return path discontinuity (RPD). This can result in a large simultaneous switching noise (SSN) voltage being induced between the planes at power plane resonant frequencies. This in turn translates to an increase in the insertion loss of the signal. From Fig. 6 sharp resonances in the insertion loss plot for the glass interposer case can be observed. These dips coincide with the power plane resonant frequencies. The surface current distribution within the power/ground plane pair at one of these power plane resonant frequencies is plotted in Fig. 7 clearly showing the development of plane resonances within the cavity. In the silicon interposer case, the high substrate losses suppress these power plane resonances and the result is a smooth insertion loss profile. Therefore although the silicon interposer results in higher overall insertion loss, it could lead to superior signal integrity and EMI performance compared to using glass interposers. Therefore it is difficult to access which technology will lead to improved electrical performance without having a clear understanding of the complete design.

Figure 6. Single-ended insertion loss for double-sided

interposer signal transition.

Figure 7. Surface current distribution at 20GHz showing

cavity resonance mode.

(a)

(b)

Figure 8. Eye diagram plots considering a 3.2 Gbps 210-1 PRBS stream for (a) glass interposer, (b) silicon interposer.

Chip-Interposer Co-analysis: 2.5D Link Example For 3D IC technology, a chip-package co-design approach

is necessary since the TSV response in the chip stack can propagate into the package. This is because in 3D ICs which are stacked using TSVs, crosstalk is a major concern especially in the case of dense TSV arrays, not only with respect to signal nets, but also in the power delivery network (PDN) as well. In this section we take a look at chip-interposer co-analysis methodologies and offer insights into the various tradeoffs involved.

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The example that is used for the study is that of a 2.5D integration based link as shown in Fig. 9 which consists of two die connected through a double-sided Silicon interposer. In order to simplify the analysis, only a few signal I/O along with the complete PDN details have been included in the die models. It was found that this basic level of detail was sufficient to validate the co-design methodologies and these findings can be extended to more realistic models as well. The IC design is based on the NCSU FreePDK 45nm technology library which features 10 metal layers and a 12um Cu backend. Cadence Virtuoso was used to generate the IC layout which was then imported into the 3D EM tool using a GDSII interface.

Figure 9. 2.5D integration link between two die using a

double-sided silicon interposer. The I/O pad map used is shown in Fig. 10. It should be

mentioned that both IC’s which are 1mm x 1mm in size, are identical to each other and share the same I/O pad map. It can be observed that 11 signals are considered in total including a combination of single-ended and differential signaling in addition to the power (VDD) and ground (VSS) reference layers. The different features of the resulting 3D die model are highlighted in Fig. 11.

Figure 10. I/O pad map considered for Die 1 and Die 2.

(a)

(b)

(c)

Figure 11. Simplified IC layout used for the analysis showing (a) top, (b) bottom and (c) cross-sectional views.

Next, the details of the interposer model are presented in

this section. As mentioned earlier, a double-sided Silicon interposer identical to the one shown in Fig. 5 is considered in this study. The total interposer dimensions are 40mm x 40mm and the two die are placed at a distance of 20mm from each other. The die are connected to the interposer pads by means of micro-bumps with a diameter of 36um and a pitch of 200um. Four signal nets are considered in this analysis which includes one differential pair and two single ended nets. Referring back the I/O pad map in Fig. 10, these nets are DIFF1+ and DIFF1-, SIG1 and SIG2 respectively. The TPVs which provide the connectivity within the interposer have a diameter of 12um and a 0.5um oxide liner thickness is considered. The various features of the 2.5D chip to chip link are highlighted in Fig. 12.

(a)

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(b)

(c)

Figure 12. 2.5D chip to chip link model (a) top view, (b) side view and (c) highlighting signal nets of interest.

Having described the channel model that needs to be

analyzed, this section will go over the various co-design methodologies considered in this study. The first method which is the most intuitive is to simulate the complete channel using the 3D full-wave EM tool. This method minimizes the number of assumptions that are made and provides the most accurate solution. However, in most practical designs, it is not feasible to simulate the complete channel using a 3D full-wave approach. This is mainly because of the extremely high aspect ratio and geometry complexity involved that leads to a very high mesh density which in turn drastically increases the computation requirements.

The next approach is based on the methodology presented in [9]. The reader is encouraged to review the cited reference for more in-depth information on the methodology. The main idea is to simplify the analysis by decoupling the die from the interposer by introducing an electric wall boundary which serves as a virtual reference plane for signal nets. By adopting this methodology, the most efficient solver technology can be used for the individual models thereby allowing for more complex designs to be analyzed. The first step in this approach is to identify the location to introduce the electric wall boundary condition. For this particular model, the most natural location is along the mid plane of the micro-bump array as shown in Fig. 13(a). Therefore accordingly, the individual micro-bumps were sliced into two halves and this resulted in three separate models being generated from the original channel model which includes two die models and one interposer model as shown in Fig. 13(b) and Fig. 13(c) respectively. In order to maintain return current continuity, discrete ports are then introduced for all signal, power and ground pins at the micro-bump location and these were referenced to a floating PEC sheet that serves as the electrical wall boundary condition as shown. Solving these three models yields three corresponding sets of S-parameter data which can then be cascaded in order to obtain the overall channel response as shown in Fig. 14.

(a)

(b)

(c)

Figure 13. Segmentation methodology for 2.5D chip to chip link model highlighting the location of the electric wall

boundary and the resulting (b) decoupled chip model, (c) decoupled interposer model.

Figure 14. Equivalent channel model using decoupled S-

parameter data for die and interposer.

The main drawback of the previously described methodology is the large number of discrete ports which need to be created for all nets including signal, power and ground nets. This might not be feasible for practical designs and also could prove prohibitive for certain EM simulation techniques. Therefore as a slightly alternative approach, discrete ports were only created for the signal nets of interest for this study and the surrounding ground micro-bumps were simply shorted to the floating PEC reference.

Fig. 15 shows the port naming convention that was used for the analysis. The discrete S-parameter ports were essentially placed between the signal pad and the nearest ground (VSS) pad. The comparative results of the 3D full-wave EM analysis by applying each of the previously discussed methodologies are provided in Fig.16. The single-ended insertion loss, return loss, near-end crosstalk and far-end crosstalk responses are compared using the three methodologies described previously and in general, good correlation can be observed over the complete frequency range of interest. Some discrepancies in the results can be seen for the case where the ground micro-bumps were shorted to the virtual reference but the degree of correlation is considered acceptable for this study. However, in order to determine the cause of these discrepancies, we can refer to the

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surface current distribution plots shown in Fig. 17 (a) and Fig. 17 (b) which are generated at 100MHz and 2GHz respectively. We can see that there is a significant amount of coupling between the excited signal net and non-neighboring nets within the IC and that the return currents spread over the entire power and ground mesh plane layers. These effects become more pronounced at higher frequencies. Therefore it is important to model the return current path correctly as failing to do so can neglect key coupling effects which may lead to large levels of discrepancy at higher frequencies.

Figure 15. Port placement and naming convention for 3D EM analysis of chip to chip link.

(a)

(b)

(c)

(d)

Figure 16. S-parameter results for 2.5D chip to chip link (a) IL, (b) RL, (c) NEXT, (d) FEXT.

(a)

(b)

Figure 17. Surface current distribution for the IC generated at (a) 100MHz, (b) 2GHz.

Chip-Interposer Co-design: 3D Die Stacking Example

In this section we modify the previous chip to chip 2.5D link test case to include 3D stacked ICs (3 tiers) where TSVs provide the connectivity between the different ICs. The modified model is illustrated in Fig. 18. Here, the top IC (tier 3) contains the signal I/Os and the PDN is distributed between the middle and bottom IC’s (tiers 2 and 1). The micro-bumps in this design have a diameter of 36um with a pitch of 200um. The TSV’s are 50um in length and have a diameter of 12um with an oxide liner thickness of 0.5um.

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Figure 18. Chip to chip link model including 3D stacked ICs

connected using a double-sided silicon interposer.

Based on the previously described segmentation methodology [9], there are multiple possible locations in the design where an electric wall boundary can be introduced as indicated in Fig. 18. This provides a three different ways of analyzing the link model using the EM simulation tool. The first method, referred to Method A is simply running the analysis for the complete 3D model. The other two methods referred to a methods B and C are explained through Fig. 19 and depend on where the electric wall boundary is introduced.

(a)

(b)

Figure 19. Segmentation methodologies for 3D IC chip to chip link (a) Method B, (b) Method C.

The comparative results of the 3D full-wave EM analysis

by applying each of three above mentioned methodologies are provided in Fig. 20. The single-ended insertion loss, return loss, near-end crosstalk and far-end crosstalk responses are shown and in general good correlation can be observed between methods B and C especially at lower frequencies whereas some discrepancies can be seen at higher frequencies. The results from both methods however do not correlate well with those from method A and this is especially true in the case of near-end and far-end crosstalk.

(a)

(b)

(c)

(d)

Figure 20. S-parameter results for 3D-IC chip to chip link (a) IL, (b) RL, (c) NEXT, (d) FEXT.

From the above results it can be inferred that the coupling

between TSV’s in the 3D IC stack have a significant impact on the overall channel crosstalk result. Therefore decoupling the link model might result in inaccurate results. In general it can be seen that the crosstalk is overestimated in the decoupled model. It can also be seen that if the segmentation/decoupling is applied correctly, fairly good broadband correlation can be achieved in terms of both the insertion loss and return loss.

Conclusions This paper demonstrates the importance of TSV crosstalk

modeling for 3D IC applications. Return path discontinuity effects are also modeled at the interposer level and it is shown that this can degrade the overall signal integrity performance. Finally, two chip to chip link examples are used to illustrate different chip/interposer co-analysis methodologies and the drawbacks of the various approaches are discussed.

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