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9/24/2009
1
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3D Stacking: EDA Challenges &
Opportunities
SEMATECH Symposium
Tokyo, Japan
September 2009
Rajiv Maheshwary
Senior Director
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Why 3D IC Design?
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Packaging Technology EvolutionAll these technologies will co-exist
Lo
wM
ed
ium
Hig
h
Low Medium High
Functionality
Den
sity
1990’s
2000’s
2010’s
*Source: Yole Development, 2008
Vertical stack Lateral stack
4
3D IC Market Drivers & OpportunityDesign ChallengeDriving Issue Case for 3D (TSV)
Performance/power(Memory Bandwidth
for Multi-media) 1 1.2 1.5
3.9 4.2
9.3 9.7
0
2
4
6
8
10
12Memory Bandwidth Requirement
Dual Core
Quad Core
+ I/O density 100X 2D
*Source: IBS, Major IDM, 2008
More IP Reuse(Time to market, cost)
Mixed Technology(Heterogeneous
Integration) 45-nm130-nm
Miniaturization(Form factor, cost)
More Moore(2.5X higher costs
per process node)
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3D IC TSV Applications
Source: Micron Technology
2008: CMOS Image Sensors
2010: High-density Flash, DRAM
2011-2: Logic + memory
2014: Multi-level 3D SiP’sSource: International Solid-State
Circuits Conference, February 2009
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Requirements for
Market Success
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9
Slide Intentionally
Left Blank For
Handout Purposes
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Test
Requirements for 3D (TSV) IC Market Success
TSV process& Wafer Thinning
Yield
Die Stacking
& Packaging
Design & Methodology
3D ICElements
3D Definition
Eco-System & Standards
Cost
Efficiency
Test
Automation
IDM/
Foundry
OSAT* EDA
EDA
*Outsourced Semi Assembly & Test
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Generic EDA Solution To Enable 3D IC Design
Die 2: Digital
Die 1: Digital Die RF
Passive (Active) Interposer
Package
Multi die planner
Abstraction/Dynamic
Link
Abstraction/Dynamic
LinkIC-Package Interface
Digital RF/AMS Package
Electrical
Analysis
Thermal
Analysis
Netlist
manager
Source: STM, DAC 2009
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Enabling 3D (TSV)
IC Design with EDA
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DRC/LVS
Model(.lib)
Parasitic
Extraction
DR
C/L
VS
Deck
Inte
rco
nn
ect
Mo
de
ling
TS
V
Mo
de
ling
• TSV stress/
reliability analysis
• Special rules TSV
• Interconnect
technology data
Foundry(Tech Files)
3D (TSV) IC Design Flow Vision
Die (Stack)
Partitioning
Synthesis &
DFT
Physical
Design
Extraction
•System level
design exploration
• Logic partitioning
• TSV connectivity
checking w/JTAG
• Test methods
• Multi-die bump &
TSV floorplan
• Auto TSV P&R
• IC-Package I/F
• TSV aware timing,
IR-Drop, EM
analysis
• Thermal analysis
• TSV aware
physical
verification
EDA Design Methodology
Tim
ing
/Po
we
r A
na
lysis
• Extract TSV,
u-bump, backside
RDL metal
Physical
Verification
Stack
Sign-off
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TSV Induced Stress and Reliability
Through Silicon Via
Interconnects
Transistors
Bumps to connect
to the package
Interconnects
Die 1
Die 2
(thin)TSV
m-bump
Typical Back-to-Front TSV Stack
Die 1
Die 2
(thin) TSV
Transistor is
being squeezed
or stretched
by adjacent TSVs
m-bump
The amount of proximity
effects depend on
geometry shape,
location, and orientation
Material deformation
leads to mobility change
Stress affects transistor
performance
Die 1
TSVTSV squeezes
or stretches
adjacent
interconnects
Die 2
(thin)
m-bump
Stress affects BEoL
reliability
De-bonding and
De-lamination
could occur under
additional stress
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3D IC Stress/Reliability Analysis Solution
Die Thinning
t=400um
t=200um
t=100um
t=20um
Compressive film stress
Von Mises Effective Stress (MPa)
TSV
001 Wafer, 110 Orientation
Effective Stress
Submodel 1
Submodel 2
Submodel 3
Global Model Multi-scale Modeling Reliability Analysis
Performance VariationStress HotspotsWafer Warpage
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3D IC Test Strategies
• Challenge– Stack testing (efficiency &
low cost)
– Low pin count test
• Solution– Test one die at a time with
isolation logic (core or boundary)
– 1000X test compression at very low pin cost
– Inter-die testing methodology
– Use/extend IEEE 1149.1 and 1500 test standards
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Today’s Flip Chip Flow
3D IC Physical Design Challenges
Chip connections
“re-distributed”
from pads to
bumps
Re-Distribution
Layer (RDL)
routing is on
upper-most layer
Bumps (solder balls)
are placed overlaying
the complete chip
Bump
cell
RDL
route
IO
pad
Substrate
Package
Chip
Bump3D IC
• Represent TSV & backside
metal in technology file
• Automatic P&R
• Support multiple chips
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TSV, IO and Bump Placement & Routing
TSV’s
Bumps/Lands
TSV’s connected
to I/O
Placement
Blockages
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3D IC Extraction Challenges
Substrate
Package
Chip
Bump
• Single-sided substrate
• Includes extraction of routing
& RDL layers
• Parasitic netlist represents a
single die
Today 3D IC
• Parasitic effects of TSV, u-bump,
bonding layer, interposer routing
• Support of multiple chips
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3D IC Extraction Solution: Stacked Die
• “2D” extraction for Chip 1
• “3D” extraction for Chip 2 with TSV and backside routing
• Generate single spice netlist with parasitics for top, TSV and
back metal layers
Chip 2
Chip 1
Interconnect Technology File
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3D IC Thermal Considerations
• Challenge– Multiple heat sources (stack)
– Substrate thinning yields poor heat dissipation per die (2D)
– Elevated thermal gradient in 3D
• Implications– Reliability
– Timing
Peak temperature
is 15% higher
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3D IC Thermal Solutions
• Accurate thermal
modeling & analysis
• Thermal-aware
physical design– 5% increase in wire-length
@ 2D peak temperature
• Thermal TSV’s
1
2
3
4
5
Heat sources
(distributed)
White space
used for
Thermal Vias
Thermally Optimized Floor-plan
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• 3D IC Market Drivers
– Cost, Performance/Power
– Heterogeneous integration
• Customers expected to have
production devices starting 2011
– Logic + DRAM and Logic + Logic
– $20B* TSV devices by 2013
• Synopsys Focus
– Enable design flow with partners
– Lead definition of emerging
interoperability standards
Summary
Source: Gartner Semiconductor Industry Briefing, June 2009
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