3.5.2 Front end electronics3.5.2.1 General considerations

According to the physics design, The BESIII detector will mainly be composed of five subdetectors which are Central Trigger chamber (CT), Main Drift Chamber(MDC), Time-Of-Flight plus Cherenkov Correlated Timing counter (TOF+CCT), Electromagnetic Calorimeter(EMC, Barrel and End), Muon Counter(MC, Barrel and End). All information of the physics processes that the experiment studies are carried in the output signals of these subdetectors. The purpose of each subdetector is different so is the design requiremen, and they are relatively independent to others. Correspondingly, the BESIII electronics will also be in five subsystems with the common functions of signal amplification and formation, amplitude and time information extraction, digitization, and subevent packing. The subevent data will be merged together to form the event data which then be transferred to on-line farm via switch network for further processing. Finally the data will be recorded on tapes for offline physics analysis. The main technical specifications for each electronics subsystem are listed in the table 3.5.2.1-1.

Table 3.5.2.1-1 Required specifications for BESIII electronics

Note: the figures marked with sign “※” in above table are estimated value. As shown in table 3.5.2.1-1, the main tasks for BESIII electronics can be

Itemnumber ofChannels

time measurements Charge measurements Count rate/ per channel

Infor- mation totriggerrange number

Of ch. σt Range numberOf ch. σQ

CT 300 0.22fc onaverage 300 20% at

0.22fc 20k hit

MDC 6000 500ns 6000 0.5ns 10 fc –1500fc 6000 4 fc 100k hit

TOF+CCT

160(TOF)160(CCT)

60ns320×2(doublethreshold)

25ps2Vmaxfor TOF,0.2Vmaxfor CCT

3202%at 2vforTOF, at o.2vfor CCT

hit overhigh vth of TOF

EMC(Br.) 22000 4 fc –

300 fc 22000 0.2 fc 1k sum ofanalog

EMC(End) 800 60ns 800 25ps 0.2vmax 800 0.5%

at 0.2v 1k sum ofanalog

Muon(Br.) 20000※ hit measurements hit

Muon(End) 20000※ hit measurements hit

Total electronics channel 76,860

1

summarized as following:① To measure the time information carried by detector signal, with a time resolution 0.5ns for MDC, 25ps for <TOF+CCT > and End EMC.② To measure the charge carried by detector signals( the signal’s amplitude).③ To extract the trajectory position(x, y) information in detector. ④ To provide the hit information and the sum of analog signals for trigger

system.

The total number of electronics channels is about 77K which is 3 times more than that of BESII electronics.

Compared with BESII, the BESIII electronics confronts with many technical challenges. The main reasons are:

① BEPCII machine will run with multi-bunch in the storage ring with a bunch spacing of 8ns. The electronics system must adopt a very new design strategy to acquire the information from detector signals.

② The luminosity of BEPCII will reach 1×1033cm-2s-1 which is 2 order of magnitude higher than BEPCI. This means the data amount to be acquired and processed by BESIII electronics, is greatly larger than BESII, the speed for data processing must be much faster.

③ The e- and e+ beam intensity of BEPCII will each reach 1100ma, which is 40-50 times that of BEPCI, and the beam lifetime is only half of that of BEPCI, so the background signals in BESIII electronics will be much more than that in BESII . The signal rate for inner detector, especially for the MDC will be much higher.

Considering the above factors, the design of BESIII electronics will take the

following technical strategies: ① The pipeline technique will be used to make sure any interesting event will

not be lost during trigger decision.② Multi-stage parallel processing technique will be adopted to make the system

dead time very small. ③ The front-end cards/digitization modules will be located as close as possible

to the detector to shorten the length of analog cables. The digitized data will be transferred to the counting room via a few optical fibers.

④ Much effective technical measures must be taken to make the system to be immune from any possible RF interference.

⑤ The modules with the same functionality in different subsystems will take

2

same design specifications to make these modules interchangable among the subsystems. By this way, the cost can be dropped down, and the future maintenance will be easy.

⑥ The VMEbus, widely used by the HEP experiments in the world, will be adopted as the system bus standard. The PowerPC will be used as the communication interface with online farm.

Based on the considerations mentioned above, a simplified block diagram of BESIII electronics system is shown in Fig. 3.5.2.1-1.

3.5.2.2 Main Drift chamber electronicsThe main tasks for the MDC electronics are:① To measure the drift time of ionized electrons towards the sense wires, so that

3

Preamp

Preamp

Preamp

Preamp Trigger

Others

VC

On-line Farm

mainamp

Trigger

Splitter

Trigger

Splitter

Sum ofanalog

Trigger

Analog sum to Trigger

Muon

EMC

TOF+CCT

MDC

mainamp

Fig. 3.5.2.1-1 BESIII electronics block diagram

Switch netw

ork

ReadoutCharge extractionCharge pipeline

ReadoutCharge extractionCharge pipeline

ReadoutCharge extractionCharge pipeline

ReadoutCharge extractionCharge pipeline

ReadoutCharge extractionCharge pipeline

ReadoutTime extractionTime pipeline

ReadoutTime extractionTime pipeline

ReadoutTime extractionTime pipeline

determine the spatial trajectory of particles flying through the chamber. The main design specifications are as follows:

Time range to be measured: 0-500nsTime resolution σt: ≤0.5ns (the timing error is not taken into account here).② To measure the charge deposition on a sense wire, so that calculate the

particle’s energy loss dE/dX in the chamber. The following specifications are required for the charge measurement:

Charge range to be measured: 10-1500 fcCharge resolution σQ: 4 fc ③ To provide the sense wire hit information to the trigger system.With consideration of above requirements, the MDC electronics is designed to

consists of 6 sections which are the preamplifier, main amplifier, charge measurement circuitry, time measurement circuitry, calibration and logic control circuitry. The system block diagram is shown in Fig. 3.5.2.2-1.

⑴ PreamplifierAs it is well known, the particle’s energy losses in the chamber obey the landau

distribution. The signal size in the low energy end of the distribution is very small, so the signals from sense wires must be amplified properly to make them suitable for further processing by subsequent circuitry. The following points in designing the preamplifier will be taken:

① A transimpedance type preamplifier will be designed, to preserve the time information carried by the signal’s rising edge.

② To reduce the noise level, the input impedance of preamplifier, which matches

4

Clk

farm

online

Preamp

farm

From TriggerTo Trigger

Start

Wire

Stop

Clock

trig

trig

dE/dX

timing

Vth

Logic control

Chargemeasurement

Fig. 3.5.2.2-1 Simplified block diagram of Main Drift Chamber electronics

Time measurement

Readoutmodule

Readoutmodule

Calibration

Mainamp

the characteristic impedance of sense wire, will be designed with so called “cold termination” technique. The preamplifier card will be directly mounted on the endplate of chamber.

③ The power dissipation should be controlled no more than 50mw/per channel, so that no any auxiliary cooling measures is needed.

④ The preamplifier will be designed and fabricated as a hybrid IC chip. Each chip consists 4 or 6 channels depending on the arrangement of chamber feedthrough. The signal wire layers of MDC, especially inner signal wire layers, are very close to the collision point. Therefore it is very important to design the preamplifier with low noise methodology. ⑵ Main amplifier The main task and basic design requirements for main amplifier are: ① To split the signal from preamplifier into two branches, one for charge measurement, another for time measurement.

② The signal in charge branch feeds to a RC filter and shaper to smooth the waveform suitable for the FADC sampling. According to a rough estimation, the hit rate of inner signal wire will be as high as 100k/s. To avoid the signal pile up, the shaping width will be controlled not more than 600ns. In this case, the probability for signal pile up can basically be negligible.

③ The signal in time branch is sent to a fast discriminator with a low threshold voltage to deliver a timing pulse, whose leading edge corresponds to the drift time. The timing error caused by time walk will be corrected using corresponding charge value in offline processing.

④ If some cells in the chamber are fired, a hit signal will be produced and sent to trigger system for trigger processing. Fig. 3.5.2.2-2 is a simplified block diagram of the main amplifier.

The main amplifier can be designed as a VME module. 32 channels per module

5

Timing

Trigger

dE/dXA3

A4

A2

A1

Vth

Filter &shaping

Discriminator

Fig. 3.5.2.2-2 Simplified block diagram of main amplifier

should be possible.

⑶ Charge measurement As mentioned above, the hit rate for inner layer wires is very high(100k/s), hence the charge measurement will take the digital pipeline scheme based on Flash ADC(FADC). The charge value carried by wire signal can then simply be extracted by numerical integration. According to the requirement for measurement precision, a FADC with 10 bit resolution and 40 MHz sampling rate will be used. The sampling clock will be synchronized with the collision bunch.

The Fig. 3.5.2.2-3 shows the simplified block diagram for charge measurement. In the diagram, the analog processing circuitry receives the dE/dX signal from main amplifier, then some necessary processing such as gain adjustment, DC level shift, signal driving and the high frequency noise filtering will be performed here to make the signal match the input characteristic of FADC chip. The FADC digitizes the signal with 40MHz rate, the digitized data will be written into a digital pipeline with the same clock. The pipeline is made of a circular dual port memory (DPM). The length of DPM should be greater than the trigger latency. With the trigger latency equal to 2.4us, an 8bit depth DPM would be enough. A clock counter provides the write address for the DPM. The read clock for DPM is the same as the write. A subtracter (a block marked with “-“ in the diagram) provides the read address for the DPM. Normally the read clock input of the DPM is open, therefore the data in the DPM will not be readout in spite of where the read pointer points to. In this case, the old data in the cells of DPM will be overwritten by new one circularly. The subtracter has two inputs, one receives the output of clock counter, another is connected to a constant value “trigger latency”. The output of the subtracter, i.e., the difference between the output of clock counter and trigger latency will be used as the read address for the DPM.

When the trigger L-1 is active, its leading edge will immediately start the following procedures:

① To ask the subtracter to subtract the trigger latency from the current output of the clock counter, the difference value is used as the read address for the DPM. It is obviously that the read address at this moment is just the write address when an interesting event was produced at the moment t = t. The digitized data related to this event in a channel must be stored in the cells starting from the current read address. The number M of these cells possibly occupied by these data should be “maximum drift time + signal width”.

6

② To ask the processing logic circuitry to close the switch (sw) immediately, the read clock will be active from this moment. The data starting from the t = t then will be readout from DPM to the buffer1 one by one. After reading for M times, all data related to the current event in this channel will have been transferred from DPM to buffer1.

③ To make the trigger no. counter to increase its output value with 1. The resultant output will be the current trigger number. This trigger number should be readable out by VME. Also this counter should be resetable by VME and other external source, say the trigger circuitry.

④ With a proper delay, to save the current content of the trigger no. counter into a trigger no. register.

After receiving a trigger number, the trigger no. register will set a flag bit ID to be equal to “1” immediately. Normally the processing logic circuitry always checks the ID bit. Once ID=”1” is found, the processing logic will read out a batch of data correspond to the current trigger number from the Buffer1, and then make a numerical integration over them to get the charge value, and finally compare this value with a threshold stored in a RAM. If the charge value is greater than the threshold, the processing logic will assemble the charge value with the trigger number, and then put it into the buffer2, waiting being read out by VME.

In each module, there is a global buffer(G_buf), which is used to keep so called “hit map” words. The length of each hit map word is 32 bits, and each bit represents a

7

Fig. 3.5.2.2-3 Block diagram of FADC module for charge measurement

Add

W

G_buf

GlobalFPGA

ID

Buffer2

ckReset (from Trigger)

ck

ck

Reset

SW

12

Add

R

FPGA

Vin

VM

Ebus

w R

Trigger active

Buffer1Pipeline

Clockclock

Analogprocessing

FADCCircular DPM FIFO

ClockCounter

——

triglatency

Processing Logic

Trigger No. counter

Trigger no. registerdelay

RAM

FIFO

FIFO

channel in the module. If the charge value in a channel is greater than threshold, the corresponding bit in the hit map word will be set to “1”, otherwise to “0”. When VME starts a read cycle, it will first read the hit map, from which the VME will know which channel has meaningful content and should be read out.It can be seen from above description that the FADC conversion, data transfer from pipeline to buffer1, charge extraction, zero suppression and VME readout, all these five processes can be performed concurrently.

In the Fig. 3.5.2.2-3, all the logic functions in the upper dotted line block will be implemented by a part of FPGA (Field Programmable Gate Array). One FPGA will be enough for four channels, so in each module there will be 8 such FPGAs. All logic functions in the lower dotted line block will be performed by another so called global FPGA.

The module will be designed on 9U VME standard board(280mm×366.7mm or 220mm×366.7mm). 32 channels in one module is possible. Totally there will be 188 FADC module, and 11 of 9U VME crates will be needed.

⑷ Time measurement The time measurement module receives the discriminated signal from main

amplifier. Its main task is to measure the time interval between the time t at which a good event was produced, and the leading edge of the discriminated signal. The time t is given by trigger system.

There are a number of optional schemes to perform time measurement. At present two schemes are considered as given below. ① Time measurement based on CERN HPTDC

As a first option, the HPTDC chip, which is designed recently with 0.25um CMOS technology by CERN microelectronics group, will be chosen as a key component for time measurement. This is a general time measurement chip with high performance aimed for time measurements for several large detectors at LHC which are being constructed. The first prototype chips are under testing in CERN at present. Its main specifications are as follows:

□ No dead time.□ High integration. 32 channels on each chip.□ Good time resolutions with four programmable options(estimated):

～ 250ps RMS low resolution mode ～ 70ps RMS medium resolution mode ～ 35ps RMS high resolution mode

8

～ 15ps RMS very high resolution mode (8 channels)□ double pulse resolution: ～ 5ns.□ Cheap. ～ RMB 600.0Yuan per chip.

Using the CERN HPTDC chips to design the MDC TDC module on a 6U VME standard board, it is expected that at least 64 channels per module is possible. For total 6000 time channels, the time measurement system can be setup with 94 6U- VME modules in 6 6U-VME crates.

② Time measurement based on <TAC + FADC> The Fig. 3.5.2.2-4 shows a concept diagram for this scheme. In the diagram, td is the drift time to be measured. The trigger clock is a pipeline clock according to which the trigger system makes trigger decision step by step. One trigger clock period (40ns) will cover 5 collision bunches (8ns).

Suppose at a moment t = t, an interesting collision occurred. At the moment t = td, the hit signal (discriminated wire signal) comes. As shown in the diagram, the interval td between the two moments is the time to be measured. It is obviously that the interval td contains two portions: a number of clock period, and a fraction of a clock called as mantissa tm. We have: td = n×T + tm (a)where n is an integer, i.e., the clock number the td covers. T(40ns) is the clock period. The integer n can be simply measured by counting the clock number covered by the drift time. Therefore if tm can be measured, it will be easy to get the drift time td. It is rather complicated to measure the tm directly. But it can be seen from the diagram:

9

Fig. 3.5.2.2-4 Concept diagram for drift time measurement

Triggerclock

hit (discriminatedwire signal)

Triggeractive

tm tx40 ns

Good event (t = t)

td to bemeasured

Trigger latency

t = td

tm = T - tx Therefore: td = (n + 1) ×T – tx (b)So the time measurement for tm can be replaced by measuring tx. An analysis proves that such replacement will greatly simplify the circuit design, and also the measurement precision will be better. With the above considerations, the drift time measurement can be divided into two parts: one counts the clock number (integer) covered by drift time, another uses <TAC + FADC> scheme to measure the tx precisely. Thus from equation (b), the drift time td can be completely measured with a good resolution.

A simplified block diagram for such scheme is given in Fig. 3.5.2.2-5. The module can be designed on to 9U VME standard board. 32 channels in one module will be possible.

3.5.2.3 Central trigger chamber electronics This subsystem is designed to measure the charge value carried by the output

signal of central trigger chamber and to provide hit information to trigger system. The Central Trigger Chamber will adopt a design scheme based on <optical fiber

+ avalanche diode>. As the signal from the avalanche diode is quite weak, a very low noise preamplifier must be designed specifically to have an acceptable S/N ratio. The

10

FPGA

VM

Ebus

reset

Clock

starthit TAC

Self-reset

Add

W

G_buf

GlobalFPGA

ID

Buffer2

ckReset (from Trigger)

ck

ck

Reset

SW

12

Add

R

w R

Trigger active

Buffer1Pipeline

clock

FADCCircular DPM FIFO

ClockCounter

——

triglatency

Processing Logic

Trigger No. counter

Trigger No. registerdelay

RAM

FIFO

FIFO

Fig. 3.5.2.2-5 Block diagram based on <TAC+FADC>

design for the rest of this system can refer to one for the charge measurement of MDC.

3.5.2.4 TOF Electronics(1) Overview

The TOF counter consists of plastic scintillator, CCT and PMTs. The main tasks of TOF electronics are:

◊ By measuring the flight time of the particles to provide the information for particle identification;

◊ To provide hit information for trigger system.◊ By measuring the charge to correct the flight time.

The main measurement requirements are as follows:◊ Time measurement

Number of channels: 640 Time range: 0-60ns Time resolution: σt ≤25ps

◊ Charge measurement Number of channels: 320

Dynamic range: 2Vmax for TOF 0.2Vmax for CCT

resolution: 2% at 2V for TOF, at 0.2Vfor CCT

11

From L1 Trigger

L-threshold

H-threshold

L0 trigger

From Online

To Trigger

Pre-amp

Stop

Splitter

Start

Stop

Signal Driver ADC Read-out

TDCDisc.

Read-out

Calibration

Disc.TDC

Read-out

Fig. 3.5.2.4-1 Block Diagram of the TOF electronics

The TOF electronics is composed of preamplifier, splitter, time measurement, charge measurement, read-out and calibration. The signals from preamplifier are splitted into three ways in splitter board to provide input to :

(a) Drivers, for charge measurement;(b) Discriminators with High threshold, for time measurement and trigger

system;(c) Discriminators with Low threshold, for time measurement.

(2) PreamplifierThe preamplifier aims to amplify the smaller signal from CCT with fast speed,

Lower power consumption and low noise, to give an voltage output. They should be located close to the PMTs and be capable of driving 50 Ω load. A calibration input will be available for test purpose.

(3) Time measurementTwo kinds of schemes have been studied for time measurement. The first

candidate is based on a special device HPTDC, which is a event driven time to digital converter. For dead timeless operation, HPTDC will fulfill the requirements. The features are high precision, lower power dissipation and lower cost per channel.

The second scheme for time measurement is based on a TAC plus digital pipeline, of which the block diagram is shown in Fig. 3.5.2.4-2.

TAC Section:The TAC operates in common start mode, the start is provided by trigger L0,

which is synchronized with the beam crossing time. Each PMT signal (hit) is delayed for 200ns (trigger L0 latency) and is used as a stop. A ramp signal is generated by discharge a capacitor with a constant current. The final voltage is held on the ramp

12

Pipeline

VM

E bu

s

WR

Trig. 1

Clock

Stop

Start

Trig. 0

Hit Delay TAC

FAD

C

FIFO FIFO

-1

Proc

essi

ng

FIF

O-2

Fig. 3.5.2.4-2 Block diagram of time measurement

capacitor after the arrival of stop. The value represents the time interval between the trigger .L0 and arrival time of particle.

The bunch spacing is 8ns and the cycle of trigger pipeline clock is 50ns. In this case, about 6 collisions will occur during each trigger clock. Since the longest flight time of particle is 60ns, a time window of 110ns will be needed. A reset signal is given to reset the capacitor 180ns after Trig. L0. The timing relationship for time measurement is shown in Fig. 3.5.2.4-3.

ADC Section:BEPCII will operate with multi-bunch and higher luminosity. To keep the signal

information before the arrival of trigger L1, the pipeline technology will be used.For TOF system the time measurement with a precision of 25ps is required,

based on this requirement, the output of TAC is digitized by a 12bit FADC operating at a sampling rate of 20MHz. The result of digitalization is written into the pipeline FIFO-1 with the same clock frequency of FADC. The length of digital pipeline is set to equal to length of trigger L1 latency. The data N+3 from FIFO-1 is considered as a good event when the trigger is active. These data will be stored into event buffer(FIFO-2), waiting being readout by VME controller. The functions implemented on the board for data processing are: (a) Empty channel detection/suppression; (b) Hardware offset subtraction; (3) Events assemble with data format.

13

50ns

N+2 N+3N+1N

Beam crossing * * * * * * *

FADC clock

Reset

Hit

TAC output

Trig. 0

Fig. 3.5.2.4-3 Timing relationship for time measurement

20M Clock

Trigger 1 (2.4us )

50ns WR RD

(4) Charge measurement The charge measurement circuitry consists of a voltage-to-current converter, an integrator, a FADC, a subtractor and two FIFOs. Digital pipeline is used for charge measurement. The block diagram is shown in Fig. 3.5.4.3-4:

The bottom width of the signal from PMT is ～ 20ns and the flying time of particle is less than 60 ns. The FADC digitizes the output of integrator with 20MHz clock. The timing relationship for charge is as follows:

The difference between the data N+4 (peak value) and data N+1 (baseline) represents the charge value. Following operation is similar to the time measurement.

14

Beam crossing * * * * * *

N+4N+3N+2N+1NFADC Clock

Sampling point

Integrator output *

50ns 60ns

20ns

Hit

Fig. 3.5.2.4-4 The timing relationship for charge measurement

FADC

Inte

grat

or

V/I FIFO-1FIFO-2

Fig. 3.5.4.3-4 Block diagram for charge measurement

Peakfounding

3.5.2.5 Electromagnetic Calorimeter Electronics (EMC)(1) IntroductionBESIII Electromagnetic Calorimeter is composed of two parts: barrel and end-

cap. The barrel electromagnetic calorimeter is made of 20200 pieces of BGO crystals and photodiodes. Its electronics measures the charge output of the detector. The end-cap electromagnetic calorimeter is made of scintillating fibers, lead, and photo-multipliers. There are 1000 detector cells in total in the end-cap. Its electronics measures charge as well as the arrival time of the particles. Both electronics must provide trigger information.

The bunch spacing of BEPCII is 8ns. The digital pipeline is adopted to keep the event information before the arrival of trigger signal. The design follows VME bus standard. Most circuits are assembled on 9U VME modules, 32 channels in one module. The mother-daughter board structure is used for easy maintenance. The data read out of each crate is done by the master (Power PC).

(2) Barrel Electromagnetic Calorimeter Electronics① System specification and working conditions

Trigger clock 40 MHzL1 trigger latency 2.4 usSingle channel event rate 1KHz/chThe range of charge 300 fc to 4 fcThe resolution of charge q=0.2 fc

② Electronics systemFig. 3.5.2.5-1 is the block diagram of barrel electromagnetic calorimeter electronics.

15

Trigger

Post amplifier

V

M

ETrigger L1CTrigger CL1

Trigger L1

CR (RC)2Preamp

∑

Calibration

Fan out

Fig 3.5.2.5-1 Block diagram of Barrel EMC electronics system

from detector Chargemeasureme

ntcontroller

The operation principle of barrel electromagnetic calorimeter is as follows: Preamplifier

The energy resolution is good in BEMC because the BGO crystals and photodiodes are used. The preamplifier must have high gain and low noise to satisfy the system requirements since the photodiode has no gain and its output charge is only in the order of femto-coulomb.

The anti-noise performance is good in the charge sensitive amplifier. It is used almost in all high-resolution energy spectra measuring systems.

The barrel electromagnetic calorimeter uses FET as the input stage of the low noise charge sensitive preamplifier. Its main specifications are:

Gain: 12 mv/fcEquivalent input noise: q=0.2 fc (when input capacity is 230 pf)Dynamic range 300 fc to 4 fcTime constant of output decay 800 s

Post amplifierThe post amplifier will adopt a CR-(RC)2 shaping circuit to increase the signal to

noise ratio, eliminate the signal piling up and improve the sampling accuracy of the charge measurement. The time constant of the CR-(RC)2 shaping circuit is 0.5 s.

The signal voltage is sampled and converted to digital data by FADC with the sampling frequency of 20 MHz. The data then enter a peak finding circuit. The peak data represent the charge value to be measured. It is required that the width of the signal peak should be wider than the FADC sampling interval, so that one or more FADC samples can fall on the signal peak. If we define the difference between the sampled data and the peak value within the peak range as less than 0.1%, we can get 1 to 2 samples on the peak range after the signal passes through the CR-(RC)2 shaping circuit with the time constant of 0.5 s. The signal after shaping goes to 2 path. One for charge measurement, and in another path signal is added with the adjacent signals for trigger circuit to make trigger decision.

Charge measurementThe charge of the detector signal is proportional to the peak amplitude of the

voltage signal of the post amplifier’s output. Electromagnetic calorimeter electronics samples the post amplifier signal and finds the peak sample to measure the charge value. Fig. 3.5.2.5-2 is the block diagram of charge measurement.

16

a. Auto-range encoding circuit (AREC)The dynamic range of charge measurement is 1500:1 (11 bits). To reduce the

electronics cost, we choose 10 bits FADC. An auto-range encoding circuit will be used to reach the 11 bits dynamic range. Its operation principle is shown in Fig.3.5.2.5-3.

The full scale of FADC is 4 V. The post amplifier output is 4 V when the EMC electronics input charge is 300 fc. The post amplifier signal is fed to FADC through the auto-range encoding circuit. The auto-range encoding circuit divides the post amplifier signal to A and B two path. The gain of path A is 8, and the gain of path B is 1. Path A is connected to FADC when the output of post amplifier is low, and path B is connected to FADC when the post amplifier output is higher than 3.2V/8=0.4V. This circuit controls the above procedure automatically.

Obviously, the full scale of the 10 bits FADC is multiplied by the factor of 8. It is equivalent to a 13 bits FADC. The cost is even lower than a 12 bits FADC.

Fig. 3.5.2.5-4 is the resolution of BGO crystal, 12 bits FADC and 10 bits multi-range FADC. It shows that the energy resolution of the 10 bits multi-range FADC is much better than the energy resolution of the BGO crystal itself.

17

Fig.3.5.2.5-3 Block diagram of the Auto-Range Encoding Circuit

×8

×1 B

AFADC

FIFO

Post amplifier 0 ― 4V

threshold: 3.2V Comp.

BufferFIFO2

WR

Post amplifier

AREC

FADC

PipelineFIFO1

WR RD

FindPeak

TriggerCounter

FADC CLK

Trigger L1Trigger number

Fig.3.5.2.5-2 Block diagram of the charge measurement

b. Peak findingAll the data, after the trigger system claims a good event within 1.5 s, are read

into a peak finding circuit to find out the peak value, which is then stored in a buffer with the current trigger count.

The peak finding circuit is implemented with FPGA. Its operation is synchronized with FADC and the digital pipeline. The result is generated 1.5 s after the arrival of L1 Trigger signal.

Read out controllerThe commercial VME master, Power PC, is chosen as the read out controller. Its

main functions are:a. Reading out the data from all the modules of its crate, adding the data address

(module number, channel number), and sending the whole crate data after packaging to Online system.

b. Executing the instructions from Online system (data taking, calibration, etc.).c. Calculating the calibration constants and pedestals, correcting the data

according to the calibration constants and sending back the pedestals to the modules.

Fan outThe pipeline clock, L1 Trigger must be fanned out and sent to each signal channel. The requirements of the fan out circuit are: High speed, small time jitter and equal delay time.

Data transfer and zero suppression There are 32 channels on each module. Power PC of each crate reads out the

data. We would like to choose hardware zero suppression method.

18

Fig.3.5.2.5-4 Block diagram of the Resolution of BGO and electronics system0.01 0.1 1 10 100

654321

BGOMulti-range 10bit FADCSingle range 12bit FADC

Ener

gy R

esol

utio

n (%

)

GeV

The data must be compared with the pedestal of each channel and stored in the event buffer when the L1 Trigger presents. The corresponding hit flag will be set to “1”, if the data are higher than the pedestal of a channel. There is a 32-bit hit flag register in each module. The Power PC read the hit flag register first, and then read the data according to the hit flag bits. The channels with the data lower than the pedestals will be skipped.

The channel numbers, the module numbers are packaged into the data flow in the Power PC. The pedestal of each channel is written into each module after calibration.

Calibration circuitThe main function of the calibration circuit includes calibration and system

checking of the electromagnetic calorimeter electronics. This circuit must also provide the necessary simulated L1 Trigger signal, besides the calibration charge. The calibration charge must have good linearity.

(3) The electronics of End-Cap EMCThe End-Cap EMC of BESⅢ consists of scintillating fibers, lead and PMTS.

There are about 800 signal channels in total.The main tasks of the electronics are to measure amount of charge (signal

amplitude) and time of particle arrival.The block diagram of electronics of End-Cap EMC is shown in fig.3.5.2.5-5.

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FromDetector

∑

V

M

E

Calibration

Controller

Controller

Fan out

Trigger

Trigger CL0,CL1 CTriggerL0,L1 Trigger

Shaping

Disc.

Splitter

Preamp

Chargemeasurement

Timemeasurement

Fig.3.5.2.5-5 Block diagram of End Cap EMC electronics system

① The system specification and working conditions Clock of trigger 40MHz Delay of L1 trigger 2 .4s

Delay of L0 trigger 200nsEvent rate of single channel 1 KHz / chPrecision of charge measurement 1 %Range of time measurement 60ns Precision of time measurement 25ps

② Electronics system of End Cap EMC 1. PreamplifierPreamplifier must be put as near detector as possible. It should have features of

fast response, low noise and ability to drive load of 50 ohms.2. Splitter

Signals from the PMTs are sent to the splitters via preamplifier and then split into 3 ways.

a. One way, after shaping, is sent to charge measurement unit to measure energy depositions of the particles.

b. One way is sent to time measurement unit to measure the time.c. “Analog sum” of adjacent channels are sent to the trigger system

3. Charge measurementThe operation principle of charge measurement is similar to that of barrel

EMC.4. Time measurement There are two ways to realize time measurements. The best way is to use

HPTDC of CERN. HPTDC is a time measuring method based on DLL (Delay Locked Loop). It has advantages of low cost and dead time free.

Another way to measure time is “TAC + FADC”. It is a way to convert time to voltage first and then digitize the voltage. This method is similar to the method of time measurement of EMC of CLOE, except that we plan to use the method of digital pipeline to decrease the dead time. The block diagram of “TAC + FADC” of time measurement is shown in fig.3.5.2.5-6. The controller of read-out, fan-out, transfer of data, zero suppression, calibration circuits and so on, are similar to these of barrel EMC.

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To sum up above, it is possible for electronics system of EMC to complete Data acquisition of charge and time.

In order to guarantee required precision of measurement, interval between two good events should be longer than 1.5s.

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W P(1)＝1.5710-2

R

L1

Clock

VMEBUS

Stop

StartL0

HitDelay TAC

FAD

C

FIFO

FIFO

Processing FIFO

Fig.3.5.2.5-6 Block diagram of time measurement

3.5.2.6 Muon counter electronicsMuon counter (MC) consists of a barrel and two end-caps, constructed with

streamer tubes to have 40000 channels. The function of the readout system of the MC is to transform the signals, after shaping, from the X and Y strips of the streamer tubes into the binary data, to handle the data of the event after trigger signal presents, to store the data into the sub-event buffers with the corresponding header and to wait being readout by the DAQ system.

The readout system of the MC contains 7 VME modules composed of 24 chains of the data scanning in a crate. A chain of the data scanning scans 256-bit data from the strips of the streamer tubes. The readout system is able to scan 43008 data in parallel to satisfy the requirement of the MC.

(1) Output of streamer tubes of MCThe position of a particle hit is presented by the cross-points of the X and Y

strips with induced signals, of which the arrangement with streamer tubes is shown in Figure 3.5.2.6-1. The signal of the strip obtained directly from the end of the strip is a positive signal as shown in Figure 3.5.2.6-2. For a typical strip signal the amplitude is around 6 mV, rise-time 10 ns, length at the base ~ 100 ns.

The discriminator (DISC) and pulse shaping (SHAPE), shown in the leftmost

circuits of the Figure 3.5.2.6-3, transform the strip signals into the data of the position information. The threshold of each discriminator is settable individually.

(2) Chain of data scanning In the readout system of the MC, a chain of the data scanning which scans 256-bit data from the strips, splits into three components: a signal scanning, a trigger processing and a sub-event buffer. The signal scanning is located on the detector; the trigger processing is housed in the extended box near the detector; the sub-event

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buffer is in the VME module. The block diagram of a chain of the data scanning is shown in Figure 3.5.2.6-4.

① Signal scanning The signal scanning, an input component of a chain in the data scanning, scans the output signals of the 256 channels, transforms the analog signals of the strip into the logic signals and transmits the logic signal to the pulse shaping. Due to the small free space of the MC, only the discriminators and output cables are located on the detector, and the other parts of the signal scanning are placed in the extended box. Individually setting the threshold of the discriminater is supplied in order to adapt to the requirements of the different intentions of the experiment.

② Trigger processing The trigger processing as a key component of a chain of the data scanning continually reads the data from the discriminators, saves the data into the FIFO and waits for the arrival of the trigger signal. When the trigger signal arrives, the data corresponding to the current trigger must be sent on the 32-bit bus, caught by the latches and handled by the event processing because the trigger signal appears in 2.4 μs after the appearance of the corresponding data. The event processing contains three steps: saving the event data into a trigger buffer, transmitting the event data through the local bus, adding the header and saving the data into an event buffer.

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The trigger processing consists of a pulse shaping, a FIFO and a trigger buffer. The 256-bit parallel data are transformed into 32-bit parallel data in the 9 words in the trigger buffer. The pulse shaping, a mono-stable flip-flop with 60 ns, extends the output logic signal of the discriminator to a TTL digital signal latched by the system clock (40 ns) correctly; meanwhile, the data will be saved into the FIFO in this latching cycle of the clock. The FIFO is a pipeline device aimed at reading the data from the strips of the streamer tubes continually and “synchronizing” the data corresponding to the current trigger signal. There are 60 words in the FIFO, whose delay time from the first word to the last word is 2.4 μs. The FIFO will save the current data into the sixtieth cell and push the data of the first cell out to the 32-bit bus in a system clock cycle (clk) in every data-reading cycle. If the trigger signal arrives in a data-reading cycle, the data on the bus will be latched with the trigger signal and saved into the trigger buffer (TRGBFFR) as the data corresponding to current trigger appear on the 32-bit bus. If the trigger signal does not arrive in a data-reading cycle, the data will not be save in the trigger buffer, the cycle will be over and then the other cycles will be continually repeated. The data on the bus will be saved in sequence with the latch 0, latch 1 … and latch 7. In that case, the 256-bit parallel data from the strips become 32-bit data in one word in series with the order word 0 to word 7 and be transmitted to a sub-event buffer in a VME module via 10m transmission cables to reduce the number of the cables. A device transforming the TTL signal into the TTL differential signal is used to protect signal from strong noise disturbance. The component of the TTL to TTLD transformation is shown in Figure 3.5.2.6-4. The spent time of the trigger processing for a chain is about 2 µs, which includes not only the delay time of the data latching, the time needed for saving data into the trigger buffer, but also the delay time of the voltage level transformation, the long distance cables transmission, and the time saving data into the sub-event buffer. Considering that a VME module contains 24 data scanning chains and that the data of each chain are transmitted to the sub-event buffer in a serial way, it will need about 48μs for the data of the 24 chains to be transmit into sub-event buffers in a VME module. In order to avoid data lost for a new trigger during the current trigger processing, a trigger buffer of a chain consists of 9 banks, of which each block is 32-bit wide and 8-words deep. In fact, the size of the trigger buffer can be estimated in the condition of the event rate 3 kHz.

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If the data input rate and data service rate in a buffer both comply with the Poisson distribution, the following formula is used to estimate the size of the buffer,

where λ is the average input rate of the data, Δλ is the rate of the lost data, µ is the average service rate, is the transferring ratio and is the relative rate of the lost data of a buffer with the K banks. If the input rate of the data, that is, the trigger rate is 3 kHz and the number of the banks is 9, the relative rate of the lost data is equal to 2.279× which means that the data lost for one hour is just equal to 2.279× ×1000×3600＝0.246. In this case the lost data can be ignored.

(3) VME module for data scanning The VME module for the data scanning consists of a data receiver, a sub-event buffer and a controller of the local bus. The data receiver is a transformation device whose responsibility is to transform the TTL differential signal into the TTL signal ,

and after which the data can be saved into a sub-event buffer through the 32-bit bus. The controller of the local bus gives the timing for the transmission bus.

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The block diagram of the VME module for the data scanning is shown in Figure 3.5.2.6-4. In the figure a 32-bit counter named “M+C Addr” is used to identify the address of the modules and the chains, which are set with the dip switches in each individual module and chain. These 32-bit address data are coded in the following way: 16 bits for the address of the module and other 16 bits for the chain of the data scanning. The sub-event buffer, whose responsibility is to save the event data from the trigger processing, is a key component of the VME module for the data scanning. To be saved in the buffer, the event data need a header that includes the current trigger number and the address linked with the module and the chain. Considering that the data handling of the DAQ system needs some time, the size of the sub-event buffer should be in 5 banks, each with 32-bit wide and 8-words deep to avoid from some event data lost when a new trigger comes during the current trigger processing. A data structure in the sub-event buffer for a chan is shown in Figure 3.5.2.6-5. The memory of 50 words with 32 bits each word is organized into 5 banks. The first cell of each bank is used to save the current trigger number, and the second cell saves the address data of module and chain. Following cells are sequentially for data of one chain from the lowest channel to the highest channel. So when saved into the sub-event buffer, the data is arranged in the following way: the bit sequence is from the lowest bit to the highest bit in a word; the word sequence is from the third word to the ninth word of each bank. Thus the bit 0 of the cell 2 keeps the data of the channel 0 in the current chain, and the bit 31 of the cell 2 keeps the data of the channel 31 in the current chain. Also, the data of the channel 255 of the current chain is in the bit 31 of the cell 9 in the current bank.

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The trigger number and the address representing the module and the chain will be saved into the sub-event buffer through the 32-bit bus for which the timing is given by a controller of the local bus. One VME module contains 24 chains of the data scanning. The counter of the trigger number (TRGNoCounter) is a common device for all 24 chains in a module, and this trigger number will be saved into every chain’s sub-event buffers. Each chain owns its individual address which, representing the address of the module and the address of the chain itself, is saved into the second cell of its bank of sub-event buffer.

The VME module of the data scanning can read all the data of the 24 chains in parallel, that is, the data of the 6144 channels.

(4) Readout system of MC

The readout system of the MC consists of 7 data scanning VME modules each contains 24 chains of the data scanning to collect 256×24 data from strips of the streamer tubes. So the readout system can read in parallel the data of the 43008 channels to meet the requirement of the MC.

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3.5.2.7 Readout Configurations and Software（1） Objective

According to estimation, the DAQ event rate of BESIII will reach 3000Hz, and event length is less than 8K bytes. The capability of data taking and transmission will be much higher than BESII. So the emphasis consideration for the read-out configuration scheme is how to reduce the “dead-time” in data taking from the front-end electronics and to avoid to come into being the “bottle-neck” of data flow in event data transmission to online computers.

The multilevel parallel processing scheme will be adopted in BESIII read out electronics system. The electronics signals are divided into some parts based on sub-system and channel amount. Each part is one “read out node”. According to electronics channel amount, each sub-system is corresponding for 1 to 7 nodes.

There is one high capability multi-CPU computer as a host computer at each node, in order to control the operation at the node. The host will be linked to the online computer system by one port of multi-port network card, and linked to the master processor of “VME read out crate” by other ports as shown in Fig.3.5.2.7-1. One 100Mhz switch hub is used to build up the network connection between node computer and master/processors in “VME read out crate”.

A “VME read out crate” consists of the front-end electronics modules and one master/processor as crate controller. Normally, there are less than 576 channel-signals in each “VME read out crate”. VME processor with PowerPC750 is adopted as Master/processor, being used for data taking from the front-end electronics, data pre-processing and event data transmission and monitoring for running control.

The total channel number of BESIII read out electronics system is about 76860, and the channel number for each node should be arranged less 3500 channels (Muon system is exception.), i.e. about 6 VME read out crates per node. The device configuration table of BESIII read out electronic system is listed in Tab.3.5.2.7-1.

Based on the network production market trend, the prices of main devices (such as 100M switch hub) are decreased, while the capabilities are increased. And it is now easy to build up the system with market devices. The multi-CPU computer capability/price will become better in the future. So the present commerce products can satisfy the requirements of BESIII read out electronics system. By the way, because there is one master/processor in each VME read out crate, we may reduce its capability such as using a low price PowerPC750 single-board computer to reduce the system overall cost.

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Fig.3.5.2.7-1 BESIII read out electronics system configuration

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Table 3.5.2.7-1 BESIII read out electronics system device list

(2) Software developmentThe software development of BESIII read out electronic system includes the

testing of electronics system and the data taking of DAQ.Based on the future BESIII engineering stages, the following development of the

electronics read out system will be done:① Data taking

Establish and implementation of communication interface protocol of computers, implementation of its control commands; implementation of data taking under parallel computer condition, data pre-processing, event’s data assembling; and implementation of network communication and data transmission.

② System calibrationSetting up the calibration system of the readout electronics system and the calibration program for online system.

③ System fault diagnosisSetting up electronics system fault diagnosis, self-test of sub-system.

④ Condition monitorSetting up the run-time monitor system for electronics system by using advanced technology.

(3) Software developmentThe VxWorks real time operating system and C++ programming language will

be adopted for BESIII read out electronics software development. In order to develop the software for host computer and processor on VME read out crate, it is necessary to order the processor kernel development package BSP.

Microsoft Windows operating system and Visual BASIC, Visual C++ and LabVIEW programming languages will be adopted to build up the software

Item Channels Nodes Read Out Crates

VC 300 1 1 DC 12000 4 22

TOF 960 1 2 EMC(Br.) 22000 7 39

EMC(End) 1600 1 3 Muon(Br.) 20000 1 4

Muon(End) 20000 1 4 Total 76860 16 75

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developing condition for the device or small system testing.In order to meet the quality requirements for the software development, it is

necessary to adopt the standard of software engineering for designing, developing and managing. The software development should be of security, maintainability, expansibility and portability. And finally, the documents and all paper work will be finished.

(4) Main device capability requirementTo get better system performance, the main device will adopt reliable

commercial products. The main devices are as following: ① MVME2431 PowerPC Processor② 100M Switch (8-16 Port) ③ PC Computer with Multi-CPU，Multi-Port Network Card ④ SBS 616 PCI-VME bus Adapter( for test system) ⑤ VxWorks X86 BSP

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