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8/2/2019 3)Architecture
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MicroProcessor Part II 1
MCS-51 Family Overview
Memory Organization
Logical Separation of Program and Data Memory
PROGRAM MEMORY(READ ONLY)
DATA MEMORY(READ/WRITE ONLY)
/EA=0
Ext
/EA=1
Int
Ext
Ext
/ PSEN / RD / WR
0000
FFFF FFFF
00
FF0FFF
4KB=4096B
216
Int
Int
Int
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MicroProcessor Part II 2
MCS-51 Family Overview
After reset, the CPU begins execution from location 0000h
The interrupt causes the CPU tojump to that location, where it
commences execution of the service routine
Ex) External Interrupt = 0003h
The lowest 4K bytes of program memory can be either in the On-chip
ROM or in an External ROM( /EA (=External Access ))
The read Strobe to external ROM, /PSEN, is used for all externalprogram fetches./PSEN is not activate for internal program fetches.
Program Memory
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MicroProcessor Part II 3
MCS-51 Family Overview
0000
0003
000B
0013
001B
0023
002B
8 BYTE
INTERRUPTLOCATIONS
RESET
Internal Program Memory : Lower 4KB region of the program memory
0FFF
PROGRAMLOCATIONS
Program Memory
Longer service routines can be jumpinstruction
If an interrupt service routine is shortenough ( as is often the case in controlapplications), it can reside entirelywithin that the 8-byte interval.
8/2/2019 3)Architecture
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MicroProcessor Part II 4
MCS-51 Family Overview
Internal Data Memory space is shown divided into three blocks, which are generallyrefereed to as the lower 128, the Upper 128, and SFR space
Internal Data Memory Address are always 1 byte wide ( 256Byte )
Data Memory
Accessible byindirectAddressing only
00
FF
807F
UPPER 128
LOWER 128
Accessible bydirectAddressing
Accessible bydirectand indirectaddressing
PORTSSTATUS BITCONTROL BITTIMERREGISTERSSTACK POINTACCUMULATOR(ETC..)
SpecialFunctionRegisters
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MicroProcessor Part II 5
MCS-51 Family Overview
00 ~ 07
08 ~ 0F
10 ~ 17
18 ~ 1F
20 ~ 2F
30 ~ 7F
BANK
SELECTBIT INPSW
11
10
01
00
4 BANKS OF REGISTER (R0~R7)
BIT-ADDRESSABLE SPACE
The Lower 128 Byte of internal RAM
Scratch pad area
The Lower 128 Byte of internal RAM
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MicroProcessor Part II 6
MCS-51 Family Overview
R7R6R5R4R3R2R1R0
R7R6R5R4R3R2R1R0
1st REG. BANK
2nd REG. BANK
3rd REG. BANK
4th REG. BANK
4 X 8 REGISTER BANK
4 Banks Of Register
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MicroProcessor Part II 7
MCS-51 Family Overview
07 06 05 04 03 02 01 00 20h
0F 0E 0D 0C 0B 0A 09 08 21h
77 76 75 74 73 72 71 70 2Eh
7F 7E 7D 7C 7B 7A 79 78 2Fh Boolean Instruction ( Bit Operation )
AND, OR, CLEAR, SETCOMPLEMENT, MOVE BIT ..
Ex) ANL c, Bit AddressCY
Bit AddressAND CY
ANL c, 7fh
Before : CY 1(7fh) 0
0CYAfter :
Bit-Addressable Register
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MicroProcessor Part II 8
MCS-51 Family Overview
Special Function Register (SFR) - (I)
Register MnemonicInternalAddress
Bit/ByteAccess
Port 0 Latch P0 80 Bit
Stack Point SP81
ByteData point ( Word ) DPTR 82 ~ 83 Word
Data point Low Byte DPL 82 Byte
Data point High Byte DPH 83 Byte
Power Control PCON 87 Byte
Timer/Counter Control TCON 88 Bit
Timer/Counter Mode Control TMOD 89 ByteTimer/Counter 0 Low Byte TL0 8A Byte
Timer/Counter 1 Low Byte TL1 8B Byte
Timer/Counter 0 High Byte TH0 8C Byte
Timer/Counter 0 High Byte TH1 8D Byte
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MicroProcessor Part II 9
MCS-51 Family Overview
Register Mnemonic InternalAddress
Bit/ByteAccess
Port 1 Latch P1 90 Bit
Serial Port Control SCON 98 Bit
Serial Data Port SBUF 99 Byte
Port 2 Latch P2 A0 Bit
Interrupt Enable IE A8 Bit
Port 3 Latch P3 B0 Bit
Interrupt Priority Control IP B8 Bit
Program Stats Word PSW D0 Bit
Accumulator Acc or A E0 Bit
B Regster B F0 Bit
Special Function Register (SFR) - (II)
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MicroProcessor Part II 10
MCS-51 Family Overview
Acc : 8 Bit Accumulator ( Arith./Logical Operation)
B : General Purpose Register : X , /
DPTR : 16Bit Register , 8-bit accessable.
( using address pointer in the transmit External Data transfer )
PSW : 8 Bit -Register,
( carry, Overflow, Parity Flag, Selection of the Register Bank )
SP : Stack Point , 8-Bit Register
Special Function Register (SFR) - (III) - Software Control/Operation
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MicroProcessor Part II 11
MCS-51 Family Overview
Timer/Count: TH1, TL1, TH0, TL0, TMOD, TCON
Serial Port
: SBUF, SCON, PCON
Interrupt control
: IE, IP
I/O Port
: P0, P1, P2, P3
Special Function Register (SFR) - (III) - Internal Unit Control
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MicroProcessor Part II 12
The PSW contains several status bitthat reflect the currentstateof the CPU.
Program Status Word (PSW)
CY AC F0 RS1 RS0 OV P
PSW7CARRY FLAG RECEIVES CARRY OUTFROM BIT 7 OF ALU OPERANDS
PSW6AUXILARY CARRY FLAG RECEIVES CARRY OUTFROM BIT 3 OF ADDITION OPERANDS
PSW5GENERAL PURPOSE STSTUS FLAG
PSW4REGISTER BANK SELECT BIT 1
PSW0PARITY OF ACCUMULATOR SETBY HARDWARE TO 1 IF IT CONTAINSAN ODD NUMBER OF 1S, OTHERWISEIT IS RESET TO 0
PSW1USER DEFINABLE FLAG
PSW2OVERFLOW FLAG SETBY ARITHMETIC OPERATIONS
PSW3REGISTER BANK SELECT BIT 0