ECE2411 – Logic Circuits II Lab 1

Introduction to Edge-Triggered Flip-Flops and Their Applications

Name: ___________________________________________________

Due 6/18/2007 at the beginning of class

For this lab Verilog HDL will be used to describe the digital circuits and simulate the circuit. The Verilog will be simulated. You can use the Verilog simulator of your choice. Silos is installed in the lab and a tutorial is available on the course website. Verilog Simulators, Student version available for download Modelsim - www.model.com/resources/student_edition/student_default.asp Active-HDL - www.aldec.com/education/students/ Silos - www.simucad.com/products/simucad/silos/silos.html Turn in a lab report with the Verilog and Simulation results 1. Edge-Triggered Flip-Flops

A positive edge-triggered D flip-flop with asynchronous reset (direct inputs) whose schematic symbol is given in Figure 1.a can be modeled by Verilog HDL as follows: // positive edge-triggered D flip-flop with asynchronous reset module DFF( output reg Q, output wire Q_bar input wire D, input wire clk, input wire rst, ); assign Q_bar = ~Q; always @( posedge clk or posedge rst) begin if (reset) Q <= 1’b0; else Q <= D; end

ECE2411 – Logic Circuits II Lab 1

endmodule

Using the above as an example, give the Verilog description of the T flip-flop whose schematic symbol is shown in Figure 1.b. Use the testbench given below to generate the desired waveform. Demo the desired waveform to the instructor during lab. //testbench of TFF module module t_TFF; reg T; reg clock, reset; wire Q, Q_bar; // Device Under Test (DUT) TFF FF1 (Q, Q_bar, T, clock, reset); // Test Stimulus initial fork begin clock=0; forever begin #5 clock=~clock; end end begin reset=0; #2 reset=1; #10 reset=0; end begin T=0; #20 T=1; #38 T=0; #9 T=1; #2 T=0; #2 T=1; #2 T=0; end begin #200 $finish; end join endmodule

Use the t_TFF testbench to run the DFF (changes will need to be made) and also run TFF. Capture the simulation results and include them in your lab report. Repeat the above for a JK flip-flop. Create the JK flip-flop module and testbench.

ECE2411 – Logic Circuits II Lab 1

2. 2-Bit Counter Design a 2-bit Counter using two D flip-flops. The counter has an asynchronous reset input reset and a clock input clock. It provides two outputs Q1, and Q0, as shown in Figure 7. Upon an asserted reset, the output of the counter should be initialized to 00. Then triggered by the rising edge of the clock signal, the counter should start counting.

To design the 2-bit counter first generate the Boolean equations from the following truth table Q1 Q0 NQ1 NQ0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 From the above truth table (similar to homework assignments) the Boolean equations can be derived for a combinational circuit that adds 1 to the current value. Note a half adder and full adder could be used as well but in this case the circuit will be derived directly. Use the Boolean equations derived to define what the Q1 input (D) will be. Example: Q0 <= a & b | c; Q1 <= b ^ a;

Use the given header and port declaration to model the counter by Verilog HDL. //2-bit counter module counter_2b ( output reg Q1, output reg Q0, input wire clk, input wire rst ); ...... //more code goes here endmodule

ECE2411 – Logic Circuits II Lab 1

Verify the functionality of the 2-bit Counter using the given test bench. Generate the desired timing diagram shown as follows. Demo the desired waveform to instructor during lab. module counter_2b_t; reg clock, reset; wire Q1, Q0; wire [1:0] Q1_Q0; assign Q1_Q0 = {Q1, Q0}; // Device Under Test (DUT) counter_2b C2B (Q1, Q0, reset, clock); initial fork begin clock = 0; forever #5 clock = ~clock; end begin reset = 0; #2 reset = 1; #5 reset = 0; end join initial #80 $finish; endmodule