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8/16/2019 35 Detailed Routing New Chlgs
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Detailed Routing:
New Challenges
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• Manufacturers use different wire widthsVias connecting wires of different widths
− block additional routing resources on the layer with thesmaller wire pitch
Detailed Routing:New challenges
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Detailed Routing:New challenges
130nm 90nm 65nm 45nm 32nm
M 1
M 2
M 3
M 4
M 5
B 1
B 2
M 1
M 2
M 3
M 4
B 1
B 2
B 3
E 1
E 2
M 1
M 2
M 3
M 4
B 1
B 2
C 1
C 2
B 3
E 1
U 1
U 2
M 1
M 2
M 3
M 4
B 1
B 2
B 3
E 1
E 2
M 5
W 1
W 2
M 1
M 2
M 4
M 5
M 6
M 3
Representative layer stacksfor 130 n ! 32 ntechnology nodes
©
2 0 1 1
S p r i n g e r
V e r
l a g
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• Manufacturing yield: a key concern in detailedroutingRedundant vias and wiring segments as backups(via doubling and non-tree routing )
Manufacturability constraints (design rules) becomemore restrictive complicate detailed routing− E ample! design rules specify minimum allowed spacing
between wires and vias depending on their widths andpro imity to wire corners"
− E ample! Recent spacing rules take into account multipleneighboring polygons"
Detailed Routing:New challenges
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#ia Dou$ling
%
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• Detailed routers ust account foranufacturing rules and the i pact ofanufacturing faults
Via defects#performance degradation (frommisalignments)!− Via doubling during or after detailed routing− $rea penalty
%nterconnect defects!− &on-tree routing! $dd redundant wires to already routed
nets (postprocess) $ntenna-induced defects!
Detailed Routing:New challenges
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(ntenna )ffect
•Recent D*M +ssue'ong metal lines and vias introduce antenna
violations"onductor layers fabricated from lowest layer to
highest layer"he etch process builds up the electrical chargeson metal layers"
hese charges cause a high voltage spike* which
may destroy the gates connected to the etals,
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(ntenna )ffect
$ long line connected to gate only can cause
failure&ot a problem after chip is complete since everynet has at least one driver
Driver .diffusion/ oad .poly/
M1
M2
ut we can have a pro$le during anufacturing
ere is the sa e net after M1 is $uilt $ut not yetM2
Driver .diffusion/ oad .poly/
M1
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(ntenna )ffect
Sink 1Difusion Sink 2
Antenna violation
©]5u[
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(ntenna RulesViolations to the above antenna rules in every
metal layer have to be fi ed before the chiptapeout"Each metal layer may have various upper limitrules based on the process specifications"
+", (+",.) um technology! the ma imum length ofan /antenna0 wire 1 2++ um (3+ um)"
6rocess!+nduced Da age Rules .otherwise known as 7(ntenna Rules8/!
9eneral Re uire ents,http:;;www, osis,org;
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(ntenna (voidance1, >u per +nsertion:
Router inserts 4umpers for long metals from low-levelmetals to upper-level layers"− he 4ump cuts the long metals in the low-level layers to
disconnected pieces"− based on the fact that wire segments on top routing layers are
normally fabricated at the end
Difusion Gate
Difusion Gate
Jumper insertion
Antenna violation
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(ntenna (voidance1, >u per +nsertion:•. Disadvantage:
4umpers introduce e tra vias− 5egrade both manufacturing yield and circuit timing
performance
>ia 5ang ai ?hou 7@pti al >u per +nsertion for
(ntenna (voidance under Ratio Apper! ound 8 D(C 200&,
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1%
(ntenna (voidance3, ayer (ssign ent:
Reduce antenna length by layer assignment"
Di 5u >iang u and Ra$i Mahapatra 7Coupling (ware