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ECE 551: Digital System Design * & Synthesis

Lecture Set 3

3.1: Verilog - User-Defined Primitives (UDPs) (In separate file)3.2: Verilog – Operators, Continuous Assignments, Behavioral Modeling, Procedural Assignments, Flip-Flop and Latch Models

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Summary of Verilog Operators - 1

Type Argument(s)

Result Operators Example

Arithmetic

2 operands Binary Word

+, -, *, /, % C = A + B;

Bitwise 2 operands Binary Word

~, &, |, ^, ~ ^ C = A ^ B;

Reduction 1 operand Bit &, ~&, |, ~|, ^, ~ ^

c = &A[7:0];

Logical 2 operands Boolean !, &&, ||, = = , !=, = = =, != =

if (a && b) then

Valid operations and result type depend on types of input operands.

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Summary of Verilog Operators - 2 *

Valid operations and result type depend on types of input operands.

Type Argument(s)

Result Operators Example

Relational 2 operands Boolean <, <=, >, >=

if (A <= B) then

Shift - LogicalShift-Arithmetic

1 or 2 operands

Binary Word

<<, >>, <<<, >>>

C = A << 4;

Conditional 3 operands Expression

? : (A < B) ? A: B;

Concatenation, Replication

2 or more operands

Binary Word

{},{{}} C = {A, B};C = {2{A}};

Operator Precedence+ - ! ~ (unary)

**

* / %

+ - (binary)

<< >> <<< >>>

< <= > >=

= = != = = = != =

& ~&

^ ^~ ~^

| ~|

&&

||

? :

Highest

Lowest

Operators in same box have the same precedence

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In-class Operator Discussion

Bitwise and (&) and logical and (&&)Reduction and (&) and nand(~&)Logical equality(==)/inequality(!=)Case equality (===)/inequality(!

==)Right shift (>>) and Arithmetic right

shift (>>>)

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Special Registers:Memories and Strings

A memory is an array of n-bit registers reg [15:0] mem_name [0:127]; //128 16-bit words Reference can only be made to a word of memory

mem_name[122] = -127; // assigns word mem_name[13][5] = 1; // illegal Verilog 2001 allows multidimensional arrays/memories

Strings are stored using properly-sized registers reg [12*8: 1] stringvar; // 12 character string

stringvar = “Hello World”; // string assignment Unused characters are filled with zeros

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Types of Assignments

Continuous Procedural

Blocking Non-Blocking Continuous

•assign, deassign•force, release

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Continuous AssignmentAssigns values to nets, bits of nets,

parts of nets, or concatenation of any of the above

Appear in RTL/dataflow descriptionsSyntax assign LHS = RHS Execution: If operand on RHS

changes, RHS evaluated and if RHS value changes, new value assigned to LHS

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Continuous Assignment Examples

assign S = A + B; assign {C0, S} = A + B + CI; assign W = X & (Y ^ Z); assign p = (m >= n) ? m : n; assign x = y | z;

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Procedural AssignmentsTypes

assign = continuous assignment = blocking assignment <= non-blocking assignment

Assignments (with one exception) to: reg integer real realtime time

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Procedural Assignments - Some Rules

Variable can be referenced anywhere in module Variable can be assigned only with procedural

statement, task or function Variable cannot be input or inout Net can be referenced anywhere in module Net may not be assigned within behavior, task

or function. Exception: force … release Net within a module must be driven by

primitive, continuous assignment, force … release or module port

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Procedural Continuous Assignment

Two types assign … deassign

•to variable•dynamic binding to target variable

force … release•to variable or net•dynamic binding to target variable or net

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Procedural Continuous Assignment - Examples

Example 1: reg Q;always @ (clk)

if clk = 1 assign Q = D;else assign Q = Q;

Example 2: net Q;always @ (set or reset)

if set = 1 force Q = 1; elseif reset = 1 force Q = 0; elseQ = Q;

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Procedural Continuous Assignment

A procedural continuous assignment overrides all regular procedural assignments to variables

Example:module dff_pc (q, d, clear, preset, clk);output q;input d, clear, preset clk;reg q; //continued on next slide

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Procedural Continuous Assignment

always@(clear or preset) if (!clear) assign q = 0; else if (!preset) assign q = 1; else deassign q;always@(posedge clk) q = d;endmodule

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Behavioral ConstructsConcurrent communicating behaviors

=> processes = behaviorsTwo constructs

Initial - one-time sequential activity flow - not synthesizable but good for testbenches

Always - cyclic (repetitive) sequential activity flow

Use procedural statements that assign only variables (with exception of force/release on net)

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Behavioral Constructs (continued)

Continuous assignments and primitives assign outputs whenever there are events on the inputs

Behaviors assign values when an assignment statement in the activity flow executes. Input events on the RHS do not initiate activity - control must be passed to the statement.

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Behavioral Constructs (continued)

Body may consist of a single statement or a block statement

Block statement begins with begin and ends with end

Statements within a block execute sequentially

Behaviors are an elaborate form of continuous assignments or primitives but operate on registers (with one exception) rather than nets

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Behavioral Constructs - Example

Initial: Always: initial always begin begin

one = 1; F1 = 0, F2 = 0 two = one + 1; # 2 F1 = 1;

three = two + 1; # 4 F2 = 1; four = three + 1; # 2 F1 = 0; five = four + 1; # 4;

end end

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Procedural Timing, Controls &

SynchronizationMechanisms Delay Control Operator (#) Event Control Operator (@) Event or Named Events wait construct

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Procedural Timing, Controls &

SynchronizationDelay Control Operator (#) Precedes assignment statement - postpones

execution of statement For blocking assignment (=), delays all

statements that follow it Blocking assignment statement must

execute before subsequent statements can execute.

Example: always @(posedge clk),#10 Q = D;

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Procedural Timing, Controls &

SynchronizationEvent Control Operator (@)

Synchronizes the activity flow of a behavior to an event (change) in a register or net variable or expression

Example 1: @(start) RegA = Data; Example 2: @(toggle) begin

… @ (posedge clk) Q = D; … end

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Procedural Timing, Controls &

SynchronizationEvent or - allows formation of event expression

In Verilog 2001 can use , instead of orExample:

always @ (X1 or X2 or X3) assign Y = X1 & X2 | ~ X3;

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Procedural Timing, Controls &

SynchronizationMeaning of posedge: 0 -> 1, 0 -> x, x -> 1 Special Example:

always @ (set or reset or posedge clk) begin

if (reset == 1) Q = 0; else if (set = = 1) Q = 1; else if (clk == 1) Q = data;

end// Does this work correctly? Why or why not?

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Procedural Timing, Controls &

SynchronizationNamed Events module cpu (…);

always @ (peripheral.interrupt) begin

... end

module peripheral (…);event interrupt;… -> interrupt;

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Procedural Timing, Controls &

Synchronizationwait Construct Suspends activity in behavior until

expression following wait is TRUEExample:

alwaysbegin

a = b; c = d; wait (advance);

end

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Latches and Flip-Flops

D-LatchPET D Flip-Flop with Asynchronous

Set and ResetPET D Flip-Flop with Synchronous

Set and Reset

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Verilog Model of D-Latch *

module d_latch (enable,d, q); input enable, d; output q; reg q; always @(enable or d)

if (enable) q <= d;endmodule

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Verilog Model of PET DFF with Asynchronous Set

and Resetmodule pet_dff_sr (clk, d, reset, set, q); input clk, d, reset, set; output q; reg q; always @(posedge clk or negedge reset

or negedge set) //active low R and S if (!reset) q <= 0; else (!set) q <= 1; else q <= d;endmodule

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Verilog Model of PET DFF with Synchronous Set and

Resetmodule pet_dff_ssr (clk, d, reset, set, q); input clk, d, reset, set; output q; reg q; always @(posedge clk) //active low reset and set if (!reset) q <= 0; else (!set) q <= 1; else q <= d;endmodule

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Things To KnowOperatorsInteraction of Operators and Operands

Widths For x and z values

Assignments Continuous Procedural

BehaviorsBehavior ControlsVerilog coding for simple storage elements