3/3/2006EECS150 Lab Lecture #71 Digital Video EECS150 Spring 2006 – Lab Lecture #7 Brian Gawalt Greg Gibeling

3/3/2006 EECS150 Lab Lecture #7 1

Digital Video

EECS150 Spring 2006 – Lab Lecture #7

Brian GawaltGreg Gibeling


Today

Digital Video Administrative Info ITU-R BT.601 ITU-R BT.656 Video Encoder I2C Bus More Information


Digital Video (1) Pixel Array

A digital image is represented by a matrix of pixels which include color information.

Frames Motion is created

by flashing a series of still frames

1920

1080High-Definition Television (HDTV), 2 Mpx

1152

900Workstation, 1 Mpx

800

600PC/Mac,1‡2 Mpx

640

480Video, 300 Kpx

352

240

SIF,82 Kpx

High-Definition Television (HDTV), 1 Mpx

1280

720


Digital Video (2) Scanning

Images are generated on the screen by scanning pixel lines, left to right, top to bottom

Early CRTs required time to get from the end of a line to the beginning of the next. Therefore each line of video consists of active video portion and a horizontal blanking interval. Even more time is needed for the CRT gun to transition from the end of the last line to the start of the first, requiring each frame to have a vertical blanking interval.

To reduce flicker, each frame is divided into two fields: odd and even


Digital Video (3) Colors

Usually represented as red, green and blue

In the digital domain we could transmit 8 bits for each RGB component.

Transition from Black & White Kept compatible with old TV sets Added separate color or “Chroma” signals

Y: Luma (Traditional Black and White) Cr: Chroma Red (New color signal) Cb: Chroma Blue (New color signal)


Digital Video (4) Digital Chroma Subsampling

Human eye is more sensitive to Luma than Chroma; use this to save space and bandwidth

R0

R2

R1

R3

G0

G2

G1

G3

B0

B2

B1

B3

Y0

Y2

Y1

Y3

CB

CB

CB

CB

CR

CR

CR

CR

Y0

Y2

Y1

Y3

CB 0-1

CB 2-3

CR 0-1

CR 0-1

Y0

Y2

Y1

Y3

CB 0-3

CR 0-3

Y0

Y2

Y1

Y3

CB 0-3

CR 0-3

RGB 4:4:4 Y CR CB 4:4:4 4:2:2 (ITU-601) 4:2:0 (MPEG-1) 4:2:0 (MPEG-2)


Administrative Info (1) Design Review Process

Walk your lab TA through the module Control/Datapath Top-down design with interconnections

Errors will be pointed out, but corrections are left up to you

Ideal duration: 10 minutes It’s a team effort!

Convince us you know what you’re doing!


ITU-R BT.601 Formerly, CCIR-601.

Designed for digitizing broadcast NTSC

America’s National Television System Committee

Variations: 4:2:0 Chroma

Subsampling PAL (European) version

Component streaming: line i: CB Y CR Y CB Y CR Y line i+1: CB Y CR Y CB Y

CRY Effective Bits/Pixel:

4 components / 2 pixels = 32/2 = 16 bits/pixel

Active Frame Size

720 x 507

Frame Rate 29.97 /sec

Scan Interlaced

Chroma subsampling

4:2:22:1 in X onlyCoincident

Bits per component

8

Effective bits/pixel

16


ITU-R BT.656 (1)

Details Pixels/Line: 858 Lines/

Frame:525 Frames/S: 29.97 Pixels/S: 13.5M

Active Pixels/Line: 720 Lines/

Frame:507

Blanking SAV/EAV: 4B/4B Black filler

7 1 8 7 1 9 72 0 7 2 1 0 1 2

3 59 3 6 0 0 1

359 3 6 0 0 1

7 3 67 3 2( )

3 6 83 66( )

3 6 83 6 6( )

8 5 78 6 3)(

Y 71

8

Y 71

9C

36

0B Y 72

0C

36

0R

Y 7

21

C

359

B

C

359

R

Y 7

36(7

32)

C

368(

366)

B

C

368(

366)

R

Y 85

5(86

1)C

42

8(43

1)B

Y 8

56(8

62)

Y 85

7(86

3)C

0

B

Y 0

C

0R

Y 1

C

428(

431)

R

C

0B

Y 0

Y 1

C

0R

C

359

B

Y 71

8

Y 71

9C

35

9R

L as t sam p leof d igi ta l act iv e l in e

S am p le d a tafor O i n st an t

F irs t sam p leof d igi ta l act iv e l in eH

Lu m in an ced a ta , Y

C h ro m in an ced a ta , C R

C h ro m in an ced a ta , C B

R e p lace d byti m in g referen ce

s ign al

R ep laced b yd igi tal b la nk in g d a t a

R ep l aced b yt im i n g re fe r en ce

s ig na l

E n d ofact iv e v id eo

Star t ofact iv e v id eo

T im in g refere nce si gn a ls

N o te 1 – Sam p le i d en ti fi cat io n nu m b ers i n pa ren the se s a re for 6 2 5 -li ne syst em s w h e re th e se di ffe r fro m th os e for 5 2 5 -li n e s yst em s . (Se e a lso R eco m m en d ation IT U -R B T .8 0 3 .)

FIG U RE 1

C om po sit ion of in te r fa c e da ta s tre a m

D 0 1


ITU-R BT.656 (2) Odd Field (262 Lines)

Total: 262 Lines 6 Vertical Blanking 254 Active 2 Vertical Blanking

Even Field (263 Lines)

Total: 263 Lines 7 Vertical Blanking 253 Active 3 Vertical Blanking


ITU-R BT.656 (3)

SAV Header F: Field Select (0: Odd, 1: Even) V: Vertical Blanking Flag H: EAV/SAV Flag (0: SAV, 1: EAV) E[3]=V^H, E[2]=F^H, E[1]=F^V, E[0]=F^V^H

P9 P8 P7 P6 P5 P4 P3 P2

1’b1 1’b1 1’b1 1’b1 1’b1 1’b1 1’b1 1’b1

1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0

1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0

1’b1 F V H E[3] E[2] E[1] E[0]


Video Encoder (1) Analog Devices ADV7194

Supports ITU-R BT.601/656 S-Video and Composite Outputs I2C Control (We will give this to you)


Video Encoder (2)Signal Widt

hDir Description

VE_P 10 O Outoing NTSC Video (Use {Data, 2’b00})

VE_SCLK 1 O I2C Clock (For Initialization)

VE_SDA 1 O I2C Data (For Initialization)

VE_PAL_NTSC

1 O PAL/NTSC Mode Select (Always 1’b0)

VE_RESET_B_

1 O Active low reset (~Reset)

VE_HSYNC_B_

1 O Manual Control (Always 1’b1)

VE_VSYNC_B_


VE_BLANK_B_


VE_SCRESET 1 O Manual Control (Always 1’b0)

VE_CLKIN 1 O Clock (27MHz, Just send Clock)


Video Encoder (3)Signal Width Dir Description

Clock 1 I Clock input (27MHz)

Reset 1 I Reset input

DIn 32 I Requested Data from ROM

InRequest 1 O Request Data from ROMDIn will be valid after rising edge

InRequestLine

9 O Line of Video ({Line[7:0], Field})The ROM will return a pixel from this line

InRequestPair

9 O Pair of PixelsThe line will return data for this pixel pair


Video Encoder (4)

AD

V7194

Monitor

Ou

tgoing

Video

(S-V

ideo Ou

t Cable)

Test ROM 32b N

TS

C V

ideo

(No

Blanking)

10b NT

SC

Vide

o(C

om

plete)

Video Line &

Pa

ir A

ddre

ss

I2C Control

HCount VCount

H FSM V FSM

Blank Gen

(Mux)

Data Clip

VideoEncoder

IOR

egI2C

Clock &

data

I2C

Clock &

data

32b Clipped YCrYCb(0x10≤Data≤0xF0)

Blank Control

Ho

rizonta

l &

Ve

rtical Co

unt

I 2C D

one

General Video Encoder Block Diagram


Video Encoder (5) Basic Design

Stream EAV, Blank, SAV, Active Lines Generate EAV/SAV/Blank using a

multiplexer Register output data (Timing reasons)

Request Incoming Data Request it the cycle before you need it Clipping data

Minimum data is 0x10 Maximum data is 0xF0 Otherwise it will appear to be blanking signals


Video Encoder (6) Testing

Test thoroughly Simulation is difficult with test ROM Try using values which count, so you can

see it Design your testbench early

Perhaps one partner should design the module, one should design the testbench

Ensure that you test corner cases First and last lines Off-by-one errors in counters


I2C (1) ADV7194 Initialization using I2C

Requires only 2 wires Serial Data (Bidirectional) Clock (Driven by master)

Runs at up to 400kHz Bidirectional Communication

Given to you Complicated to get right Hard to debug


I2C (2) Physical Protocol

Data Open collector

bidirectional bus Driven by sender

Clock Open collector

unidirectional bus Driven by master May be pulled low

to stall transmission

10kΩ Pullup 10kΩ Pullup

DIn

DO

ut

Ena

ble

DIn

DO

ut

Ena

ble

Endpoint BEndpoint A

Bidirectional Open Collector Bus


I2C (3) Protocol

Start Condition Address Address Acknowledge Data Transfer Data Acknowledge Stop Condition


I2C (4) Arbitration

Anyone can drive bus at any time No central arbiter No short circuits (Impossible in open collector)

Decentralized Arbitration Check data bus against value you’re sending Mismatch means someone else is transmitting

So let them finish, and then try again Inherently gives preferences to accesses with

more 1’b1s in them


More Information Checkpoint Writeup Documents Page of the Website

Video in a Nutshell ADV7194 Datasheet

Complete ADV7194 reference ITU-R BT.656 & ITU-R BT.601 Standards

Complete video standards I2C Bus Specification

READ THE DATASHEETS!