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Progress In Electromagnetics Research Symposium Proceedings, Suzhou, China, Sept. 1216, 2011 541

A Broadband Low Noise Amplifier for X-band Applications

Cheng-Chi Yu1, Jiin-Hwa Yang2, Hsiao-Hua Yeh1, and Lien-Chi Su1

1Department of Communications Engineering, Feng-Chia UniversityNo. 100, Wen-Hua Rd., Seatwen, Taichung 407, Taiwan, R.O.C.

2

Ph.D. Program in Electrical and Communications Engineering, Feng-Chia UniversityNo. 100, Wen-Hua Rd., Seatwen, Taichung 407, Taiwan, R.O.C.

Abstract A broadband low noise amplifier (LNA) for X-band (812GHz) applications isproposed in this study. The proposed LNA circuit is composed of three-stage NMOS transistorswhich construct a cascade configuration. The design can achieve wide-band matching and highergain at the same time. The proposed LNA chip is fabricated by TSMC 0.18 m CMOS process.The chip occupies a die area of 0.45 mm2 (0.73mm 0.62 mm) only. On-wafer measurement wasused to measure the characteristics of the LNA. The measured results show that gain ( S21) of15.15 20.05 dB, noise figure (NF) of 2.9 3.1 dB are obtained. The total power consumptionis 12.45 mW under a power supply voltage of 0.75 V. The good performances of the LNA makeit suitable for X-band applications

1. INTRODUCTION

The high sensitivity X-band (812 GHz) receiver is an important device for wireless communicationapplication such as radar and satellite communication. The X-band systems are widely used inmilitary radar and aircraft [1]. Low noise amplifier (LNA) is one of the most important buildingblocks in front end of communication systems. It is a key component that provides good inputreturn loss, low noise figure and good linearity for the receiver. Low voltage, low power, and goodperformances are always targets of LNA design, especially for radar applications. At high frequency,the parasitic affect the circuit performance greatly. To find a good architecture is essential that canfit demand and provide a good performance for X-band LNA This paper demonstrates a three-stagecascade configuration X-band broadband LNA design by TSMC 0.18 m CMOS process

2. CIRCUIT DESIGN AND ANALYSIS

The complete schematic of the proposed LNA is shown in Fig. 1. This circuit is a three-stage NMOStransistor architecture It is constructed by a cascade configuration which is adopted to enhancethe bandwidth. For producing the 812 GHz operating frequency range of the proposed LNA, theoperating frequencies of first, second and third stages are designed at 8 GHz, 10 GHz and 12 GHz,respectively. The three-stage architecture can achieve wide-band matching and higher gain at thesame time [2]. The source inductor is used to improve impedance matching in this circuit [3].

Furthermore, in order to reduce chip area, the authors self-layout mutual coupled inductor [4]which combines with source inductors of MOS1 and MOS2 is presented in this design to replacethe conventional structure of the CMOS process. And the circuit only uses two supply power padson one side. That can save the area of supply power pad on other side. An obvious size reductionis obtained by these topologies. The proposed LNA chip is fabricated by TSMC 0.18m CMOS

Figure 1: Schematic of the proposed broadband LNA. Figure 2: Photograph of the X-band LNA.

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542 PIERS Proceedings, Suzhou, China, September 1216, 2011

process. The die photograph of the LNA is shown in Fig. 2 The chip only occupies a die area of0.45mm2 (0.73mm 0.62 mm).

3. EXPERIMETAL RESULTS

The proposed LNA was simulated by ADS simulator. The simulated S-parameters are shown inFig. 3. The simulated and measured results of the LNA are summarized in Table 1. The simulated

and measured results have a good agreement. The LNA requires only a 0.75 V supply voltage andconsumes 12.45 mW powers. The circuits -factor is more than 1 which means that the circuit isunconditional stable in the operating frequency. The simulated and measured power gain is shownin Fig. 4. Between the operating bandwidth of 812 GHz, the proposed LNA has power maximumgain of 2005 dB, noise figure (NF) of 2.9 3.1 dB, with input return loss between 10.5 to 9.7 dBand output return loss less than 1 dB. The proposed LNA exhibits a good performance of gain,noise and chip size.

4 6 8 10 12 14 16

Frequency (GHz)

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

30

Mag

nitud

e(dB

)

S11 [dB]S22 [dB]S21 [dB]S12 [dB]

Figure 3: Simulated S-parameters of broadband low

noise amplifier.

4 6 8 10 12 14 16

Frequency (GHz)

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

Ga

in(d

B)

SimMeas

Figure 4: Simulated and measured results for power

gain of broadband LNA versus frequency.

Table 1: The performance of proposed broadband LNA.

Broadband Low-Noise Amplifier

Vdd1/ Vdd2 (V) 0.75 / 0.75

Technology Simulation Measurement

Operating Frequency (GHz) 812 812

Power Gain (dB) 18.5 1.5 17.6 2.45

Input Return Loss (dB) < 10 10.5 ~9.7

Output Return Loss (dB)