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28HPC – For High Performance and
Power Sensitive Applications
ARM® Asia Tech Symposia
Nov 2014
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28nm – Key Process Technology for next Decade!
*Source: IBS Forecast, July, 2014 Predicted 28nm Wafer Volume*
Both HKMG and Si ON Options
Last 2D mass production technology
Stable process and high native yield
Available at many leading edge foundries
IP re-use/established eco-system
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Market Segments for 28HPM/28HPC
Consumer Enterprise/
Networking
Mobile/
Tablet
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ARM-TSMC Partnership enabling
SoC designs over 15 process geometries
14/16nm 20nm 28nm 40nm 55nm 65nm 80nm 90nm 110nm 130nm 150nm 152nm 160nm 180nm 250nm
FinFET
l l l l l l l l l l l
YEAR 2013 YEAR 2012 YEAR 2011
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ARM Artisan® IP for TSMC 28nm Processes
“G”
Platform
(HKMG)
“LP”
Platform
(HKMG)
“LP”
Platform
(Si ON)
28HPM
Customer
Silicon
28HPC
Available
28HPL
Customer
Silicon
28LP &
28LP+/28LE
Customers
Taped out
2014/
2015
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Comprehensive ARM Platform for TSMC28HPM/28HPC
Optimization
Criteria
Logic IP
Products
Memory Compiler
Products
ARM CPU &
GPU POP
Ultra High Density
Balanced
Density/Performance
High Performance
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Develop higher* performance 28nm SoCs with
same or reduced leakage
Performance Gain with ARM Platform for 28HPC
*Compared to existing 28HPM products
Improved and expanded POPTM offering adding
latest ARM 64bit CPU and GPU processors
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Achieve smaller* SoC die area due to new and
enhanced logic and memory architectures
Power/Cost Reduction with ARM Platform for 28HPC
*Compared to existing 28HPM products
Increased flexibility/ finer grained tuning in
controlling SoC leakage v/s performance
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Traditional on chip variation (x% OCV)
approach may be too conservative due to
excess design margin
Change in Sign Off Methodology for 28HPC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3sig
ma
of
de
lay d
iffe
ren
ce
path depth
intercept=margin
To address this, ARM libraries will support
SB-OCV with new de-rating tables per cell
(along with hold variation modeling)
rf_type: rise
derate_type: late
depth: 1 2 3 4 5 6 8 10 20 30 40 50
60 80 100
distance:
table: 0.8713 0.8979 0.9123 0.9199 0.9259
0.9306 0.9379 0.9433 0.9581 …
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Predictable Results
The New Paradigm of Cortex® -A Implementation Success
Predictable Time-Line
in a
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Implementation Targets
High-Performance
Mobile Cluster
(big)
Cortex-A57 MP2/4,
Fmax
Low-Power
Cluster
(LITTLE)
Cortex-A53 MP4,
Low-Power
High Performance
Server/Networking/
Enterprise
Cortex-A57 MP4 +
ECC,
Fmax
Low-Power
Server
Cortex-A53
MP4+ECC,
Fmax
LITTLE
big
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ARM POP IP : Solving ARMv8-A CPU Implementation Problems on 28nm
Premium
SoC Problems
Complexity of 64-bit CPU implementation - 64-bit CPUs need more engineering & compute resources
- ARM Cortex-A57 run-time in several days
“Winner takes all” – time-to-market is very important
Flexible
solution
Address a wide
variety of market
segments
Reduce Risk
Leverage ARM
expertise
Reduce
Development
Cost Phy. IP + Scripts +
Implementation
Knowledge
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ARM POP IP Enables New Era of Partnership
SoC
Designer
EDA
Scripts
EDA
Flow
Foundry
Process
Optimization
Implementation
Support
RTL
Optimization
ARM
Cortex-A
CPU
ARM
POP IP
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Accessing ARM 28HPC Physical IP on DesignStart™
http://www.arm.com/products/designstart
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Summary: ARM 28HPC Physical IP offers …
Higher performance 28nm SoCs with same or reduced leakage
Improved and expanded POP offering
Smaller SoC die area with new logic and memory architectures
Increased flexibility in SoC performance v/s leakage tuning
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Thank You
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