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2.4GHz Fast Hopping Frequency Synthesizer
A thesis submitted to
The Hong Kong University of Science and Technology
in partial fulfilment of the requirements for
the Degree of Master of Philosophy in
Electrical and Electronic Engineering.
By
Wong Ming Yip Wallace
Department of Electrical and Electronic Engineering
B.Eng (Elec)
January, 1999
2.4GHz Fast Hopping Frequency Synthesizer
By
Wong Ming Yip WallaceApproved by:
____________________________Dr. Jack LauThesis Supervisor
____________________________Prof. Philip ChanThesis Examination Committee Member (Chairman)
____________________________Dr. Philip Mok
____________________________Prof. Philip ChanHead of Department
Department of Electrical and Electronic Engineering
The Hong Kong University of Science and Technology
January, 1999
2.4GHz Fast Hopping Frequency Synthesizer
By
Wong Ming Yip Wallace
for the Degree of theMaster of Philosophy in Electrical and Electronic Engineeringat The Hong Kong of University of Science and Technology
in January, 1999
Abstract
A 2.4GHz frequency synthesizer is proposed as a part of a low cost RF front end for ISM
band applications. The frequency synthesizer employed a new dual loop architecture to
improve the settling time, while keeping a fine frequency resolution.
With a settling time of 30µs, the frequency synthesizer is able to hop at 2k hop/s with less
than 10% overhead. When utilized in a digital wireless system, the fast hopping rate is able to
improve the efficient of the coding scheme and improve the performance of the system.
The frequency synthesizer includes a monolithic LC tank VCO with a phase noise perform-
ance of -94.728dBc/Hz, -113.2dBc/Hz and -118dBc/Hz at 100kHz, 600kHz and 1MHz offset
respectively, with an innovative varactor design, the VCO is able to achieve a tuning range of
600MHz, from 1.8GHz to 2.4GHz. When designed in a 0.35µm CMOS technology, the syn-
thesizer drew 40mA from a 3V supply.
Acknowledgments
The completion of this thesis would have been impossible without the intellectual and physi-
cal support from many individuals. During the last five years, I have been growing to be an
educated as well as cultivated person. I have to thanks for every person who have shared their
time, experience and knowledge with me.
Firstly, I would like to thank my thesis supervisor, Dr. Jack Lau, not only for his technical
and financial support, but also for sharing his valuable experience and his intellectual matu-
rity with me. Next I would like to thank for the people in the Consumer Media Laboratory
and UMAN group, who had discussed with me varies issues in related to my Thesis. Special
thanks go to Frankie Hui, who had provided a great due of technical support during my
research. I would also like to thank Prof. Philip Chan and Dr Philip Mok for sitting on my
thesis committee.
I would like to extend my appreciation to Mr Jack Chan and Mr Siu-Fai Luk for the help in
layout submission to MOSIS, Mr Joe Lai for sharing his experience in using varies RF equip-
ments.
Last but not the least, I would like to thank my parents for their support and love.
CHAPTER 1 INTRODUCTION 1
Phase Locked Loop Frequency Synthesis 2
Frequency Hopping Wireless Audio System 4
Overview 6
CHAPTER 2 PHASE-LOCKED LOOP 7
Linear Model of Phase-locked Loop 7
Second order loop 9
Passive Loop filter 9
Active loop filter 10
Loop filter with charge-pumping phase detector 11
Closed-loop response 12
Frequency synthesizer 17
Dual loop architecture 19
CHAPTER 3 HARDWARE IMPLEMENTATION 23
Voltage Controlled Oscillator 23
Oscillator Theory 24
Spiral inductors 27
Varactor 30
Voltage Controlled Oscillator 41
Mixer 52
Prescaler 54
Phase detector 60
Loop Simulation 62
CHAPTER 4 CONCLUSION 63
REFERENCES 65
3
12
2
o
tion
nt
nt
aci-
9
Figure 1. A general block diagram of a RF receiver 2
Figure 2. A block diagram of a phase-locked loop frequency synthesizer
Figure 3. The wireless audio system 4
Figure 4. Frame structure of the RS code 5
Figure 5. Linear model of a phase-locked loop 7
Figure 6. Passive lag-lead loop filter 9
Figure 7. Current feedback active loop filter 10
Figure 8. Passive loop filter to realize a) type I system and b) type II system
Figure 9. Open loop transfer function 15
Figure 10. Typical output spectrum of a PLL 16
Figure 11. Frequency divider in a “VCO” 17
Figure 12. Dual-loop architecture using vernier effect 19
Figure 13. Improved dual loop architecture 20
Figure 14. Matlab simulation result for the dual loop frequency synthesizer 2
Figure 15. An LC tank oscillator 25
Figure 16. Conversion of noise around integer multiples of the oscillating frequency int
phase noise 27
Figure 17. A spiral inductor 28
Figure 18. Model of a spiral inductor 29
Figure 19. Substrate model 29
Figure 20. a) a PN junction varactor, b) an PMOS capacitor varactor and c) an accumula
-mode varactor 31
Figure 21. Cross-sectional view of the gated varactor 32
Figure 22. Simplified MEDICI simulation showing the carrier concentration under differe
gate bias 34
Figure 23. Simplified MEDICI simulation showing the carrier concentration under differe
drain bias 35
Figure 24. The carrier concentration of the varactor when reaching its a) maximum cap
tance and minimum capacitance 37
Figure 25. Measured capacitance under different bias 3
4
46
9
0
0
0
61
Figure 26. Measured Q-factor of the varactor 40
Figure 27. VCO fabricated in HP 0.35mm process 42
Figure 28. Capacitance tuning characteristic 43
Figure 29. Tuning characteristic of the VCO with HP process 43
Figure 30. The output spectum of VCO with the HP process 4
Figure 31. Schematic of 2.4G Hz VCO with TSMC process 45
Figure 32. The measured impedence of the inductor a) real part, b) imginary part.
Figure 33. Measured Q factor of the inductor 47
Figure 34. Extracted inductance 47
Figure 35. Phase noise plot, carrier frequency = 2.419GHz 4
Figure 36. Phase noise plot, carrier frequency = 2.020GHz 5
Figure 37. Phase noise plot, carrier frequency = 1.770GHz 5
Figure 38. The tuning characteristic of the VCO 51
Figure 39. The die photo of the 2.4GHz VCO 51
Figure 40. Mesurement setup of the VCO 52
Figure 41. Gilbert Cell mixer 53
Figure 42. 512 to 768 programmable frequency divider 55
Figure 43. Timing diagram of a 8 to 12 divider 55
Figure 44. Divide 2/3 circuit 57
Figure 45. Implementation of NOR/flip flop in current steering logic 57
Figure 46. Differential to single end converter 58
Figure 47. D flip flop by TSPC logic 58
Figure 48. The digital comparator used in this work 59
Figure 49. Simulation of the divider 59
Figure 50. Phase/Frequency detector implementation 6
Figure 51. Charge pump circuit 61
Figure 52. Simulation output of the phase detector and charge pump circuit
Figure 53. Simulation of the dual loop architecture 62
Table 1. Summary of loop filter feedback and transfer function 11
Table 2. Summary of Second-Order Loop Equations 13
Table 3. Summary of Inductors used 46
Table 4. Phase noise measurement at 2.4GHz 48
has
ne has
g, the
sing
ters
wire-
less
uency
Reed-
CHAPTER 1 Introduction
Since the first demonstration by Guglielmo Marconi in 1901, the wireless technology
been gone through dramatic changes in the past 20 years. The cost of the cellular pho
been lowered dramatically in the past decade. As the technology keeps on advancin
wireless transmission is no longer limited to voice communications. There is an increa
popularity in wireless applications such as wireless Local-Area-Network, wireless prin
and wireless speakers. The market is demanding for a lower cost and more integrated
less devices.
The motivation of this study is to design a CMOS frequency synthesizer for indoor wire
applications. The frequency synthesizer is designed to meet the needs of a 2.4GHz freq
hopping wireless audio system which transmits MPEG compressed audio sources with
Solomon error protection coding scheme.
1
Phase Locked Loop Frequency Synthesis
y an
e RF
and
sig-
y ref-
power,
nsi-
1.1 Phase Locked Loop Frequency Synthesis
FIGURE 1. A general block diagram of a RF receiver
Figure 1 displays a general block diagram of a receiver. The RF signal is picked up b
antenna. The signal is filtered and amplified by a RF filter and a low noise amplifier. Th
signal is then down converted to the an intermediate frequency (IF) for further filtering
down converting. The local oscillator (LO) signal which is used to down convert the RF
nal to the IF signal is usually generated by a frequency synthesizer from a low frequenc
erence. Phase-locked loop frequency synthesizers have the advantages of low
feasibility of monolithic implementation and phase coherence during frequency tra
tions[1].
LO
LNA IF
2
Phase Locked Loop Frequency Synthesis
chro-
om-
ses is
tor N
usu-
fre-
FIGURE 2. A block diagram of a phase-locked loop frequency synthesizer
Figure 2 shows a block diagram of a phase-locked loop frequency synthesizer. The syn
nized oscillator is usually a voltage controlled oscillator (VCO). The phase detector c
pares the output of the frequency divider and the reference. The difference in their pha
computed ase, and the signale is filtered to produceu which controls the oscillator. The loop
provides a feedback to keep the frequency of the output of the synchronized oscilla
times the frequency of the reference. In a frequency synthesizer, the dividing radio, N, is
ally variable. Variation in N allows the synthesizer to synthesis a LO signal of different
quencies of channel selection.
LoopFilter
PhaseDetector
ReferenceOscillator
Synchronized
/ N
e u
3
Frequency Hopping Wireless Audio System
opping
PEG
itted
ed data
1.2 Frequency Hopping Wireless Audio System
FIGURE 3. The wireless audio system
The frequency synthesizer described in this thesis is designed as part of a frequency h
wireless audio system. Audio data with data rate of 1411.2kbps is compressed into M
audio with data rate of 128kbps. The MPEG audio is protected by RS code and transm
through the wireless channel. The RS encoded data rate is 250.81875kbps. The encod
is framed. A frame consists of 819 bytes and with a duration of 26.123ms.
RF module
RF moduleRS decoding
RS coding
Rayleigh faying channel
Mpeg audio
Mpeg audio
4
Frequency Hopping Wireless Audio System
into
mn is
s of a
erfer-
at the
cy to
s than
FIGURE 4. Frame structure of the RS code
In order to maximize the efficiency of the RS coding scheme, each frame is interleaved
63 columns with each column contents 13 RS symbols and 2 test symbols. Each colu
transmitted at a different frequency channel. This topology ensures not all the column
frame is transmitted through a deep fade channel or a channel which is occupied by int
ences. The received data is reconstructed and the missing columns are recovered
decoder from the received columns.
With a frame rate of 26.123ms, the hopping rate,hrate, is calculated as
(1)
The required settling time for the frequency synthesizer to translate from one frequen
another frequency has be to less than 1/10 of the frame duration in order to achieve les
10% overhead, i.e., less than 50µs.
...
Test symbols
13 RS symbols
63 columns
hrate26.123ms
63-----------------------
1–
2400hop/s≈=
5
Overview
al to
, the
fre-
fre-
that
LC
enta-
bri-
ed a
z at
d. A
The settling time of a phase-locked loop frequency synthesizer is inversely proportion
the loop bandwidth, which in turns limited by the frequency of the reference. However
frequency of the reference is limited by the minimum frequency step of the output of the
quency synthesizer. A typical loop with a carrier frequency of 2.4GHz and a minimum
quency step of 200kHz requires a settling time of 150µs.
1.3 Overview
A new architecture which allows fast frequency hopping is proposed, simulation shows
the architecture is able to achieve a settling time of 30µs. A 2.4GHz monolithic LC tank
VCO is designed and fabricated. To overcome the problem of limited tuning range in
tank VCO, a gated varactor, which has a wider tuning range than other existing implem
tions, is proposed. An intensive study in monolithic inductor is also conducted. The fa
cated VCO achieved a tuning range of 600MHz from 1.8GHz to 2.4GHz and achiev
phase noise performance at 2.4GHz of -94.7dBc/Hz, -113dBc/Hz and -118dBc/H
100kHz, 600kHz and 1MHz offset respectively.
Besides, the VCO, others building blocks in the frequency synthesizer is also studie
complete loop simulation has been performed. When designed in a 0.35µm CMOS technol-
ogy, the synthesizer drew 40mA from a 3V supply.
6
Linear Model of Phase-locked Loop
ic of a
y of a
nse of
in by
CHAPTER 2 Phase-locked Loop
To understand the operation of a phase-locked loop frequency synthesizer, the bas
phase-locked loop is described in this section. A phase-locked loop filters the frequenc
signal. A transfer function can be used to describe the transients and frequency respo
the “filter”. The transfer function of a phase-locked frequency synthesizer can be obta
replacing parameters in the transfer function of a phase-locked loop.
2.1 Linear Model of Phase-locked Loop
FIGURE 5. Linear model of a phase-locked loop
KvcosKd F(s)
θθ i o
7
Linear Model of Phase-locked Loop
utput
tector
.
a low
ter. In
ance.
utput
nd of
nd or
Figure 5 presents a linear model of a phase-locked loop. The input,θi, of the phase-locked
loop is the phase of the reference frequency. The output,θo, of the loop is the phase of the
oscillator of the phase-locked loop. The phase detector compares the input with the o
and produces a signal by multiplying the difference of the two phases with the phase de
gain,Kd. The phase detector converts the phase information into a voltage or a current
The signal produced by the phase detector is passed to the loop filter, which is usually
pass filter. The characteristic of the phase-locked loop greatly depends on the loop fil
later sections, we are going to discuss how the filter shape influences the loop perform
The voltage controlled oscillator transfers the voltage to frequency. By integrating the o
frequency, we obtain the phase of the output. The VCO is modelled by a integrator,Kvco/s.
The VCO gain,Kvco is in the unit of radian per volt.
The closed-loop transfer function of the phase-locked loop is
(2)
where (3)
Due to the 1/s in the VCO’s linear model, a phase-locked loop is at least order of 1 a
type I. The loop order depends on the order of the loop filter.
order of loop = order of loop filter +1 (4)
First order loop provides only one degree of freedom for designers, hence, the seco
higher order loop is usually preferred.
H s( )θo
θi-----
G s( )1 G s( )+---------------------= =
G s( ) KdF s( )Kvco
s-----------=
8
Second order loop
this
rder
r to
while
ows a
nents
t low
ype II
phase
mp,
error.
2.2 Second order loop
As discussed in previous section, the order of the loop is determined by the loop filter. In
section, we are going to study some of the filter types. The loop filter of a second o
phase-locked loop can be an active filter or a passive filter. Active filter allows the filte
provide DC gain and also allows the poles and the zeros to have wider range of value,
the passive filter has the advantage of simplicity. A charge-pumping phase detector all
near integrator response while allows the filter to be implemented by passive compo
only.
A phase-locked loop, due to the present of the VCO, is at least type I. Additional poles a
frequency may change the system type. The primary difference between type I and t
loop is the nature of the phase error. In response to a frequency step, the steady-state
error of a type I loop will change but that of type II will not. In response to a frequency ra
the type I loop has an ever increasing phase error and type II loop has a steady phase
2.2.1 Passive Loop filter
FIGURE 6. Passive lag-lead loop filter
R1
C
vu
R2
9
Second order loop
filter
tem,
n the
e of
The general form of the passive filter is shown in Figure 6. The transfer function of the
is shown in equation (5) to (6).
(5)
(6)
The pole of the filter,ωp, is located at1/(R1+R2)C, and the zero,ωz, is located at1/R2C. The
passive filter, while simple and easy to implement, cannot provide DC gain to the sys
results a type I system.
2.2.2 Active loop filter
The values for pole and zero in a passive filter are limited to have the pole higher tha
zero. The active loop filter provides the possibility of providing gain and a wider rang
values for the pole and zero.
FIGURE 7. Current feedback active loop filter
F s( ) vu---
1 R2Cs+
1 R1 R2+( )Cs+---------------------------------------= =
1 sωz-----+
1 sωp------+
----------------=
R1u v
FBZ
G
10
Second order loop
e
nt of
detec-
xima-
ith a
The general block for a current feedback active loop filter is shown in Figure 7.G is the
transconductance of the amplifier.ZFB is a generic feedback. The transfer function of th
loop filter is shown in equation (7).
(7)
Some implementations are summarised in Table 1 [2], whenF(s) is the transfer function of
the filter.
TABLE 1. Summary of loop filter feedback and transfer function
Integrator and integrator and lead type loop filter result in a type II system due to prese
additional integrator. While Lag-lead filter gives a similar system as the passive filter.
2.2.3 Loop filter with charge-pumping phase detector
A charge-pumping phase detector provides a high output impedance. When the phase
tor drives a capacitor, it produces a near integrator response. It provides a better appro
tion to an integrator than a active filter and provides infinite lock-in range to the loop. W
ZFB F(s) ωp ωz
Integrator (1+G)R1C --
Integratorand lead
-- 1/R2C
Lag 1/RpC --
Lag-Lead (R2+Rp)C R2C
F s( ) vu---
ZFB s( )
R1 1 1G----+
-------------------------= =
1Cs------
Gs ωp⁄( )
------------------
R21
Cs------+ 1
R1C----------
1 s ωz⁄+
s---------------------
Rp
1 RpCs+-----------------------
Rp
R1------
11 sRpC+-----------------------
Rp R1 1 Cs( )⁄+( )Rp R1 1 Cs( )⁄+( )+-------------------------------------------------
Rp
R1------
1 s ωz⁄+
1 s ωp⁄+----------------------
11
Second order loop
ty of
filter
real-
nc-
charge-pumping phase detector, the lock-in range is only limited by the tuning capabili
the VCO.
A charge-pumping phase-detector outputs a current rather than a voltage, the loop
transfers the current input to a voltage output. The filters and their transfer functions to
ize the type I and type II system are shown in Figure 8.
FIGURE 8. Passive loop filter to realize a) type I system and b) type II system
The transfer function of the filter in Figure 8 a) is shown in equation (8). The transfer fu
tion of the filter in Figure 8 b) is shown in equation (9).
(8)
(9)
2.2.4 Closed-loop response
Given the loop filter response as equation (10).
(10)
The closed-loop transfer function of the PLL is given as equation (11).
v
R1C
I
a)
v
R1
I
C1
C2
b)
VI----
R1
1 sR1C+----------------------=
VI----
1s C1 C2+( )---------------------------
1 sR1C2+
1 sR1C1C2( ) C1 C2+( )⁄+-----------------------------------------------------------------=
integrator lead-lag filter
F s( ) KLF
1 s ωz⁄+
1 s ωp⁄+----------------------=
12
Second order loop
ua-
t
rized
ly
t
(11)
whereK=KdKLFKVCO
Comparing the denominator ofH(s) with the denominator of a standard second order eq
tion.
(12)
whereζ is the damping factor andωn is the natural frequency. From this it is apparent tha
(13)
(14)
The equations can be further simplified by taking approximation. The results are summa
in Table 2[2].
TABLE 2. Summary of Second-Order Loop Equations
To provide an optimally flat frequency response,ζ is usually greater than 0.5 and preferab
equal to [3]. The loop bandwidth,ωn, of a phase-locked loop is limited by the inpu
FilterType Lag Lag-Lead
Integrator andLead
H(s)
ζ
ωn2
H s( ) Kωp
1 s ωz⁄+
s2 sωp 1 K ωz⁄+( ) Kωp+ +-------------------------------------------------------------------=
s2 2ζωns ωn2+ + s2 ωp 1 K ωz⁄+( )s Kωp+ +=
ωn2 Kωp=
ζ 12---
ωp
ωn------
ωn
ωz------+
=
ωn2 1
s2 2ζωns ωn2+ +
--------------------------------------- ωn2 1 s ωx⁄+
s2 2ζωns ωn2+ +
---------------------------------------
12---
ωp
ωn------
12---
ωp
ωn------
ωn
ωz------+
12---
ωn
ωz------
Kωp K pKv
R1C-------------
1 2( )⁄
13
Second order loop
o be
an a
. The
e
frequency, it is shown in [3] that for type II phase-locked loops the loop bandwidth has t
limited to roughly 1/10 of the input frequency.
The transfer function for the charge-pump type II system is a third order loop rather th
second order loop, the transfer function of the loop is different from a second order loop
open loop gain of the loop isG(s)=KpdF(s)Kvco, whereKpd is the phase detector gain,Kvco is
the VCO gain andF(s) is given in equation (9). Definer1 andr2 as in equation (15)[5] and
equation (16)[5] and,G(s)can be calculated in terms of frequency, ω, the filter time constant
τ1 andτ2, and the design constantsKpd andKvco as shown in equation (17)[5]. The phas
margin is determined in equation (18)[5].
(15)
(16)
(17)
(18)
τ1 R1
C1 C2⋅C1 C2+-------------------⋅=
τ2 R1 C2⋅=
G s( )s jω=
K– pdKvco 1 jωτ2+( )
ω2C1 1 jωτ1+( )--------------------------------------------------
τ1
τ2----=
φ ω( ) 180° ωτ21–
tan ωτ11–
tan–+=
14
Second order loop
, we
e
s can
] and
FIGURE 9. Open loop transfer function
The open loop transfer function is plotted in Figure 9. To maximize the phase margin
want the unity gain frequency,ωp, to be at the inflection point of the phase plot. By taking th
derivative and set the derivative to zero, we get equation (19)[5]. And the time constant
be expressed in terms of the phase margin and loop bandwidth as in equation (20)[5
equation (21)[5]. By settingG(ωp)=1, the values of theR1, C1 andC2 follow as equation (22)
to equation (24)[5].
(19)
(20)
(21)
(22)
(23)
0dB
-180
-90
Phase margin
ω p
ωp 1 τ1τ2( )⁄=
τ1
φpsec φptan–
ωp----------------------------------=
τ21
ωp2τ1
--------------=
C1
K pdKvcoτ1
ωp2τ2
--------------------------1 ωpτ2( )2+
1 ωpτ1( )2+----------------------------=
C2 C1
τ1
τ2---- 1–
=
15
Second order loop
y, the
refer-
utput
sup-
he fre-
onents
z, i.e.
(24)
The loop filter is completely specified by the two parameters,ωp and φ.
The closed-loop response of the PLL is of low pass. As the input frequency varies slowl
loop responses rapidly to the changes and tracks the variation. When locking to a clear
ence, the phase-locked loop rejected the close-in phase noise of the VCO. A typical o
spectrum of a PLL is shown in Figure 10. The close-in phase noise of the oscillator is
pressed by the loop. The phase noise of the output follows the VCO’s phase noise as t
quency offset from the carrier increases. In practise, noise generates in the loop comp
raises the out band noise level by a few dB. Phase noise is usually measured in dBc/H
the noise power per hertz when compared with carrier power.
FIGURE 10. Typical output spectrum of a PLL
R2
τ2
C2------=
Typical shapes of oscillator phase noise
Phase noise of a closed loop
nω
16
Frequency synthesizer
ced by
fre-
O in
ltiples
tion of
Phase noise peaking occurs at frequency offset approximately equal toωn. The peaking
occurs due to the overshooting in a second order system. The overshooting can be redu
increasingζ to close to 1.
2.3 Frequency synthesizer
The block diagram of the frequency synthesizer is shown in Figure 2. A phase-locked
quency synthesizer can be represented by substituting the circuit of Figure 11 for the VC
the phase-locked loop. The output frequency,fout, is equal to theffb × N, andffb is locked to
the reference frequency.
FIGURE 11. Frequency divider in a “VCO”
For an integer-N frequency synthesizer, the output frequency is forced to be integer mu
of the reference frequency. Hence the reference frequency defines the frequency resolu
the frequency synthesizer which is usually the channel spacing.
fout
ffb
Kvco’ 1/N
Kvco=Kvco’/N
17
Frequency synthesizer
e syn-
utput
e is
nd
ution.
ease
ssion
ency
izer a
is a
Another important feature of the frequency synthesizer is the transients response of th
thesizer. As the dividing radio, N, changes, the synthesizer takes a finite time for the o
frequency to settle within an acceptable margin around the final frequency. The finite tim
defined as settling time of the system.
The settling time,ts, of the synthesizer is inversely proportional to the loop bandwidth, a
the value is given in equation (25)[3], whereα is the settling accuracy, andP is defined in
equation (26)[3].
(25)
(26)
The loop bandwidth, as discuss in previous section, is defined by the frequency resol
As a result the settling time is limited by the frequency resolution. It is desirable to incr
the loop bandwidth of the loop. Higher the loop bandwidth allows a better noise suppre
and improves the settling time.
Another problem in integer-N synthesizer is the large dividing ratio magnifies the frequ
offset of the reference by N times. For example a 1MHz reference is used to synthes
2.4GHz LO. The dividing ratio is 2400. For a 10ppm crystal, in the worst case, there
10Hz offset at the reference frequency, the LO frequency offset is 10 × 2400 = 24kHz.
ts1
ζωn--------- P
α 1 ζ2–-------------------------ln≈
Pstep size
original frequency--------------------------------------------=
18
Dual loop architecture
ger-N
izers
n
cil-
ther
, which
2.4 Dual loop architecture
The relationship between the channel spacing and the reference frequency of the inte
phase-locked synthesizers can be altered by employing two or more loops.
FIGURE 12. Dual-loop architecture using vernier effect
A dual-loop architecture shown in Figure 12 is proposed in [4]. Two frequency synthes
generates outputs atf1=f0+kfref1 and f2=f0-kfref2. The two signals are mixed to produce a
output frequency offout=2f0+k(fref1-fref2). The output frequency resolution is equal tofref1-
fref2, while fref1 andfref2 can remain large.
The primary difficulty exists for the architecture in Figure 12. Both the oscillators are os
lating at frequency which is very close to each other and may experience “pulling”. Ano
disadvantage is the mixer generates cross products of the harmonics and creates spurs
may fall into the desired band.
Loop 1 Loop 2
f1=f0+kfref1
fout=2*f0+k(fref1-fref2)
f2=f0-kfref2
19
Dual loop architecture
syn-
,
iffer-
g
be
lement.
FIGURE 13. Improved dual loop architecture
An improved dual loop architecture is shown in Figure 13. A secondary loop is used to
thesize output atfout2=fref2 × N. The fout2 mixed with the VCO output of the primary loop
lower pass filtered and feedback to the prescaler. The output of the mixer which is at d
ence of the two VCOs output frequencies is locked toM × fref1. Hence at the output of the
primary VCO, we havefout=M × fref1 + N × fref2. If fref2=fref1+fstep, thenfout=(M+N) × fref1
+ N × fstep. By maintainingM+N = constant, the output frequency can be varied by varyin
N.
In this architecture, the output frequencies of the VCOs are different and “pulling” can
avoided. Furthermore, the prescalers are running at lower speed and are easier to imp
PD LF VCO
Precaler
fref2
PD LF VCO
Precaler
fref1
M
N
fout2=fref2 x N
fout=Mxfref1+Nxfref2
20
Dual loop architecture
efer-
is
im-
n in
0
Also cross products of the mixer can be avoided by careful frequency planning. The r
ence offset is also magnified by smaller number by reducing the dividing ratio.
The following configuration is used in our system.
1. fref1 = 1.65MHz
2. fref2 = 2.15MHz
3. fstep = fref2 - fref1 = 500kHz
4. M = 513 - 768
5. N = 513 -768
The required tuning range of the primary VCO isfomin= (Mmax+ Nmin) × fref1+ Nmin × fstep
= 2.370GHz tofomax=(Mmin+Nmax) × fref1+Nmax× fstep= 2.498GHz, whereMmin is mini-
mum value ofM, Mmax is the maximum value ofM, Nmin is the minimum value ofN and
Nmax is the maximum value ofN. The required tuning range of the secondary VCO
fo2min=Nmin × fref2 = 1.1G Hz tofo2max=Nmax× fref2 = 1.6512GHz. The reference frequency
is increased from 500kHz to 1.65MHz and 2.15MHz. The choice of M and N is mainly l
ited by the tuning range of the secondary VCO.
The dual loop architecture is simulated in Matlab. The input of the primary VCO is show
Figure 14, the simulation result shows that the settling time improved to be less than 3µs.
21
Dual loop architecture
etec-
tector.
FIGURE 14. Matlab simulation result for the dual loop frequency synthesizer
The ripples at the input of the VCO after settling is generated by the XOR type phase d
tors used in the simulation. The ripples can be reduced by using other type of phase de
The ripples result in sideband spurs at the output of the VCO.
0 2 4 6
x 10−5
−1
−0.5
0
0.5
1
1.5
22
Voltage Controlled Oscillator
the-
its for
fabri-
e
tun-
rm-
to the
ency
CHAPTER 3 HardwareImplementation
In this chapter, varies building blocks of the loop is discussed. Building blocks of the syn
sizer include the RF VCOs, mixer, high speed prescalers, some high speed digital circu
control purposes and charge-pumping phase detectors. Some of the building blocks is
cated and tested in a 0.35µm Digitial CMOS technology. The difficulties for designing th
building blocks are discussed. The proposed solutions, which include an innovative wide
ing range varactor, are presented.
3.1 Voltage Controlled Oscillator
The high performance voltage controlled oscillator (VCO) is a key issue for high perfo
ance frequency synthesizer. Ideally, a VCO generates a frequency that is proportional
input voltage. When a voltage is applied to the input of the VCO, the output of the frequ
can be written as equation (27).
(27)V t( ) A ω0t φ t( )+( )sin=
23
Voltage Controlled Oscillator
-
ely
ad in
r dif-
One
ation
ent.
tors.
ver-
s the
the
vative
tank
rs at
y, the
phase
whereφ(t) is a time independent function. However,φ(t) is usually a random process, it intro
duces jitter on the total phase, which creates phase noise inV(t). The phase noise is usually
characterized in terms of single sided spectral noise density.
Monolithic LC-tank CMOS oscillators with on-chip spiral inductors have been intensiv
studied to improve the phase noise performance[6][7]. Challenges, however, still lie ahe
achieving reliable monolithic VCOs. For one thing, the process variation makes it rathe
ficult to accurately produce a VCO with the right centre frequency and tuning range.
possibility is to enhance the tuning range of the LC-tank so as to offer some compens
over process variation. In a LC-tank VCO, a varactor is primarily used as the tuning elem
Thus, the tuning range of the VCO is strongly related to the tuning range of the varac
The traditional PN junction varactor is quite limited in the tuning range. One way to o
come the problem is to employ a switched tuning VCO[8]. Such an approach increase
circuit complexity and may not be preferred. Alternatively, innovation can be made with
varactor itself. Accumulation-mode varactors with a tuning range of±30% and nominal
capacitance of 1pF and 3.1pF have been reported[9][10]. We have proposed a inno
wide tuning range varactor in [11][12] achieving±50% in tuning range with nominal capaci-
tance of 1.5pF.
3.1.1 Oscillator Theory
Before we further discuss on the new varactor. The oscillator theory is revised. An LC-
oscillator is a feedback network with an LC tank as the feedback circuit. Oscillation occu
the frequency at which the loop transfer function is 1 and have zero phase shift. In realit
loop transfer function is always designed to have value greater than 1, but have zero
24
Voltage Controlled Oscillator
ear
] as
e tun-
shift at the oscillating frequency. The amplitude of oscillation is usually limited by nonlin
effects.
FIGURE 15. An LC tank oscillator
For the oscillator shown in Figure 15. The oscillation conditions are shown by [13
(28),(29) and (30).
(28)
(29)
(30)
From equation (30), if we increase the value ofC, the power consumption of the VCO
increases, but the action improves the tuning range.
The major criteria of an oscillator is to have good phase noise performance. Besides, th
ing range and the tuning characteristic is also critical for an oscillator.
GM
RL
+
-
Rp
Rc
C
L
Vout
ω01
LC------------=
Reff Rc Rl1
Rp ω0C( )2⋅-----------------------------+ +=
GM Reff ω0C( )2⋅=
25
Voltage Controlled Oscillator
on-
. The
wn in
arrier
the
noise
g cur-
con-
ever,
e total
noise
An oscillator is a periodically time varying system. The time varying nature of the VCO c
verts the noise around integer multiples of the oscillating frequency into phase noise
major noise sources are noise generated in transistors in theGmcell and the thermal noise by
varies resistance in circuit. A detail analysis on the effect of varies noise source is sho
[14]. The noise generated by a transistor is shown in equation (31). Due to the hot c
effect, the value ofγ in equation (31) can be as high as 3 in a short channel devices, whileγ is
around 2/3 for long channel devices.gdo is the channel conductance and is defined as
resistance at the drain node atVds=0. gdo is a function ofW, LandVgs.
(31)
To improve the phase noise, we should increase the ratio of the carrier power to the
power. One way to do it is to increase the size of the transistors and reduces the biasin
rent. Keepinggdo constant, the thermal noise generated by the transistors are kept at a
stant level, but the1/f noise reduces due to the increase in the total gate area. How
increasing the gate dimension, the gate capacitance contributes a larger portion of th
capacitance required for oscillation, the tuning range reduced.
Another noise source is the thermal noise of the series resistance of the inductors. The
generates by the a resistor is shown in equation (32).
(32)
i noise2 4KTγ gd0 K
I a
f b-----∆f+=
vnoise2 4KTR=
26
Voltage Controlled Oscillator
on-
lation
y pre-
To minimize the noise power generated by the series resistance, theQ factor of the inductor
should be maximized.
FIGURE 16. Conversion of noise around integer multiples of the oscillating frequency into phase noise
3.1.2 Spiral inductors
The phase noise and power consumption of an oscillator greatly depends on theQ factor of
the inductors. Higher theQ factor, better the noise performance and lower the power c
sumption.
On-chip inductors are realized as spiral inductors. The basics for the inductance calcu
of these planar spiral inductors were developed by Greenhouse in 1974[15]. The theor
dicts the inductance within±5%.
ω 0 ω 02X
27
Voltage Controlled Oscillator
ortant
limit
18.
FIGURE 17. A spiral inductor
The resistive losses in the substrate and low self-resonant frequency are the most imp
limitations in using planar spiral inductors in a standard CMOS process. These factors
the value of inductors to be at 2-10nH withQ-factor of 2-8 at 2GHz whereQ is defined as
A model for a spiral inductor with the substrate effect proposed in [16] is shown in Figure
Cox, Csi andRsi are used to model the substrate effect. TheQ-factor of the inductor is shown
in [16] as in equation (33).
(33)
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����������������������������
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��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
Via Oxide
Substrate
Top Layer of Metal
Second Layer of Metal
Im Z{ }Re Z{ }----------------- X
R----=
QωLs
Rs---------
Rp
Rp ωLs( ) Rs⁄( )2 1+[ ] Rs⋅+--------------------------------------------------------------------× 1
Rs2 Cp Cs+( )
Ls------------------------------– ω2Ls Cp Cs+( )–
×=
Substrate Loss Factor Self-Resonance Factor
28
Voltage Controlled Oscillator
odel.
ces to
whereRp andCp are the extracted parallel resistance and capacitance of the substrate m
The value ofRp andCp are shown in equation (34)
(34)
FIGURE 18. Model of a spiral inductor
FIGURE 19. Substrate model
If the substrate loss factor and the self resonance factor are set 1, equation (33) redu
, the two factors are always smaller than 1. TheQ factor of the inductor can be
improved by reducingCox.
Rp1
ω2Cox2 Rsi
----------------------RsiCox Csi
2+
Cox2
------------------------------+= Cp Cox
1 ω2 Cox Csi+( )CsiRsi2+
1 ω2 Cox Csi+( )2Rsi2+
----------------------------------------------------------⋅=
Cs
Ls RsCox Cox
Rsi RsiCsi Csi
Cox
Rsi Csi
Rp Cp
QωLs
Rs---------=
29
Voltage Controlled Oscillator
f the
ner is
ually
h
inner
r coils
ploy-
io.
causes
large
d the
0.
To reduceCox, we can either reduce the thickness of the oxide or reduce the total area o
inductor. Since the oxide thickness is limited by the process, the only choice for a desig
to reduce the total area of the inductor. However, reducing the area of the inductor, us
results in reducingLs or increasingRs, both factors reduce theQ factor by reducing the first
term in equation (33). There exist some metal width, at which theQ factor of the inductor is
maximized.
Intensive studies in maximize theQ of the inductor [6][13][16] have suggested that widt
metal width is not efficient. Besides hollow coils show be used. The resistance of the
coils increase enormously due to eddy currents induced by the magnetic flux. The inne
contribute little to the total inductance while contribute a lot to the series resistance. Em
ing hollow inductor design, maximizes theQ by increasing the inductance to resistance rat
The magnetic flux also penetrates through the substrate and induces eddy current and
energy lost. Large coils induce flux penetrates deeper into the substrate. Hence very
coils are not efficient.
3.1.3 Varactor
Commonly used varactors include the PN junction varactors, the PMOS varactors an
accumulation-mode varactors. The structures of these varactors are shown in Figure 2
30
Voltage Controlled Oscillator
The
d by
de a
sistor.
f the
lation-
mula-
e/
FIGURE 20. a) a PN junction varactor, b) an PMOS capacitor varactor and c) an accumulation -modevaractor
The PN junction varactor consists of a P+ and an N+ region residing in an N-Well.
depletion region is formed between the P+ region and N-Well. The tuning range provide
a PN junction varactor varies with the doping profile. Typical PN junction varactors provi
±10% tuning range. The PMOS varactor utilizes the gate capacitance of a PMOS tran
While providing a wider tuning range than the PN junction varactors, the tuning range o
PMOS varactors is limited by the source and drain parasitic capacitance. In an accumu
mode varactor, the N+ contacts replace the source and drain of a PMOS varactor. Accu
tion-mode varactors achieve a tuning range of±30% after the removal of the parasitic sourc
drain capacitance.
a) N+ P+ N+
N-Well
������
b) P+ P+
N-Well
������
N+ N+c)
N-Well
31
Voltage Controlled Oscillator
tran-
e con-
g only
r pro-
tact is
ode is
as the
The gated varactor structure is shown in Figure 21. The structure is similar to a PMOS
sistor except that the drain node is replaced by an N+ contact. The gated varactor can b
sidered to be a combination of the three varactor structures mentioned above. Replacin
the drain node by an N+ region while keeping the source node as P+, the gated varacto
vides a wider tuning range by varying the source capacitance.
FIGURE 21. Cross-sectional view of the gated varactor
The new structure is a three terminal device. The first terminal connected to the N+ con
defined as the drain node. The gate node is connected to the poly-silicon gate. The P+ n
defined as the source node. In this study, the capacitance of the device is defined
capacitance looking into the drain node. These notations are shown in Figure 21.
����
��������������������������������������������
��������������������������������������������
����������������������������������������������������������������������������������������
����������������������������������������������������������������������������������������
������������������������������������������������
������������������������������������������������
����������������
P+
N-Well
SourceDrain
N+
Gate
Drain
Gate
Source
32
Voltage Controlled Oscillator
drain
and the
apaci-
ce, and
offer a
ractor
quire
I, is
cess.
f-
in the
ary-
g the
the
rtant
gate
The capacitance can be varied by changing the potential difference between either the
node and the gated node, or the drain node and the source node. The characteristics
physics behind the gated varactor are discussed in later sections of this paper. The c
tance consists of several capacitances —the gate capacitance, the junction capacitan
some parasitic. Due to the presence of these capacitances, the gated varactor is able to
higher capacitance per unit area than the other implementations. The implemented va
records a capacitance per unit area of 2.875 fF/µm2.
The new structure is fully compatible with the standard CMOS process, and does not re
any post-processing.
In order to understand the operation of the varactor, a device simulation tool, MEDIC
used to simulate the carrier concentration of the device with a standard bulk CMOS pro
N-Well doping concentration of 1.2× 1017 cm-3 is set. The structure is simulated under di
ferent biasing condition. The simulation is used to develop a set of theories that expla
operation of the device.
The experiment was divided into two parts. In the first part, we examined the impact of v
ing the voltage at the gate node. In the second part, we examined the effect of varyin
voltage at the drain node. In both cases, the source node was connected to ground.
The simplified MEDICI simulation results are shown in Figure 22. In order to improve
readability of the simulation results, we redrew the diagrams and showed only the impo
information of the simulation. Figure 22 shows the carrier concentration under different
33
Voltage Controlled Oscillator
nts the
var-
nd the
gate
drain
cture,
drain
n the
row 1
e and
es the
nction
biasing. The drain and the source node are grounded. The darkened region represe
depletion region. The depletion region shrinks as the voltage at the gate increases.
FIGURE 22. Simplified MEDICI simulation showing the carrier concentration under different gatebias
The operation of the gated varactor is similar to the operation of the accumulation-mode
actor. Increasing the gate voltage moves the varactor towards the accumulation mode a
capacitance increases.
In Figure 23, a similar diagram with the drain biased at different voltage is shown. The
node and the source node are grounded while the drain voltage is varied. Varying the
voltage has two impacts on the device. Despite the finite resistance of the N-Well stru
the drain node and the N-Well should have roughly the same potential. Increasing the
voltage increases the potential of the N-Well. And as the potential difference betwee
gate and the N-Well reduces, the device moves into inversion mode. This is shown by ar
in Figure 23. The depletion region extends as the device moves towards inversion mod
reduces the capacitance that looks into the drain node. As the drain voltage increas
potential across the PN junction also increases. The depletion region across the PN ju
VgC
��������
N+ P+
depletion region
N-Wellshrinks as Vg increasesdepletion region
34
Voltage Controlled Oscillator
region
arrier
t the
oint, a
hich
at the
apaci-
er the
some
ion
widens, and the capacitance further reduces. One may notice that the depletion
extends at the subsurface region of the N-Well at which the gate loses control of the c
concentration. This phenomena is similar to the sub-surface DIBL effect and occurs a
lower doping region at the subsurface. When the drain voltage increases to a certain p
depletion region which formed underneath the gate merges with the depletion region w
formed at the subsurface. The capacitance looking into the drain reaches its minimum
point.
FIGURE 23. Simplified MEDICI simulation showing the carrier concentration under different drainbias
The total capacitance of the gate primarily consists of three components: the gate c
tance, the junction capacitance and some parasitic. While the first two components off
varactor the ability to tune its capacitance, the last component limits the capacitance at
finite value. The maximum capacitance can be estimated by equation (35).
(35)
Ctotal is the total capacitance that looks into the drain.Cox is the oxide capacitance.Cj is the
junction capacitance andCmin includes the overlapping capacitance, the interconnect
C
depletion region
N+ P+
N-Well
��������
2
1
Ctotal Cox Cj Cmin+ +=
35
Voltage Controlled Oscillator
. When
ed, the
f the
f Cox,
imum
surface
ads to
ases.
gated
capacitance and the other parasitic capacitance that may appear at the drain node
reaching its minimum capacitance, due to the subsurface depletion phenomena describ
Cox andCj offer little capacitance to the total capacitance. The minimum capacitance o
varactor is roughly equal to the qualityCmin.
Compared with the accumulation-mode varactor, which has a maximum capacitance o
the gated varactor offers a higher total capacitance. When the varactor reaches its min
capacitance, the depletion region at the subsurface. This depletion enables the sub
region, which cannot be depleted by controlling the gate voltage, to be depleted, and le
a lower minimum capacitance. Figure 24 shows the carrier concentration of these c
Essentially, with a higher maximum capacitance and lower minimum capacitance, the
varactor allows a wider tuning range.
36
Voltage Controlled Oscillator
r-
meters
as con-
tracted
from
)
FIGURE 24. The carrier concentration of the varactor when reaching its a) maximum capacitance andminimum capacitance
A testing varactor was fabricated using a 0.35µm digital CMOS process. The measured va
actor consists of 100 segments with total gate dimension of 500µm by 0.4µm, The size of
each segment including the gate, source and drain is 5µm × 1.6µm. Fingering reduces the
gate resistance. The measurement was done by a network analyzer. The 2-port S-para
were measured with the drain node and the gate node as the ports. The source node w
nected to the ground port. The capacitance and the resistance values were finally ex
from the 2-port S-parameters. The admittance looking from the drain was calculated
equation (36), while the equivalentRp and capacitanceCeqwas calculated as in equation (37
and (38).
������������������������������������������������������������������������������������������������������������������������
������������������������������������������������������������������������������������������������������������������������
����������������
����������������
depletion region
depletion region
����������������
N+ P+
N-Well
a) Maximum Capacitance
N+ P+
N-Well
��������������������
b) Minimum Capacitance
37
Voltage Controlled Oscillator
e and
ltage
(36)
(37)
(38)
The extracted capacitance is shown in Figure 25 with the x-axis showing the gate voltag
the family of curves representing the capacitance measured with the drain biasing vo
varying from 0V to 4V with a 1V step. With an oxide thickness,tox, of 7.5nm, junction bot-
tom capacitance,Cjo, of 9.3× 10-4 F/m2, and junction sidewall capacitance,Cjsw, of 2.1× 10-
10 F/m and gate to drain parasitic capacitance,Cgdo of 4.7 × 10-10 F/m, the capacitances are
calculated as in equation (39) to equation (41).
(39)
(40)
(41)
Y Y0
1 S11–
1 S11+----------------=
Rp Re y( ) 1–=
CeqIm y( )2πf
--------------=
CoxεAtox------=
0.94pF=
where A 500µm 0.4µm×=
Cj Cjo Asource× Cjsw w×+=
0.66pF=
where Asource 500µm 1.2µm×=
Cmin Cgdo w Cpad Cinter+ +×=
0.55pF=
where Cpad Cinter+ 0.3pF≈
38
Voltage Controlled Oscillator
eas-
the
ithin
ilar
o the
effect
alcu-
FIGURE 25. Measured capacitance under different bias
TheAsourceis the area of the source node,w, the gate width is 500µm in our varactor.Cpad
andCinter is estimated by multiplying the metal area with the capacitance per unit area m
ured. Substituting the values in equation (35), we getCmax=2.15pF andCmin=0.55pF. 0.66pF
of the total capacitance is provided by the PN junction which is roughly about 30% of
total tuning range. Compared with the measured values, the equation is correct w
±10%. If one of the curves in Figure 25 is looked at, the behaviour of the varactor is sim
to an accumulation-mode varactor. When the drain voltage is varied, the curves shift t
right and experience a reduction in the minimum capacitance. This corresponds to the
of driving the device to inversion mode with subsurface depletion. The tuning range is c
−4 −3 −2 −1 0 1 2 3 4Vg
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
Cap
acita
nce
Increasing Vd
Vd=0V
Vd=1V
Vd=2V
Vd=3V
39
Voltage Controlled Oscillator
ieves
log
e
istance.
ination
lated with equation (42). With a center capacitance of 1.5pF, the fabricated varactor ach
a tuning range of ±53%, from 0.7pF to 2.3pF.
(42)
TheQ factor of the varactor is shown in Figure 26. In the graph both axes are shown in
scale. The measuredQ value, when measured, exceeded 20 at 2GHz. A capacitorCeq with a
parallel resistorRp and a series resistorRs represent a simplified model for the varactor. Th
series resistance includes the contact resistance, gate resistance and the N-Well res
The parallel resistance is an equivalent resistance related to the generation-recomb
current, diffusion current and surface leakage current. For a given bias,Q varies aωCeqRp at
low frequency and as 1/ωCeqRp at high frequency.
FIGURE 26. MeasuredQ-factor of the varactor
tuning range12---±
Cmax Cmin–
Cmax Cmin+-----------------------------=
1 10frequency (GHz)
10
Q fa
ctor
Vd=2V
Vd=1V
Vd=0V
40
Voltage Controlled Oscillator
-
tal.
d the
erse
The
ifying
tional
tank
urces
ifting
odes
ons
e N-
revious
accu-
apaci-
gain
3.1.4 Voltage Controlled Oscillator
Two voltage controlled oscillators are fabricated in 0.35µm CMOS processes which is pro
vided by HP and TSMC. Both VCOs have inductors fabricated with the third layer of me
Gated varactors are used as the tuning element. A circuit topology is developed to utilize
third terminal to maximize the tuning range. The topology forces the varactors to trav
across the family of curves in Figure 25, while keeping the VCO as a single input block.
oscillators with gated varactors can be used in a phase-locked loop system without mod
the system architecture to accumulate the third terminal which is not presented in tradi
VCOs.
The schematic of the VCO fabricated in the HP process is shown in Figure 27. The LC
consists of inductors of 2nH. The drain nodes of the varactors are biased at 1V. The so
of the varactors are connected to the output of a source follower to provide a level sh
from the tuning voltage. The tuning voltage also controls the voltage bias of the gate n
directly. The level shifting of 1.5V provided by the source follower prevents the PN juncti
of the varactors from forward biasing.
WhenVtune is set to 0V, the PN junctions are reverse biased at 1V and the potential of th
Wells (drain node voltage) is lower than the gate by 0.5V. When the tuning voltage,Vtune,
increases, the voltage across the drain and the source nodes drops. As discussed in p
sections this action increases the capacitance of the varactor. At the same time, asVtune
increases, the gate voltage also goes up. This drives the device from inversion mode to
mulation mode and the capacitance further increases. With both actions moving the c
tance to the higher capacitance region, this circuit topology provides maximum VCO
41
Voltage Controlled Oscillator
e in
nven-
y the
also
and tuning range. The capacitance tuning characteristic is shown with a solid lin
Figure 28. The capacitance of the varactor is now varied by one tuning voltage as in co
tional varactors.
Long channel devices are used in the tuning source follower. The noise injected b
NMOS transistors can be described by equation (31). Using long channel devices
increases the gate area and hence reduces the 1/f noise.
FIGURE 27. VCO fabricated in HP 0.35µm process
Vtune
2nH 2nH
104u/0.4u104u/0.4u
70u/2u
7.5mA
42
Voltage Controlled Oscillator
var-
FIGURE 28. Capacitance tuning characteristic
The tuning characteristic of the VCO is shown in Figure 29. The frequency of oscillation
ies by 320MHz with a 1.4V variation in the tuning voltage.
FIGURE 29. Tuning characteristic of the VCO with HP process
−4 −3 −2 −1 0 1 2 3 4Vg
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
Cap
acita
nce
0 0.5 1 1.5Tuning Voltage (V)
1.7
1.8
1.9
2
2.1
Fre
quen
cy (
G H
z)
Increaseing Vd
Utilizing configurationmentioned above
Family of curves showingthe VCO frequency at differentVg and Vd.
43
Voltage Controlled Oscillator
wer,
The
ffset.
. The
ctor
ted by
rease
e
sche-
le 3
The VCO, excluding the output buffers, draws 7.5mA from a 3V supply. The output po
when driving a 50 ohm loading through a source follower is measured to be -6dBm.
phase noise is measured to be -87dBc/Hz at 100kHz offset and -105dBc/Hz at 1MHz o
FIGURE 30. The output spectum of VCO with the HP process
In order to improve the phase noise performance of the VCO, the VCO is redesigned
current bias for the tuning source follower is reduced from 1mA to 50uA and a new indu
is designed. The reduction in bias current of the source follower reduces the noise injec
the tuning circuit. The values of the inductors are increased from 2nH to 3.7nH. The inc
in inductor values reduced the capacitance required for oscillation and reduces thGm
required for oscillation, as a result, the noise injected by the transistors reduces. The
matic of the VCO is shown in Figure 31. The tuning circuit is not shown in the figure. Tab
summarized the inductors used in the two runs. In the table,w is the width of the metal lines,
44
Voltage Controlled Oscillator
igned
34.
nted
effect
n in
s’ 1/f
cant.
s is the separation between the metal lines,z is the number of segments used.A is the length
of the innermost metal line andL is the calculated inductance of the inductor.
The measured inductance of the new inductor is 3.8nH, when compared with the des
value 3.7nH, the difference is less than 3%. The measuredQ is 3.5 compared with simulated
Q of 2 in the previous run. The measurement results are shown in Figure 32 to Figure
.
FIGURE 31. Schematic of 2.4G Hz VCO with TSMC process
A 70 ohm tail resistance is used to adjust the DC bias of the VCO output. When impleme
with poly-silicon, the resistance introduces a tail capacitor and a tail noise source. The
of the tail capacitor and tail noise source in a LC tank VCO is studied in [17]. It is show
[17] that only the noise around even harmonics of the oscillating frequencyf0 and at low fre-
quency have a significant effect on the phase noise. At low frequency, the transistor
noise dominates and the 1/f noise produced by the poly-silicon resistance is not signifi
Furthermore, the poly-silicon resistance is made up by a piece of 8µm × 70µm poly-silicon,
6mA
3.7nH 3.7nH
64u/0.4u 64u/0.4u4u/0.4u70 Ohm
3.7nH3.7nH
45
Voltage Controlled Oscillator
it. At
filter-
the large area of the poly-silicon resistance reduces the 1/f noise injected into the circu
high frequency, the tail capacitance introduced by the large poly resistance provides a
ing to the high frequency noise produced.
TABLE 3. Summary of Inductors used
FIGURE 32. The measured impedance of the inductor a) real part, b) imaginary part.
HP TSMC
w(µm) 30 12
s(µm) 1.2 1.2
z 16 20
A(µm) 50 60
L(nH) 2 3.7
Q factor 2 3.5
a) b)
Measured data with probe pad attracted
deembedded data
frequency (GHz) frequency (GHz)
46
Voltage Controlled Oscillator
n
FIGURE 33. Measured Q factor of the inductor
FIGURE 34. Extracted inductance
The phase noise spectrum of the VCO at the 1/f2 region can be calculated as equatio
(43)[14].
(43)
frequency (GHz)
frequency (GHz)
indu
ctan
ce (
H)
phase noise at offset of∆ω 102FkT
Ps--------------
ωo
2Q∆ω----------------
2
⋅log⋅=
47
Voltage Controlled Oscillator
n,
V
half.
dBc/
d by
4. The
ulated
r fre-
VCO
wherePs is the average power dissipated in the resistive part of the tank,F is known as the
device excess noise number andQ is theQ factor of the LC tank. For steady-state oscillatio
By equating .Vmaxis simulated to be increase from 400mV to 1
andGm is reduced by half by reducing the both the basing current and the W/L ratio by
The factorPs is 3 times in the new VCO. The estimated improvement in phase noise is
(44)
The fabricated VCO records a phase noise of -94.728dBc/Hz, -113.2dBc/Hz and -118
Hz at 100kHz, 600kHz and 1MHz offset respectively at 2.4GHz. The figures are obtaine
averaging the measurement results of 5 measurements. The data is shown in Table
phase noise improvement at 1M Hz is -13dB. The 4dB difference in measured and calc
phase noise improvement is mainly due to the derivation in fitting parameter,F.
TABLE 4. Phase noise measurement at 2.4GHz
With the gated varactor, the tuning range of the VCO is as wide as 600MHz, the carrie
quency is able to tune from 2.419GHz to 1.77GHz. However, the phase noise of the
100k Hz offset 600k Hz offset 1M Hz offset
-95.67dBc/Hz -112.85dBc/Hz -117.83dBc/Hz
-94.17dBc/Hz -113.88dBc/Hz -118.83dBc/Hz
-95.00dBc/Hz -112.50dBc/Hz -119.00dBc/Hz
-95.17dBc/Hz -112.00dBc/Hz -119.50dBc/Hz
-93.63dBc/Hz -114.00dBc/Hz -119.00dBc/Hz
Ps12---
Vmas2
R-----------⋅ 1
2--- Vmax
2 Gm⋅ ⋅= =
Improvement in phase noise 10
ωo1
ωo2
--------
2
Ps1
Ps2
-------Q1
Q2------
2
⋅--------------------------log=
10
2.4G2G
------------
3Ps
Ps-------- 3.5
2-------
2
⋅----------------------------- 9dB–=log=
48
Voltage Controlled Oscillator
meas-
and
c/Hz, -
noise
degrades rapidly when the carrier frequency is tuned to below 2GHz. The phase noise
ured at 2GHz is -94.00dBc/Hz, -108.67dBc/Hz and -113.67dBc/Hz for 100kHz, 600kHz
1MHz offset respectively. The phase noise measured at 1.77GHz is recorded as -81dB
105.00dBc/Hz and -108dBc/Hz at 100kHz, 600kHz and 1MHz respectively. The phase
plots of the measurements are shown in Figure 35 to Figure 37.
FIGURE 35. Phase noise plot, carrier frequency = 2.419GHz
49
Voltage Controlled Oscillator
ed to a
ces the
FIGURE 36. Phase noise plot, carrier frequency = 2.020GHz
FIGURE 37. Phase noise plot, carrier frequency = 1.770GHz
The performance of the phase noise degrades mainly due to the PN junctions are bias
point close to forward bias, the leakage current across the varactor increases and redu
Q factor of the varactors.
50
Voltage Controlled Oscillator
n in
The tuning characteristic of the VCO is shown Figure 38, and the die photo is showFigure 39. The measurement setup of the VCO is shown in Figure 40.
FIGURE 38. The tuning characteristic of the VCO
FIGURE 39. The die photo of the 2.4GHz VCO
0 0.5 1 1.5 2 2.5 3voltage(V)
1.8
2.3
freq
uenc
y(G
Hz)
1.8
2.3
Tuning characteristic2.4GHz VCO
51
Mixer
cy by
mixer
fre-
we
ffers
to the
tion
ut of
FIGURE 40. Measurement setup of the VCO
3.2 Mixer
In our synthesizer, a mixer translates the output of the 2.4GHz VCO to a lower frequen
a secondary frequency that is synthesized by the secondary loop. The output of the
consists of two frequencies,fo-f1 and fo+f1 where fo is the frequency of the output of the
2.4GHz VCO andf1 is the secondary frequency generated by the secondary loop. The
quency,fo+f1, should be filtered out by a low pass filter. However, in our architecture,
have the advantage of the two frequencies,fo-f1 andfo+f1, are very far apart. The filtering can
be done relatively easy. In our circuit, the low pass characteristic of the mixer and the bu
followed by the mixer are used to suppress the higher frequency components. Due
absence of the interference, the linearity of the mixer is not important. However, isola
between ports are still very important. In sufficient isolation results in spurs at the outp
the synthesizer.
To spectrumAnalyzer
VCO die
on-chip buffer
balun
10nH
10nH
1pF
1pF
Vtune
52
Mixer
h is
od
vice
fre-
ize of
In order to achieve high port-to-port oscillations, double balanced Gilbert cell mixer, whic
shown in Figure 41, is used. The fully differential structure of Gilbert cell provides go
port-to-port isolation. In practice, the mixer suffers from a finite feed through due to de
mismatch.
Due to the large output bandwidth required for the mixer, the mixer is operating at a
quency that is out of its 3dB bandwidth. The value of the loading resistance and the s
the transistors are selected to provide enough gain to drive the following stages.
FIGURE 41. Gilbert Cell mixer
f0+
f0 -
+f1 f1-
3k
32u/0.4u 32u/0.4u
64u/0/4u
0.8mA
out+
out-
53
Prescaler
ma-
nput
t
tially,
e out-
t-
f the
3.3 Prescaler
The architecture requires two prescalers work up to 1.6GHz with dividing ratio program
ble from 513 to 768. The architecture of the divider is shown in Figure 42. The 1.6GHz i
is feed into a dual-module prescaler. When themodeis set to high, the prescaler triggers a
every three input cycles, otherwise the prescaler triggers at every two input cycles. Ini
the prescaler is at divide-by-two mode. The counter counts the number of triggers at th
put of the prescaler, when the number of trigger is greater or equal to theexternal control, the
modeis set high. The dividing ratio of the circuit is equal to (768-b), whereb is the binary
number at theexternal control.
To understand the operation of the prescaler, the timing diagram of a 9 to 12 divider is shown
in Figure 43. Theb is set to 3. The output is dividing at a ratio of (12-3=9). The divider ou
put is the same as the MSB for the counter.
In the divider, the operation frequency of the 2/3 prescaler is 1.6 GHz. The remainder o
divider works at 800MHz or below.
54
Prescaler
8] is
ula-
ately
FIGURE 42. 512 to 768 programmable frequency divider
FIGURE 43. Timing diagram of a 8 to 12 divider
The dual module prescaler is implemented by D flip flops. A prescaler proposed in [1
shown in Figure 44. The circuit is modified such that each flip flop has a fanout of 2. Sim
tions indicate that this technique increases the maximum operating speed by approxim
clk
mode
out in
count
MSB
outin1
in2
Digitial comparator
8
8
8bit counter
divider output
external control
2/3 prescaler
1.6G input
10 10 10 10 10 10 10 10 10 10 10 10
100 1 100 1 100 1
100 10 0 1 1 100 10 0 1 1
1 2 3 4 5 6 7 8 9 10 11 12
100 1 0 0 0 01 1 1 1
1 1 10 0 0 0 1
100 10 0 1 10 0 0 0 0 0 0 0 0 01 1 1 1 11
Input
MSB
mode
LSB
coun
t
prescaler output
55
Prescaler
own
caler
nder
d by
f the
high.
para-
it is
mption
28.
o
ces
80M
fre-
lica-
40%. The D flip flops are implemented with current steering logic. The schematic is sh
in Figure 45. The NOR gates are embedded in the flip flops. The output of the pres
drives a differential to single ended converter to produce rail-to-rail swings for the remai
of the divider.
The remainder of the divider is implemented in TSPC logic. The schematic of a D flip flop
implemented in TSPC logic is shown in Figure 47. The counter is a ripple counter forme
a chain of D flip flops.
The digital comparator compares the input from the counter with an external input. I
input from the counter is greater or equal to the external input, the comparator outputs a
Given the advantage of the output of the counter is monotonically increasing. The com
tor is implemented by circuit shown in Figure 48. Since the asynchronous circu
employed, a glitches remover is inserted. The glitches remover works base on an assu
that the glitches have much shorter duration than the actually pulses.
The simulation result of the divider is shown in Figure 49. The divider is set to divide at 7
The measured period of the output is 5.17852× 10-7s. The input frequency is 1.4GHz. The
dividing ratio is 5.17852× 10-7 × 1.4GHz = 725. Due to the delay in circuit the dividing rati
is offseted by 3. The offset is constant for dividing ratio from 513 to 765. The offset redu
the number of available channel by 3 from 256 to 253. For complete coverage of the
ISM band, the reduction in available channel reduces the frequency resolution. The
quency resolution reduces from 80M/256=312.5kHz to 80M/253=316kHz. In our app
56
Prescaler
effect
tion, the channel width is 500kHz, hence the reduction in frequency resolution has notin our application.
FIGURE 44. Divide 2/3 circuit
FIGURE 45. Implementation of NOR/flip flop in current steering logic
D QD Q
inputMode
out
1k 1k
32u/0.4u
32u/0.4u
32u/0.4u
12u/0.4u 12u/0.4u
16u/0.4u
64u/0.4u64u/0.4u
64u/0.4u64u/0.4u
1.5mA
Out
CLK CLKP
VREFA
B
57
Prescaler
FIGURE 46. Differential to single end converter
FIGURE 47. D flip flop by TSPC logic
16u/0.4u16u/0.4u
8u/0.4u 8u/0.4u
4u/0.4u 4u/0.4u1.2u/0.4u
3.6u/0.4u
3.6u/0.4u
1.2u/0.4u
in+ in-
output
300uA
Qp
D
Clk
58
Prescaler
FIGURE 48. The digital comparator used in this work
FIGURE 49. Simulation of the divider
8
8
8
8
In
External Control Dflipflop
DClk
Q
Reset
Glitches remover
Delay
SymbolWaveD0:A0:v(o)
Vol
tage
s (li
n)
0
200m
400m
600m
800m
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
Time (lin) (TIME)0 50n 100n 150n 200n 250n 300n 350n 400n 450n 500n 550n 600n 650n 700n 750n 800n
DeltaX=5.1786e-07
Panel 3
59
Phase detector
liers
omple-
uces
hown
ly, the
pump
3.4 Phase detector
FIGURE 50. Phase/Frequency detector implementation
An implementation of the phase/frequency detector is shown in Figure 50. Unlike multip
and XORs, the phase/frequency detectors (PFDs) generate two outputs that are not c
mentary. If the frequency of input A is greater than that of input B, then the PFD prod
positive pulses at UP, while DOWN remains at zero. Conversely, if fA < fB, then positive
pulse is generated at DOWN.
The outputs of the PFD can drive a three-state charge pump. A charge pump circuit is s
Figure 51. When UP is high, the charge pump circuit charge up the capacitor. Converse
charge pump circuit discharge the capacitor when DOWN is high.
The simulation output of the PFD and charge pump is shown in Figure 52. The charge
is driving a capacitor.
D
CLK
Q
D
CLK
QB
A
RESET
UP
DOWN
60
Phase detector
FIGURE 51. Charge pump circuit
FIGURE 52. Simulation output of the phase detector and charge pump circuit
0.5mA
UP
DOWN
OUT
SymbolWaveD0:A0:v(loopfilter)
Volta
ges
(lin)
0
50m
100m
150m
200m
250m
300m
350m
400m
450m
500m
550m
600m
650m
700m
750m
800m
850m
900m
950m
1
Time (lin) (TIME)0 50n 100n 150n 200n 250n 300n 350n 400n 450n 500n 550n 600n 650n 700n 750n 800n
* pd
Charge Pump PFD
60ns
28ns80ns
38ns
A
B
61
Loop Simulation
es
ves a
ps are
nthe-
set-
3.5 Loop Simulation
To complete the loop, the loop filter is designed to be off chip. Off chip loop filter giv
designer the flexible to define the features they want. The design of the loop filter invol
trade off between reference sidebands and settling time. The loop bandwidth of the loo
designed to be 1/10 of the reference frequency for both stability and fast locking. The sy
sizer is simulated with a designed filter. The input of the VCO is shown in Figure 53. The
tling time of the synthesizer is less than 30µs.
FIGURE 53. Simulation of the dual loop architecture
SymbolWaveD0:A0:v(vcoin2)
Volta
ges
(lin)
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
1.2
1.3
Time (lin) (TIME)0 2u 4u 6u 8u 10u 12u 14u 16u 18u 20u 22u 24u 26u
2.4 ghz dual loop frequency synthesizer
62
ain-
sed.
is
The
uit the
ise is
om-
sfully
, the
/Hz, -
CHAPTER 4 Conclusion
A new architecture frequency synthesizer, which can improve the settling time while m
taining a fine output resolution of the synthesizer, for ISM band applications is propo
When implemented in a 0.35µm Digital CMOS technology, the synthesizer’s settling time
less than 30µs when hopped across the ISM band with frequency resolution of 500kHz.
synthesizer supports up to 253 channel locations. The synthesizer is designed to s
application for a wireless audio system.
One of the challenges of the design is to have wide tuning range VCO while phase no
also very straining. We have proposed a new innovative varactor with±50% tuning range,
which is significantly wider than any existing implementation. Wide tuning range also c
pensates for the process variation and improves the yield of the VCO. We succes
applied the varactor to a 2.4GHz VCO, resulting as a VCO with 600MHz tuning range
VCO when measured at 2.4GHz achieved a phase noise performance of -94.728dBc
113.2dBc/Hz and -118dBc/Hz at 100kHz, 600kHz and 1MHz offset respectively.
63
64
er-
less
ilter
zed
97.
8
-
tor
uits
References
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[4] Behzad Razavi, “Challenges in the Design of Frequency Sythesizers for Wire
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r in
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67