Multi-Functional Universal Device using a Band-Engineered Vertical Structure

Dong-Il Moon1, Jae-Sub Oh2, Sung-Jin Choi1, Sungho Kim1, Jee-Yeon Kim1,

Moon-Seok Kim1, Young-Su Kim2, Min-Ho Kang2, Jeoung-Woo Kim2, and Yang-Kyu Choi1*

1Department of EE, KAIST, 2National Nanofab Center, Daejeon 305-701, Korea Email: ykchoi@ee.kaist.ac.kr, Phone: +82-42-350-3477, Fax: +82-42-350-8565

Abstract A multi-functional universal device based on a vertical

channel is demonstrated as a total device solution. Four different operation modes: conventional MOSFET, steep slope FET, multi-faceted volatile memory (1T-DRAM and 1T-SRAM), and non-volatile memory are implemented in a single transistor. The steep slope FET and volatile memory are boosted by a vertically inhomogeneous doped channel for spatial energyband-engineering, and non-volatile memory capable of high performance and reliable operation is obtained via tunneling bandgap-engineering.

Introduction

The continued development of system-on-chip (SoC) is facing a growing number of challenges related to increased complexity, power consumption, manufacturing costs, and shorter design cycles. To address these issues and to promote flexibility in the application of this technology, multi-functional devices that incorporate transistors and embedded memory have been proposed [1-4]. Given this background, the integration of high performance transistors with low power consumption and hierarchical memory architecture with high capacity is required. However, challenging issues are still unresolved due to the trade-off between high performance and low power, as well as that between the memory capacity and the limit of the die size.

In this work, a universal device that combines a conventional MOSFET, a steep slope FET (SSFET), and unified memory is proposed as a basic building block for versatile SoC applications. A non-uniform doping concentration along a vertically standing Si pillar is designed for spatial energyband-engineering in the SSFET and volatile memory (VM) operation [5-6]. For the realization of a 4F2 unified memory that minimizes the area of an array, a cross-point cell consisting of a three-dimensional vertical channel transistor is experimentally demonstrated, as shown in Fig. 1. By virtue of the vertical cell structure, a floating body that inherently fulfills the function of VM is formed on a bulk substrate. Implementation of bandgap-engineered (BE)

tunneling dielectrics for a charge storage node enhances the non-volatile memory (NVM) characteristics [7]. The proposed concept can be realized through a universal device with an adjustment of the bias conditions, as shown in Fig. 2.

Device Fabrication

SEM and TEM images of the fabricated device and a summary of the process flow of the vertical structure are shown in Figs. 3, 4, and 5, respectively. Prior to the formation of a protruding Si pillar, three-step chain implantation was applied for S/D and inhomogeneous channel formation, i.e., deep for the source (S), shallow for the drain (D), and medium for the channel. Its doping profile, analyzed by SIMS, is shown in Fig. 4 (b). Note that the center of the Si pillar is doped with a high concentration of boron (δp+). It is expected that this inhomogeneous doped channel will enable SSFET operation and enhancement of VM characteristics. After the formation of the Si pillar, O1/N1/O2/N2/O3 for the BE technique and a metal-gate were sequentially stacked.

Results and Discussion

A. Normal and Steep Slope FET Characteristics: The measured output and transfer characteristics are shown in Fig. 6. It should be noted that the operation of the vertical channel FET can be separated into three modes according to VD. Firstly, the proposed device can work as a conventional MOSFET below VD of 1.1 V, which is attractive for long-term reliability. Secondly, by increasing the value of VD further, the subthreshold slope (SS) becomes steeper and the hysteresis between the forward and reverse scans becomes wider, as summarized in Fig. 7. The impact ionization (II) and BJT mode can be distinguished by the hysteresis window that can be represented by the gate controllability. This is clearly visible in Fig. 7 (c): the weak II leads to a significant charge of the floating body beginning with VD of 1.2 V. Accordingly, the value of SS is far below the physical limit of a conventional MOSFET at room temperature. In the II mode, the steep slope is primarily attained not by II but by the dynamic reduction of the threshold voltage (VT) because the holes generated by the

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weak II accumulate at the δp+ region and lower the potential barrier, as shown in Fig. 8. Therefore, the steep slope characteristic can be obtained at low VD; this was verified by numerical simulation, as shown in Fig. 8 (c). A further advantage of the spatial energyband-engineered FET is its low off-state (Ioff) leakage current, as the δp+ effectively suppresses the leakage. As a result, Ioff remains below the pA range and an Ion/Ioff ratio of 107 is realized with a gate range of 0.3 V. CMOS operations are plotted in Fig. 9. Excellent reliability with negligible hysteresis was confirmed by a stress test, as shown in Fig. 10. This SSFET is apt for low power applications. Thirdly, in the BJT mode, ID is abruptly increased with wide hysteresis by the activation of the parasitic BJT in the floating Si pillar; thus, a unique bistable state can be utilized for VM applications [8]. B. Volatile Memory Characteristics: Typical 1T-DRAM characteristics, described in an operational timing diagram, are shown in Fig. 11. A binary state is clearly distinguished in the vertical cell. It is noteworthy that the sensing current window (ΔIS) is sufficiently high to the point, such that a sense amplifier is not necessary to identify the data state. This remarkably simplifies the DRAM periphery circuit architecture. The range of available VD and VG biases for reliable memory operation was investigated, and the results are shown in Fig. 12. To evaluate the data hold retention characteristics, optimal VD was exploited. These results are plotted in Fig. 13. After the hold period, each memory state was successfully read out. Through the optimization of the bias conditions and the spatial energyband-engineering of the channel that is explained in Fig. 14, an excellent retention characteristic was achieved. The hold retention properties are mainly determined by the recombination of excess holes at the junction boundaries; thus, the higher doping concentration at the δp+ region does not affect the hold retention characteristic. Fig. 15 illustrates the P/R/E/R cycling endurance. After 1016 cycles, more than 50 % of ΔIS, compared to the value of a fresh device, was guaranteed. The cumulative curve of each data state in terms of endurance cycling is shown in Fig. 16. This notable endurance is an effect of the confined distribution of electrons with the aid of the δp+, as shown in Fig. 17. This gate protection mechanism can prevent carrier injection to the gate dielectric, and leads to significant lifetime improvement.

The read retention characteristics are shown in Fig. 18. An autonomous stable read operation that lasts longer than one hundred seconds was attained without a DRAM-like periodic refresh via the positive feedback of the BJT action. Therefore, the binary state is continually read out as long as power is supplied. One of the important advantages of the BJT read

method is the non-destructive readout, as it automatically recharges the body during the read operation. Moreover, multiple read operations are allowed without loss of the stored data, as shown in Fig. 19. Once the parasitic BJT is triggered and holes are charged in the floating body, pre-stored data are sustained in a stand-by (hold) state under VG of -2 V and VD of 0 V. These distinctive features greatly improve the operation speed, and can be used for 1T-SRAM applications. C. Non-Volatile Memory Characteristics: NVM functionality with programming/erasing (P/E) transient behaviors is shown in Fig. 20. P/E operation was performed with CHEI/HHI and FN tunneling to examine the operation for NOR and NAND applications, respectively. Regardless of the method used, a VT window that exceeded 3 V was achievable. Fig. 21 shows the reliability characteristics. Retention of ten years was deemed feasible given a VT window of 2 V. In addition, excellent P/E cycling endurance was attained after 10k cycles. By introducing the metal-gate and BE technique, excellent erase behavior with the FN method and good retention characteristics were achieved.

Conclusions Multi-functional device operation with a

three-dimensional vertical structure was demonstrated for low power design and 4F2 memory cell efficiency. A steep slope FET was realized via spatial energyband-engineering that also allowed the volatile memory to improve the data retention time with remarkable endurance of up to 1016. In a non-volatile memory application, the device showed excellent erase and retention characteristics using the bandgap-engineered structure. Thus, this band-engineered device provides a universal platform for SoC applications.

Acknowledgement

This work was supported in part by the IT R&D program of MKE/KEIT under Grant 10035320, by Nano R&D Program through the MEST under Grant 2009-0082583, and by the Samsung Electronics Company, Ltd.

References

[1] C. W. Oh et al., Symp. VLSI Tech. Dig., pp. 133-134, 2006. [2] J.-W. Han et al., IEDM Tech. Dig., pp. 929-932, 2007. [3] D.-I. Moon et al., IEDM Tech. Dig., pp. 284-287, 2010. [4] Z. Lu et al., IEDM Tech. Dig., pp. 407-409, 2010. [5] V. R. Rao et al., IEDM Tech. Dig., pp. 811-814, 1997. [6] U. Abelein et al., IEEE EDL, vol. 28, no. 1, pp. 65-67, 2007. [7] H. T. Lue et al., IEDM Tech. Dig., pp. 547-550, 2005. [8] S. Okhonin et al., IEDM Tech. Dig., pp. 925-928, 2007.

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Fig. 5 Process flow of the vertical cell structure. The sequence of the fabricationprocess is represented in numerical order. S/G and G/D are separated by theILD1 and ILD2 layers, respectively. The metal contact is made using tungsten.

Fig. 1 Schematic of a three-dimensional vertical universal device and 4F2 cellarray. Four different functional devices are integrated in a single transistor.Spatial energyband-engineering by high doping at the center of the Si pillarrealizes the SSFET and enhances the VM performance. The O1/N1/O2 servesas a non-trapping tunneling dielectric (bandgap-engineering) for NVM.

Fig. 4 (a) Cross-sectional TEM image (right) a long the b-b’ direction shown in Fig.3 (b) with a close-up view of the gate stack with BE layers (left). Ti/TiN/W for thegate electrode and O1/N1/O2/N2/O3 at 1.3nm/1.3nm/1.6nm/5.6nm/6.3nm for theNVM are formed. (b) A SIMS profile was obtained from the drain to the source.

Fig. 6 (a) ID-VD characteristics with various VG. The universal device acts as aconventional MOSFET. (b) Double sweep ID-VG characteristics with variousVD. As VD increases, SS becomes very steep (< 10 mV/dec). A wide hysteresiswindow at VD of 4 V occurs due to the activation of the parasitic BJT.

Fig. 2 Bias map of the universal device. With the separation of VD and VG,four distinguishable operations are realized without interference. The SSFETcan be used for low power applications. A memory hierarchy can beconstructed by the unified memory that covers SRAM (cache memory),DRAM (main memory), and NVM (storage).

Fig. 3 (a) Tilted SEM image of the Si pillar array. Oxide is used as a hardmask layer during Si etching. (b) In-line CD-SEM image after formationof the side wall gate. The Si pillar is surrounded by a metal gate. (c) ATEM image after BEOL across the a-a’direction shown in Fig. 3 (b).

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Fig. 7 (a) Subthreshold swing versus VD. (b) Hysteresis window (ΔV) versusVD. According to the transition point of SS and ΔV, the device operation isseparated into three parts. (c) Derivative of ID with respect to VD. At low VD,the device behaves like a conventional MOSFET. By raising VD, the electricalbehavior changes from conventional mode to impact ionization or BJT mode.

Fig. 8 (a) Band diagram before hole accumulation. (b) After holeaccumulation. The potential barrier at δp+ is lowered by the holes generated bythe weak II. (c) Simulated ID-VG characteristics of a non-uniform doping case(bottom x-axis) and a uniform doping case (upper x-axis). Steep slopebehavior is only observed in the δp+ doping case due to the reduction of VT.

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cycles. No significant degradation ofthe state ‘0’appeared during cycling.

Fig. 12 Available bias windows of (a)VG (WL) and (b) VD (BL) for thereading. Reliable read operation isconstrained by the unwanted BJTaction and leakage current.

Fig. 18 Read retention behaviors. Thestored states are sustained without lossfor more than one hundred seconds.Charge retainability is achieved due tothe non-destructive readout operation.

Fig. 11 (a) Operational bias conditions (table) and pulse waveform for theevaluation of the BJT-based 1T-DRAM operation. (b) Transient measurementof the vertical 1T-DRAM cell with a 5 nsec programming (write ‘1’) anderasing (write ‘0’) pulse time. The sensing margin, which is the difference ofthe read current between the state ‘1’and ‘0’, is nearly 40 μA/μm.

Fig. 13 Hold retention under variousVD. A retention time of 1 sec wasachieved in a VD range of 3.9 V to 4.2V. Retention is mainly enhanced due tothe effect of energyband-engineering.

Fig. 19 Multiple read operation with ahold interval. The negative VG holdsexcess holes in energyband-engineeredfloating body. The binary state isrepeatedly read out without failure.

Fig. 16 Cumulative distribution ofthe binary state. After 1010 cycles, anegligible reduction of the current,compared with that of fresh devices,was noted in the two states ‘1’ and ‘0’.

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Fig. 20 P/E transient characteristics of the BE vertical NVM for variousoperational conditions. (a) P/E is performed by CHEI/HHI for NORapplications. The erase method can be replaced by FN for reliable operation interms of endurance. (b) FN tunneling method is applied for NAND applications.

Fig. 21 Reliability characteristics of NVM based on FN for P/E. (a) Retentionand (b) endurance characteristics. Retention time is longer than ten years withVT window of 2 V, and endurance cycle is more than 104 P/E. The charge lossand gain are negligible due to the use of the bandgap-engineering technique.

Fig. 9 Numerically simulated transfercharacteristics of an n-type and a p-type MOSFET with δp+ doping. Steepslope behavior was confirmed in thecomplementary types of transistors.

Fig. 10 Hot carrier stress test underimpact ionization condition. After 100ksec, no significant degradation wasobserved in the forward and reversedirection scans.

Fig. 14 (a) The δp+ layer effectivelystores additional holes and preventsthe loss of holes at the junctionboundaries. (b) Recombination rate isnot affected by the highly doped δp+.

Fig. 17 Electrons flow near the gateinterface, but they spread out in thebulk after δp+ region. This effectivelyprotects the gate dielectric from thedamage and enhances the endurance.

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