237436528 Final Ie Lab Manual

7/18/2019 237436528 Final Ie Lab Manual

1/54

Industrial Electronics Lab Manual

CONTENTS

S.C.R.

CHARACTERIS

TICS 2

R, R-CAND

UJT

TRIE

RINCIRCUI

TS 5

SINLE!HASE

"ULL#

C$NTR

$LLED

C$N%E

RTER 12

M$N$S

TA&LE

MULTI%

I&RAT$

R 15

STUD#$"

ASTA&L

E

MULTI%

I&RAT$

R

USIN

IC ''' 18

INTERAT$R USINIC()* $!-AM!21

STUD# $" L$IC

ATES 23

REALI+ATI$N $"&ASIC ATES USIN

UNI%ERSAL ATES 28

LIHT DIMMER 30

S!EED C$NTR$L $"

DC SHUNT M$T$R. 32

1
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PERLINK%23page12http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page12http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page12http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page12http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page12http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page15http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page15http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page15http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page15http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page15http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page18http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page18http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page18http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page18http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page18http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page21http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page21http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page21http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page23http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page23http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page23http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page28http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page28http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page28http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page28http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page28http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page30http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page30http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page30http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page32http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page32http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page32http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page32http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page2http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page2http://var/www/apps/conversion/tmp/scratch_1/HYPERLINK%23page2


2/54


S.C.R.

CHARACTERISTICS

Aim: -

To stud

te %-I

caracte

ristics

o

S.C.R.

and

deter/i

ne te

&rea0

o1er

1olta2e,

on state

resistan

ce

Holdin2

current

3

Latcin

2current.

Appara

tus

require

d: -

SCR,!o4er

Su55lies

,

6atta2eResistor

s,A//ete

r,

%olt/et

er, etc.

Circuit

Diagra

m: -

Theory:-

Te Silicon

Controlled Rectiier

7SCR8 is si/5l a

con1entional rectiier

controlled b a 2ate

si2nal. Te /ain circuit

is a rectiier9 o4e1er

te a55lication o a

or4ard 1olta2e is not

enou2 or conduction.

A 2ate si2nal controls

te rectiier conduction.

Te rectiier circuit

7anode-catode8 as a

lo4 or4ard resistance

and a i2 re1erse

resistance. It is

controlled ro/ an o

state 7i2 resistance8 to

te on state 7lo4


3/54

resistanc

e8 b a

si2nal

a55lied

to te

tird

ter/inal

, te

2ate.

$nce it

is turned

on it

re/ains

on e1en

ater

re/o1al

o te

2ate

si2nal,

as lon2

as a

/ini/u

/

current,

te

oldin2

current,

I, is

/aintain

ed in te /ain or

rectiier circuit. To turn

o an SCR te anode-

catode current /ust be

reduced to less tan te

oldin2 current, I.

Notice te re1erse

caracteristics are te

sa/e as discussed

5re1iousl or te

rectiier or diode, a1in2

a brea0 o1er 1olta2e

4it its attendin2

a1alance current9 and a

lea0a2e current or

1olta2es less tan te

brea0 o1er 1olta2e.

Ho4e1er, in te or4ard

direction 4it o5en 2ate,

te SCR re/ains

essentiall in an o

condition 7notice tou2

tat tere is a s/all

or4ard lea0a2e8 u5

until te or4ard brea0

o1er 1olta2e is reaced.

At tat 5oint te cur1e

sna5s bac0 to a t5ical

2


4/54


or4ard

rectiier

caracte

ristic.

Te

a55licati

on o a

s/all

or4ard

2ate

1olta2e

s4itceste SCR

onto its

standard

diode

or4ard

caracte

ristic or

1olta2esless tan

te

or4ard

brea0

o1er

1olta2e.

rocedure: -

1. Connections are /adeas so4n in te circuit

dia2ra/.

2. Te 1alue o 2ate

current I, is set to

con1enient 1alue bad:ustin2 %.

3. & 1arin2 te anode-

catode su55l 1olta2e

%AA 2raduall in ste5-

b-ste5, note do4n te

corres5ondin2 1alues o

%A; 3 IA. Note do4n

%A; 3 IAat te instant

o irin2 o SCR and

ater irin2 7b reducin2

te 1olt/eter ran2es and

increasin2 te a//eter

ran2es8 ten increase te

su55l 1olta2e %AA.

Note do4n

corres5ondin2 1alues o

%A; 3 IA.

4. Te 5oint at 4icSCR ires, 2i1es te

1alue o brea0 o1er

1olta2e %&$.

5. A 2ra5 o %A; %


5/54

6. Te

onstate

resist

ance

canbe

calcul

atedro/

te

2ra5b

usin2

a or/ula.

7. Te 2ate su55l

1olta2e % is to be

s4itced o

8. $bser1e te a//eter

readin2 b reducin2te anode-catodesu55l 1olta2e %AA.

Te 5oint

3


6/54


at 4ic te a//eter readin2 suddenl 2oes to =ero 2i1es te 1alue o Holdin2 Current IH.

>. Ste5s No.?, @, ), ', , (, B are re5eated or anoter 1alue o te 2ate current I.

O!ser"atio# Ta!$e:-

%or&ard Characteristics 'atchi#g Curre#t Ho$di#g Curre#t

Ig( ).. *g()). I'(). Ig( ) *g() I'()

Sr #o

*A+ IA,

Sr #o IAmA

Sr #o IAmA

*o$ts

Co#c$usio#:-

1. SCR caracteristics as been studied and te or4ard brea0 o1er 1olta2e is ound out to

be 1olts.

2. Te obser1ed 1alues o oldin2 and latcin2 currents are . And

res5ecti1el.

3. SCR caracteristics a1e been dra4n ro/ te obser1ed 1alues o %A0and IA0.

4. "ro/ te 2ra5 it is clear tat ater or4ard brea0do4n 1olta2e SCR starts conductin2

and tere is a sudden decrease in te 1olta2e across SCR.SCR re/ains in te $N state

e1en i te 2ate is re/o1ed. I anode current alls belo4 te oldin2 current SCR 2et

turned $"".

4


7/54


R/ R-C AND

01T

TRI22ERIN

2 CIRC0ITS

Aim:-To studteo5eration oresistance,resistanceca5acitance andUJTtri22erin2circuitsoSCR .

Appara

tus

require

d: -

SCR

T#),!o4er

Su55lies

,

A//eter,

%olt/et

er, etc.,

Circuit

Diagram: R -

Tri22eri

n2CircuitF

Theory:

Resista#ce Triggeri#g:

Resistance

tri22er circuits arete si/5lest 3 /ost

econo/ical /etod.

Durin2 te 5ositi1e

al ccle o te

in5ut 1olta2e, SCR

beco/e or4ard

biased but it 4ill not

conduct until its

2ate current eGceeds

I2/in . Diode D

allo4s te lo4 o

current durin2

5ositi1e al ccle

onl. R? is te

1ariable resistance

3 R is te

stabili=in2

resistance .R* is

used to li/it te

2ate current. Durin2

te 5ositi1e al

ccle current I2


8/54

lo

4s.

I2

incr

eas

es

and

4e

n

I2

I2/in te SCR turns

$N .Te irin2

an2le can be 1aried

ro/ > b

1arin2 te

resistance R.

5


9/54


3ode$ 2raph: R - Tri22erin2 CircuitF

rocedure :- R "irin2 F

1. Connections are /ade as so4n in i2.

2. S4itc on te 5o4er su55l to te CR$.

3. Set te CR$ to te line tri22er /ode.

4. S4itc on 5o4er su55l to te SCR trainer.

5. $bser1e te 4a1eor/ on te CR$.

6. Stud te 4a1eor/s or 1arious irin2 an2le b 1arin2 te 5ot in R tri22er circuit.

7. $bser1e te ran2e o irin2 an2le control.

8. "or an one 5articular irin2 an2le 5lot te 4a1eor/s o te ac 1olta2e, 1olta2e across teload and te SCR.

9. Measure te a1era2e dc 1olta2e across te load and r/s 1alue o te ac in5ut 1olta2e usin2 adi2ital /ulti/eter.

10. Calculate te dc out5ut 1olta2e usin2 te eKuation.

% - %r/s 1alue o ac in5ut 1olta2e

%/ -


10/54

6


11/54


O!ser"atio# Ta!$e:-

Teoretical %oSr No "irin2 An2le cos Indicated %o

Circuit Diagram:- RC Tri22erin2 CircuitF

Theory :- RC Tri22erin2F

& 1arin2 te 1ariable resistance R, te irin2 an2le can be 1aried ro/ *B

.In te ne2ati1e al ccle te ca5acitance C car2es trou2 te diode D? 4it lo4er 5late

5ositi1e to, te 5ea0 su55l 1olta2e E/aG .Tis Ca5acitor 1olta2e re/ains constant at until

su55l 1olta2e attains =ero 1alue. Durin2 te 5ositi1e al ccle o te in5ut 1olta2e, C

be2ins to car2e trou2 R. 6en te ca5acitor 1olta2e reaces te /ini/u/ 2ate tri22er

1olta2e SCR 4ill turn on.


12/54

7


13/54


Modelra5F

rocedu

re:-

RC

"IRINF

*.

Connections are

/ade as

so4nin i2.

?.S4itc

on te5o4er

su55lto te

CR$ .

3. Sette

CR$

to teline

tri22er /ode.

4. S4itc on 5o4er

su55l to te SCRtrainer.

5. $bser1e te 4a1eor/

on te CR$.

6. Stud te 4a1eor/sor 1arious irin2

an2le b 1arin2 te

5ot in R tri22ercircuit.

7. $bser1e te ran2e oirin2 an2le control. t

u t e o T e c n o l o

2 !a2e '@

8. "or an one 5articularirin2 an2le 5lot te4a1eor/s o te ac1olta2e, 1olta2e acrosste load and te SCR.

9. Measure te a1era2edc 1olta2e across teload and r/s 1alue ote ac in5ut 1olta2eusin2 a di2ital/illi/eter.

10. Calculate te dcout5ut 1olta2e usin2

te eKuation.

8


14/54


O!ser"

atio#

Ta!$e:

In5ut

UJT

Tri22erin2

Circuit F

-

Theory:

-

A

s

n

croni=ed UJTtri22ered circuit

usin2 an UJT is

so4n in tei2ure. Diodes

D*O to D)O recti

ac to dc. Resistor R*

lo4ers %dc to a

suitable 1alue or te

=ener diode and UJT.

+ener diode +O

unctions to cli5 te

rectiied 1olta2e to a

standard le1el, %=O

4ic re/ains

constant eGce5t near

te %dc =ero. Te

1olta2e %= is a55lied

to te car2in2

circuit

RC. Current IO,

car2es ca5acitor cO

at a rate deter/ined

b RO 1olta2e across

ca5acitor is /ar0ed

b %cO as so4n.

6en %cO reaces

te

te t-&* :unction o

UJT brea0s do4n and

te ca5acitor cO

discar2es trou2

te 5ri/ar o

9


15/54


5ulse

transor

/ersendin2

a currentC?O asso4n.

As

te

curr

ent

i?O

is

in

te

or

/

o

5ul

se,4in

din

2s

o

te

5ul

se

tran

sor

/er

a1

e

5ul

se

1olta2es at teir

secondar

ter/inals. !ulse at

te t4o secondar

4indin2s eeds te

sa/e in 5ase 5ulse

to t4o SCRs o a

ull 4a1e circuits.

SCR 4it 5ositi1e

anode 1olta2e

4ould turn $N. As

soon as te

ca5acitor

discar2es, it starts

to recar2e as

so4n. Rate o rise

o ca5acitor 1olta2e

can be controlled b

1arin2 RO. Te

irin2 an2le can be

controlled u5 to

abo1e *'o. Tis

/etod o

controllin2 te

out5ut 5o4er b

1arin2 te

car2in2 resistor rO

is called ra/5

control, o5en loo5

control 7or8 /anual

control.

3ode$ 2raph:-


16/54

10


17/54


rocedure:-

1. Connect a 3 0 ter/inal o UJT tri22erin2 circuit to te 2ate catode ter/inals o SCR.

2. i1e a ?) % ac su55l.

3. $bser1e te 4a1eor/s and 5lot it or one 5articular irin2 an2le b ad:ustin2 te5otentio/eter and obser1e te ran2e o1er 4ic irin2 an2le is controllable.

4. $bser1e tat ca5acitor 1olta2e is set at e1er al ccle.

O!ser"atio# Ta!$e:-

Teoretical %o

Sr No "irin2 An2le cos Indicated %o

Resu$t: - Tus te o5eration o resistance, resistance ca5acitance and UJT tri22erin2 circuits oSCR as been studied.


18/54

11


19/54


SIN2'

E

HASE

%0''4

CONTR

O''ED

CON*E

RTER

Aim:-Tostudteo5erati

on osin2le5aseullcontrolledcon1erter usin2R andRL loadandtoobser1eteout5ut

4a1eor/s.

Appara

tus

Require

d:

!o4er

Tristo

rs,

Reostat, CR$,

Transor

/er 7*-5ase8

?@%


20/54

is

eit

er

5os

iti1

e or

ne2

ati1

e

but

out

5ut

curr

ent

is

al4

as

5os

iti1

e. "i2ure so4s te

Kuadrant o5eration

o ull controlled

brid2e rectiier 4it

R-load. "i2 so4s

sin2le 5ase ull

controlled rectiier

4it resisti1e load.

Tis t5e o ull

4a1e rectiier

circuit consists o

our SCRs. Durin2

te 5ositi1e al

ccle, SCRs T* and

T? are or4ard

biased. At Pt ,

SCRs T*

12


21/54


and

T@

are

tri2

2er

ed,

te

n

te

curr

ent

lo

4s

tro

u2

te

L -

T*-

R

loa

d -

T@ -

N.

At

Pt

Q,

su55l

1olt

a2e

all

s to

=er

o

and te current also

2oes to =ero. Hence

SCRs T* and T@

turned o. Durin2

ne2ati1e al ccle

7Q to ?Q8. SCRs T@

and T) or4ard

biased. At Pt Q

, SCRs

T? and T) are

tri22ered, ten

current lo4s

trou2 te 5at N -

T? - R load- T) - L.

At Pt ?Q, su55l

1olta2e and current

2oes to =ero, SCRs

T? and T) are

turned o. Te "i2-

@, so4s te current

and 1olta2e

4a1eor/s or tis

circuit. "or lar2e

5o4er dc loads, @-

5ase ac to dc

con1erters are

co//onl used.

Te 1arious t5es o

tree-5ase 5ase-

controlled

con1erters are @

5ase al-4a1e

con1erter, @-5ase

se/i con1erter, @-

5ase ull controlled


22/54

and

@-

5a

se

dua

l

con

1ert

er.

Tr

ee-

5a

se

al

-

4a1

e

con

1ert

er is

rare

l

use

d in

ind

ustr

bec

aus

e it

intr

odu

ces

dc

co

/5onent in te

su55l current.

Se/i con1erters and

ull con1erters are

Kuite co//on in

industrial

a55lications. A dual

is used onl 4en

re1ersible dc dri1es

4it 5o4er ratin2s

o se1eral M6 are

reKuired. Te

ad1anta2es o tree

5ase con1erters

o1er sin2le-5ase

con1erters are as

underF In @-5ase

con1erters, te

ri55le reKuenc o

te con1erter out5ut

1olta2e is i2er

tan in sin2le-5ase

con1erter.

ConseKuentl, te

ilterin2

reKuire/ents or

s/ootin2 out te

load current are less.

Te load current is

/ostl continuous

in @-5ase

con1erters. Te load

5eror/ance, 4en

@-5ase con1erters

are used, is


23/54

ter

eor

e

su5

erio

r as

co

/5

are

d to

4e

n

sin2

le-

5a

se

con

1ert

ers

are

use

d.

Edc7?E/87Cos8


24/54


readin2 o te /ulti/eter. Also note te 1alue o /aGi/u/ a/5litude %/ ro/ te 4a1eor/.

8. Set te 5otentio/eter at dierent 5ositions and ollo4 te ste5 2i1en in 78 or e1er 5osition.

9. Tabulate te readin2s in obser1ation colu/n.

10. Dra4 te 4a1eor/s obser1ed on CR$.

O!ser"atio# Ta!$e: -

Teoretical %o

Sr No "irin2 An2le cos Indicated %o

Resu$t:

Tus te o5eration o sin2le 5ase ull controlled con1erter usin2 R load as been studied

and te out5ut 4a1eor/s as been obser1ed.


25/54

14


26/54


3ONOSTA5'E

30'TI*I5RATO

R

Aim:-To stud

anddesi2n

/onosta

ble

/ulti1ibrator.

Appara

tus:-

CR$,connecti

n2

4ires,unction

2enerato

r,5robesetc.

Circuit

diagra

m:-

THEO

R4:-

A monostable

multivibrator (MMV)

often called a one-shot

multivibrator, is a 5ulse

2enerator circuit in4ic te duration o te

5ulse is deter/ined b

te R-C net4or0,

connected eGternall to

te ''' ti/er. In suc a

1ibrator, one state o

out5ut is stable 4ile te

oter is Kuasi-stable

7unstable8. "or auto-

tri22erin2 o out5ut ro/Kuasi-stable state to

stable state ener2 is

stored b an eGternall

connected ca5acitor C to

a reerence le1el. Te

ti/e ta0en in stora2e

deter/ines te 5ulse

4idt. Te transition o

out5ut ro/ stable state

to Kuasi-stable state isacco/5lised b

eGternal tri22erin2. Te

sce/atic o a ''' ti/er

in /onostable /ode o

o5eration is so4n in

i2ure.

15
http://www.circuitstoday.com/555-timer-ic-introductionhttp://www.circuitstoday.com/555-timer-ic-introductionhttp://www.circuitstoday.com/555-timer-ic-block-diagramhttp://www.circuitstoday.com/555-timer-ic-introductionhttp://www.circuitstoday.com/555-timer-ic-block-diagramhttp://www.circuitstoday.com/555-timer-ic-block-diagram


27/54


In te/onostable/ode,te '''ti/eracts as aone-sot5ulse2enerator. Te5ulsebe2ins

4ente '''ti/errecei1esa si2nalat tetri22erin5uttat allsbelo4 atird o

te 1olta2e su55l. Te4idt o te out5ut 5ulseis deter/ined b teti/e constant o an RCnet4or0, 4ic consistso a ca5acitor 7C8 and aresistor 7R8. Te out5ut5ulse ends 4en tecar2e on te C eKuals?


28/54

16


29/54


4. Teoreticall calculate te 5ulse duration as Ti2*.*. RAC

5. Co/5are it 4it eG5eri/ental 1alues

O!ser"atio# Ta!$e :-

Ton To "reKuenc Du

THE$R$TICAL

!RACTICAL

Resu$t:- Tus te /onostable /ulti1ibrator as been desi2ned and studied successull.

17


30/54


ST0D4

O%

ASTA5

'E

30'TI

*I5RA

TOR

0SIN2

IC 666

Aim:-

Stud o

Astable/ulti1ibrator

usin2 IC

''' orreKuenc

* 0=

and dutccle

('.

Appara

tus

require

d :- IC

()*,&read-

board,du

al 5o4er

su55l,unctio

n

2enerato

rresistors

and

connect

in2

4ire.

Circuit

diagra

m:-

Theory:-

Te circuit

dia2ra/ or te astable

/ulti1ibrator usin2 IC

''' is so4n ere. Teastable /ulti1ibrator

2enerates a sKuare 4a1e,

te 5eriod o 4ic is

deter/ined b te circuit

eGternal to IC '''. Te

astable /ulti1ibrator

does not reKuire an

eGternal tri22er to

can2e te state o te

out5ut. Hence te na/e

ree runnin2 oscillator.Te ti/e durin2 4ic

te out5ut is eiter i2

or lo4 is deter/ined b

te t4o resistors and a

ca5acitor 4ic are

eGternall connected to

te ''' ti/er Te abo1e

i2ure so4s te '''

ti/er connected as an


31/54

astable

/ulti1ib

rator.

Initiall

4en

te

out5ut

is i2 ca5acitor C starts

car2in2 to4ards Vcc

trou2RAandRB.

18


32/54


5$oc, diagram o7 IC 666

Ho4e1er as

soon aste

1olta2e

acrossteca5acitor eKuals

?


33/54


rocedure:-

1. Ma0e te connectins as so4n in te i2 4it te desi2ned 1alues.

2. %ar te 5reset and obser1e te out5ut on CR$.

3. $bser1e te out5ut across ca5acitor

4. %eri te 5ractical 1alues o Ton and To 4it teoretical 1alues.

O!ser"atio#s:-

Ton To Dut Ccle

THE$RI$TICAL

!RACTILAC

2raph:-

1) $


34/54


INTE2RATOR

0SIN2 IC89

O-A3

Aim:-

Tostud teo5erationoteInte2ratorusin

2 o5-a/5andtraceteout5ut4a1eor/s orsineandsKuare4a1ein5uts.

Appara

tus

Require

d:-

&read

&oardIC()*,

Resistors,

Ca5acit

ors"unctio

n

enerat

or CR$!robes

Connectin2 4ires

Circuit Diagram :- 7To

be Dra4n8

Theory:-

I#tegrator:

A circuit in4ic te out5ut1olta2e is teinte2ration o tein5ut 1olta2e iscalled an inte2rator.

In te 5ractical

inte2rator to reduce te

error 1olta2e at te

out5ut, a resistor R" is

connected across te

eedbac0 ca5acitor C".

Tus, R" li/its te lo4-

reKuenc 2ain and

ence /ini/i=es te

1ariations in te out5ut1olta2e.

Te reKuencres5onse o teinte2rator is so4n in


35/54

te i2.b is tereKuenc at4icte 2ainis d&and is2i1en b

b *


36/54


teabo1eeKuation, 4e cancalculat

e R bassu/in2 a 3C.Tisis 1eri/5ortantreKuenc. Ittells us4ereteuseulinte2rationran2estarts.Inte2rator as

4ide

a55lications in

1. Anal

o2co/5utersu

sedorsol1i

n2 dierentialeKuations insi/ulationarran2e/ents.

2. A


37/54

Resu$t: Tus,

Inte2rator circuit

as been studiedand te

4a1eor/s as

been obser1ed.

22


38/54


ST0D4 O% 'O2IC

2ATES

Aim FTo

studabout

lo2ic

2atesand

1eri

teir

truttables.

Apparatus

require

dFICs

,Connectin2

6ires

and&read

&oard.

Circuit

Diagra

m F-

AND

OR

23


39/54


NAND

NOT

24


40/54


NOR

25


41/54


E;-OR

Theory :-

Circuit tat ta0es te lo2ical decision and te 5rocess are called lo2ic 2ates.

Eac 2ate as one or /ore in5ut and onl one out5ut. $R, AND and N$T are

basic 2ates. NAND, N$R and X-$R are 0no4n as uni1ersal 2ates. &asic 2ates

or/ tese 2ates.

AND 2ATE:

Te AND 2ate 5eror/s a lo2ical /ulti5lication co//onl 0no4n as

AND unction. Te out5ut is i2 4en bot te in5uts are i2. Te out5ut is

lo4 le1el 4en an one o te in5uts is lo4.

OR 2ATE:

Te $R 2ate 5eror/s a lo2ical addition co//onl 0no4n as $R unction.

Te out5ut is i2 4en an one o te in5uts is i2. Te out5ut is lo4 le1el

4en bot te in5uts are lo4.


42/54

26


43/54


NOT

2ATE:

Te

N$T2at

e is

called

an

in1erte

r.

Te

out5ut

is

i2

4

ente

in5

utis

lo4.Te

out5ut

is lo44en

te

in5ut isi2.

NAND

2ATE:

Te

NAND2ate is a

contracti

on o

AND-N$T.

Te

out5ut is i2 4en bot

in5uts are lo4 and an

one o te in5ut is lo4

.Te out5ut is lo4 le1el

4en bot

in5uts are i2.

NOR 2ATE:

Te N$R 2ate is a

contraction o $R-N$T.

Te out5ut is i2 4enbot in5uts

are lo4. Te out5ut is

lo4 4en one or bot

in5uts are i2.

;-OR 2ATE:

Te out5ut is i2 4enan one o te in5uts is

i2. Te out5ut is lo4

4en bot te in5uts

are lo4 and bot te

in5uts are i2.

rocedure: -

1. Connections are

2i1en as 5er

circuit dia2ra/.

2. Lo2ical in5utsare 2i1en as 5er

circuit dia2ra/.

3. $bser1e teout5ut and 1eri

te trut table

.

Resu$t :- All te

basics 2ates are

studied and te trut


44/54

tables

are1eriie

d.

27


45/54


RE

A'

I

Documents

237436528 Final Ie Lab Manual