220ExamSolution

UNIVERSITY OF MICHIGAN

EECS 270: Intro to Logic Design Midterm Exam 1

Profs. Kang Shin and Trevor Mudge

Wednesday February 11, 2015

7:30-9:30 p.m.

A - O: 1013 DOW P - St: 1014 DOW Su - Z: 1017 DOW

Name: ______Solutions______________________________________________

UMID: _______________________________________________________________

Honor Pledge: I have neither given nor received aid on this exam, nor have I concealed any violation of the Honor Code.

Signature: _______________________________________________________________

Instructions: The exam is closed book except for one double-sided

8.5"x11" sheet of notes. No electronics of any kind may be used.

1. / 9

2. /15

Print your name and student ID number and sign the honor pledge.

3. / 20

4. / 16

The exam consists of 7 problems with the point distribution as indicated here. Please keep this in mind as you work through the exam. Use your time wisely.

5. / 20

6. / 10

Provide all answers on the pages provided. No additional pages will be considered.

7. / 10

Total: / 100

EECS 270 University of Michigan Winter 2015

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1. [Number Systems9 Points] A. [3 Points] What is the range of representation of non-negative decimal ranges in the following format for the following schemes? You may leave your answer in terms of powers of the specified radix. 5 digits in hexadecimal = ___[0, 165 -1]_______________

7 digits in octal = ____[0, 87 -1]_________________

12 digits in binary = _____[0, 212 - 1]_____________

B. [6 Points] Convert the following decimal numbers to binary, then to octal and hex. Only 6 fractional bits are necessary. If there is a repeating fractional part, indicate it. You may show your work below the table.

Decimal Binary Octal Hexadecimal

20.413 10100.0110102 24.328 14.6816

36.375 100100.0110002 44.308 24.6016

112.2 1110000.0011002 160.148 70.3016


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2. [Boolean Algebra15 Points] A. [5 Points] Convert (xy) to SOP form. Describe its function with one word. () = ( + )

= ()() = ( + )( + ) = + + + = +

Equality B. [5 Points] Given the truth table:

x y F

0 0 1

0 1 1

1 0 0

1 1 1

By answering the three parts below, show that F is functionally complete. You can use constants 0 & 1.

(i) Show how NOT can be implemented using one or more gates that implement F:

(ii) Show how AND can be implemented using one or more gates that implement F:

(iii) Show how OR can be implemented using one or more gates that implement F:


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C. [5 Points] Apply the rules of Boolean Algebra to show that both sides of the following equation are equivalent without using truth tables (perfect induction). Hint: expand xy and yz.

+ + = + + = + ( + ) + = + + +

= + + =


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3. [Shannons Expansion Theorem20 Points]

A. [6 Points] Prove the following:

(, , , ) = [ + (, , , , )] [ + (, , , , )]

If x2 = 0, = (1, 0, 3, , ) = [0 + (1, 0, 3, , )][1 + (1, 1, 3, , )]

= (1, 0, 3, , ) 1 =

If x2 = 1,

= (1, 1, 3, , ) = [1 + (1, 0, 3, , )][0 + (1, 1, 3, , )]

= 1 (1, 1, 3, , ) =

Q.E.D.

B. [4 Points] Expand the following around ac.

= + + + +

= ( + + ) + () + ( + + ) + () = ( + ) + () + ( + ) + ()


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C. [10 Points] For the function F given below:

(, , , ) = + +

(i) Identify all the minterms of F.

= ( + ) + ( + ) + ( + ) = + + + + +

(ii) Is the sum of minterms of F unique?

Yes, when commutativity is considered.

(iii) Prof. Shin said in class that the sum of products is not always unique. The above F(a,b,c,d) is minimal. Is this minimal expression unique? Justify your answer, i.e. show why if yes and show another minimal expression if no.

No, we can manipulate the minterms to get another minimal expression as:

= + + + + + = + + + + + = ( + ) + ( + ) + ( + ) = ( + ) + ( + ) + ( + ) = + +


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4. [Combinational Logic Blocks16 Points] [8 Points] Use an 8-to-1 multiplexer to implement the three-variable EXCLUSIVE-OR function . Inputs I7 and S2 are the most significant bits; inputs I0 and S0 are the least significant bits. Your answers should be in terms of a, b, c, 0, or 1.

Answers:

I0 = 0

I1 = 1

I2 = 1

I3 = 0

I4 = 1

I5 = 0

I6 = 0

I7 = 1


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[8 Points] Using an 8-to-1 multiplexer, implement the four-variable EXCLUSIVE-OR function . Inputs I7 and S2 are the most significant bits; inputs I0 and S0 are the least significant bits. Your answers should be in terms of a, b, c, d, 0, or 1.

Answers:

I0 = d

I1 = d

I2 = d

I3 = d

I4 = d

I5 = d

I6 = d

I7 = d


Page 9 of 12

5. [Combinational Design20 Points] A SuperSafe 2-passenger car will only start if the cars safety system signals that all passengers are seated with their seatbelts fastened. It also will not start unless there is at least one passenger seated in the car. (Note: it is possible that a seatbelt can be fastened when no passenger is in the corresponding seat in such a case, the safety system should still allow the engine to start.) In addition to starting the car, the safety system must illuminate a warning light if the car is moving fast and a seatbelt becomes unfastened. Inputs: Passengers seated (P1, P2: 0=passenger not seated, 1=passenger seated) Seatbelts fastened (S1, S2: 0=seatbelt not fastened, 1=seatbelt fastened) Car moving fast (F: 0=not fast, 1=fast) Outputs: Start engine (E: 0=do not start, 1=start) Warning light (L: 0=light is on, 1=light is off)

A. [9 Points] Write a canonical SOP equation for the start engine output E. (Do not use shorthand notation.)

= 121

2 + 1212 + 12

12 + 12

12 + 1212


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B. [8 Points] Write a canonical POS equation for the warning light output L. (Pay attention to the output signal! Do not use shorthand notation.)

F S1 S2 L L (active low)

0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1

= ( + 1 + 2)( + 1 + 2

)( + 1 + 2)

C. [3 Points] SuperSafe will only let you design the circuit using two-input NAND gates. What is the minimum number of these gates necessary to implement the start engine output? (Hint: Simplify (show your work) your solution from Part A. Try to determine the minimum number of NAND gates without drawing the whole circuit.)

= 121

2 + 1212 + 12

12 + 12

12 + 1212 = 1

2(12 + 12) + 12

(12 + 12) + 1212

= 122 + 12

1 + 1212

NOT requires 1 NAND gate, AND requires 2 NAND gates, OR requires 3 NAND gates. All NAND gates have two inputs in accordance with the question.

1221 NOT, 2 ANDs 1(1 NAND gates) + 2(2 NANDs) = 5 gates

121 1 NOT, 2 ANDs 1(1 NANDs) + 2(2 NANDS) = 5 gates

1212 3 ANDs 3(2 NANDs) = 6 gates

122 + 12

1 + 1212 The previous gates + two OR gates

16 + 2(3 NANDs) = 22 gates.


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6. [Timing and Delay10 Points]

Assume that the NOR and AND gates have a 50ns delay, and that the NOT and XOR gates have a 100ns delay. Complete the timing diagram below clearly showing all causality arrows. Assume that signals are stable at -100ns.


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7. [Laboratory Experience10 Points] Part 1: True or False [6 Points]

Circle the correct answer (True or False) for each question [1 point each].

If KEY3 is connected directly to one of the red LEDs and one of the 7 segment LEDs, one of the LEDs will be illuminated and one will not regardless of the switch setting.

True

If in lab 1, SW[17:10] are set with the value 0xC0 and SW[7:0] are set with the value 0x03, HEX[5:2] will NOT remain illuminated regardless of the select switch (KEY3) value.

True

A timing simulation unlike a functional simulation must have the FPGA pins specified in the QSF file.

False

One worst case propagation delay for the 4 bit ripple carry adder has the A input set to 0x5, the B input set to 0xA and the CIN going from 0 to 1.

True

It was necessary to covert the full adder module to a Verilog file before it could be created as a custom schematic symbol.

True

When using the timing simulation model, you are given the choice between a SLOW model or FAST model. The FAST model is best for finding worst case propagation delays.

False

Part 2: Test Bench Completion [4 Points]

Complete the following test bench that will test a simple XOR function with inputs X and Y and output Z. The schematic file name of the XOR function is myxor. You may choose any acceptable test bench module name. Each simulation case should take 20ns. Each box is worth one point. You must fill in all the blanks in the box to get the point.

`timescale 1 ns/1 ns

module _anything_but_myxor();

reg red, blue;

wire yellow;

myxor_____ t1 (.__X___ (_red__), ._Y____ (_blue__), ._Z____ ( _yellow_));

initial begin

_red_____

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