2190 IEEE JOURNAL OF SOLID-STATE CIRCUITS, …microel_group.unisalento.it/page8/page22/files/01362828.pdf2192 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004 Fig

2190 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004

A Polar Modulator Transmitter for GSM/EDGEMichael R. Elliott, Tony Montalvo, Brad P. Jeffries, Frank Murden, Jon Strange, Member, IEEE, Allen Hill,

Sanjay Nandipaku, Member, IEEE, and Johannes Harrebek

Abstract—This 0.5- m SiGe BiCMOS polar modulator IC addsEDGE transmit capability to a GSM transceiver IC without anyRF filters. Envelope information is extracted from the transmit IFand applied to the phase-modulated carrier in an RF variable gainamplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC pro-duces more than 1 dBm of output power with more than 6 dB ofmargin to the transmit spectrum mask and less than 3% rms phaseerror. In GSM mode, more than 7 dBm of output power is producedwith noise in the receive band less than 164 dBc/Hz.

I. INTRODUCTION

THE EDGE standard [1] is an enhancement to GSMdesigned to accommodate higher data rate communica-

tions. In order to achieve this, the modulation ( -shifted[eight–phase–shift keying (8-PSK)]) uses both amplitudemodulation (AM) and phase modulation (PM) versus GSM(GMSK) which requires only PM. Most GSM transmitters usean on-channel voltage-controlled oscillator (VCO) that is phasemodulated with a translational loop phase-locked loop (PLL)[2], [3]. This architecture is very efficient for constant AM,since all RF filtering can be eliminated, but it is incompatiblewith nonconstant-AM such as EDGE.

The AM of EDGE requires a linear transmitter architecture.One conventional approach for linear transmitters is direct up-conversion with an I/Q modulator. Unfortunately, since linearamplifiers tend to be noisier than saturated amplifiers, the up-converter output is likely to have a wideband noise floor thatwould fail the noise requirements of the standard. As a result,RF filtering would be required at the transmitter output to meetthe receive-band noise requirements. Further, a linear modulatoris likely to consume more power than a nonlinear modulator.

II. SYSTEM ARCHITECTURE AND REQUIREMENTS

A polar modulator architecture [4]–[8] was chosen to avoidthe external RF filters that would likely be necessary with othertransmitter topologies and for compatibility with existing GSMtransmitters for an efficient dual-mode solution. A simplifiedblock diagram of the GSM/EDGE transmitter is shown in Fig. 1.An I/Q modulator generates an EDGE (or GSM) modulated IFoutput from the baseband inputs. The IF output contains bothAM and PM in EDGE mode, which can be generically repre-sented as

IF (1)

Manuscript received April 15, 2004; revised July 8, 2004.The authors are with Analog Devices, Inc., Greensboro, NC 27409 USA

(e-mail: [email protected]).Digital Object Identifier 10.1109/JSSC.2004.836340

where is the AM and is the PM. This is the input signalto both the PM and AM signal paths.

The PM path limits the IF signal IF to remove the AM.The limited signal is then used as the reference input to a trans-lational loop PLL. The PLL locks the VCO to the transmit fre-quency, transfers the PM of the reference input onto the VCO,and acts as a tunable high-Q filter for input noise contributors inthe transmitter. The resulting VCO output from the PLL is then

VCO (2)

The IF signal IF is also input to the AM path where the AMis extracted by mixing the IF signal with an amplitude-limitedversion of itself, yielding

IF (3)

which can also be represented as

IF

(4)

The undesired component is removed by the amplitudepath filter leaving only the desired AM signal . The PMand AM signals are then recombined in the RF variable-gainamplifier (VGA) at the output of the transmitter.

In GSM mode, the AM path is disabled and the transmitterreverts to a conventional nonlinear offset PLL transmitter.This implementation includes two RF paths, each coveringtwo bands to form a quad-band solution. The low band coversthe GSM-850 (824–849 MHz) and GSM-900 (880–915 MHz)bands. The high band covers the DCS (1710–1785 MHz)and PCS (1850–1910 MHz). A detailed block diagram of thecomplete transmitter is shown in Fig. 2 with both signal pathsand the required calibration circuits. Although the solution isa complete GSM/EDGE transceiver, the focus of this paper isthe polar modulator IC.

One of the key challenges in the polar modulator architectureis the tradeoff between the RF spectrum and noise. A summaryof the requirements [1] is shown in Table I. A system-level anal-ysis of a polar modulator reveals that inadequate bandwidths inthe PM and AM paths result in spectral regrowth that can vio-late the transmit mask requirement as imposed by the standard.This spectrum degradation can be understood by comparing theamplitude and phase components of the signal to the compositesignal and the transmit mask, as seen in Fig. 3. Note that thephase component of the signal exceeds the mask requirementby over 25 dB at 400-kHz offset from the carrier.

0018-9200/04$20.00 © 2004 IEEE

ELLIOTT et al.: A POLAR MODULATOR TRANSMITTER FOR GSM/EDGE 2191

Fig. 1. Simplified transmitter block diagram.

Fig. 2. Detailed block diagram.

Fig. 4 shows the relationship between AM and PM band-widths and margin to the transmit mask at the critical offsetof 400 kHz from the carrier. At 400-kHz offset, the spectrumis the most sensitive to transmitter impairments that result inspectral regrowth. Clearly, wider modulation bandwidths resultin more margin to the mask requirement. However, as the signalpath bandwidths are increased, the out-of-band noise also in-creases. The most stringent noise requirement in EDGE modeis the noise in the receive band at 20-MHz offset from the car-rier. The transmit mask requirements are the same for both the

TABLE ISYSTEM REQUIREMENTS


Fig. 3. Signal bandwidths.

low and high bands, but the noise requirement is more difficultin the low band, so the focus will be on the low band.

Fig. 5 shows the relationship between the PM bandwidth andmargin to the transmit mask on one axis and receive-band noisemargin on the other axis for EDGE mode. The transmitter isdesigned to have 6-dB margin to the transmit mask requirementto minimize the back-off required in the power amplifier—thusmaximizing its efficiency. The receive-band noise target in-cludes 3 dB of margin to ensure manufacturability. Thus, thephase modulator bandwidth must be between 3.5–4.0 MHzor about 6%. The phase modulator is a PLL which hassignificant bandwidth variation due to the variation ofthe integrated VCO. The VCO gain variation can result innearly 30% bandwidth variation. A calibration is utilized tominimize bandwidth variation, as described in Section III-A.

The polar transmitter has other impairments that can degradespectral mask performance beyond just the bandwidth require-ments. These impairments include delay mismatch between theAM and PM paths, dc offsets in the amplitude path, and finiteRF isolation between the PM signal and the transmit output. TheAM and PM signals must be correctly time aligned before re-combination at the RF VGA. The delay mismatch system simu-lations demonstrate the requirements, as shown in Fig. 6. Noticethat the EVM performance is relatively insensitive, but the spec-tral mask margin degrades significantly with delay mismatch.As a result, the group delay of the AM path must match thegroup delay of the PLL PM path to meet the transmit mask re-quirements.

The amplitude path is also sensitive to dc offsets which pro-vide a leakage path for the PM signal to the transmit output. Thiscan be observed mathematically as follows:

TX DC (5)

which can also be expressed as

TX DC (6)

The transmit output in the presence of AM-path dc offsetscontains both the desired signal and an undesired PM compo-nent with an amplitude equal to the dc offset. The PM signalexceeds the 400-kHz offset spectral mask requirement by morethan 25 dB, as shown in Fig. 3. This translates to a dc offsetlimit in the amplitude path of 0.2% relative to the peak of theenvelope, as verified with system simulations. In addition to dcoffsets, finite isolation from input to output in the RF VGA canprovide a path for the PM signal to leak to the transmit outputand degrade the spectral mask. This is discussed in greater de-tail in Section III-C.

III. IMPLEMENTATION DETAILS

A. PM Calibration

The conflict between the narrow bandwidth required for noisefiltering and the wide bandwidth required to meet the RF spec-trum mask dictates very tight control of the phase and enve-lope bandwidths as described in Section II. The bandwidth ofthe transmit PLL (i.e., the phase modulator) is proportional to

where is the charge-pump current and isthe VCO gain. The VCO gain could have 50% variation and,as a result, the bandwidth can also vary significantly. In orderto maintain the bandwidth with the required 6% accuracy, wemust calibrate the charge pump current such that the ,product is roughly constant.

The standard allows 200 s for the frequency synthesizer tolock prior to a transmit burst. Since the transmit PLL lock timeis much less than 200 s, we can use that time to calibrate thebandwidth. A block diagram of the calibration scheme is shownin Fig. 7. The first step to calibrating the bandwidth is measuring

. Before we measure , we must set the VCO fre-quency to close to the desired carrier frequency sincedepends on frequency.

The calibration begins with the calibration of the VCO’s2 bits of tank tuning. The control voltage is disconnected fromthe PLL and set to a reference voltage, and the frequency isdetermined by counting VCO periods for “ ” times the periodof the 13-MHz GSM reference clock. “ ” is set such that theresolution is on the order of 1 MHz which is a good tradeoffbetween calibration time and the desired accuracy. The counteroutput is

COUNT (7)

where is the GSM reference time base and is theVCO period. The VCO frequency is then

COUNT(8)

A successive approximation (SAR) algorithm is used to min-imize the error between the VCO frequency and the desired car-rier frequency, which is represented by “TX channel” in Fig. 7.

After the coarse frequency adjustment is completed, anotherSAR algorithm is used to set the VCO frequency close to thedesired transmit carrier frequency by driving the control voltagewith a digital-to-analog converter (DAC). This is required to ac-count for the variation with control voltage within each


Fig. 4. Modulation bandwidth requirements.

Fig. 5. Receive-band noise and transmit mask versus PM bandwidth (EDGEmode).

Fig. 6. Transmit mask and EVM versus delay mismatch (EDGE).

capacitor setting of the VCO. Once the VCO is operating atthe transmit frequency, the is measured by forcing the

Fig. 7. Phase-bandwidth calibration block diagram.

control voltage to two different settings and measuring the fre-quency deviation . A digital algorithm usesthe measured data to set the charge-pump current in-versely proportional to .

In GSM mode the output SNR requirement is 6 dB more strin-gent than in EDGE mode. However, the PM bandwidth is muchnarrower than in EDGE mode. Thus, in GSM mode, the trans-lational-loop PLL bandwidth is automatically reduced to meetthe more stringent receive-band noise specifications. The band-width is reduced by decreasing the charge pump current by afactor of two and doubling the loop filter pole capacitance. Theslight increase in closed-loop peaking of the PLL response istolerable due to the relaxed bandwidth requirements in GSMmode and the added stability of the bandwidth calibration thatis not typically present in most PLLs.

B. RF Path: GMSK Modes

A simplified schematic of the GSM-band PM path in GMSKmode is shown in Fig. 8. The description of the PM path is fo-cused on the GSM band which has a much more stringent noiserequirement. The DCS/PCS band implementation is simply fre-quency scaled from the GSM-band implementation. The mostdifficult requirement is the noise in the receive band, as men-tioned in Section II. Ideally, the noise should be dominated by


Fig. 8. GMSK signal path.

the VCO. For this to be true, the RF driver’s noise contributionshould be very small.

The VCO—shown on the left of Fig. 8—uses a PMOS coredespite the availability of SiGe bipolar transistors. The SNR isoptimized by maximizing the voltage swing on the tank which isproportional to and by minimizing the noise current addedby the cross-coupled pair, which is proportional to . Thus,transistors with a low are preferable for a low-noise VCO.

The inductors are made with 4- m-thick aluminum. The in-ductor Q is about 11 at 870 MHz. We use two single-ended in-ductors rather than a center-tapped structure—which could havehigher Q in less area—because electromagnetic simulations pre-dict that this structure reduces magnetic coupling from the VCOto the transmitter’s output. As mentioned in Section II, any cou-pling from the phase-modulated carrier to the output results indegradation of margin to the transmit mask. The varactors aremade from collector-base pn diodes. The VCO’s frequency isdigitally tunable in four roughly 45-MHz steps in order to coverthe wide tuning range requirement with reasonably low .

The primary challenge here is low phase noise at 20-MHzoffset from the carrier. Aside from the obvious requirementsof a high-Q tank and minimal in the core transistors, alow-noise bias current is critical to achieving low phase noise.The bias current is derived from a low-noise (i.e., high current)

reference and low-pass filtered using an off-chip ca-pacitor. Further filtering of high-frequency noise that could bedownconverted to the carrier frequency is applied by the tailinductor/capacitor combination [9]. The tail current is propor-tional to absolute temperature (PTAT). A PTAT tail current keepsthe voltage swing on the tank roughly temperature-independentsince the temperature coefficient of the metal used to make theinductors results in a roughly inverse PTAT tank impedance.

The VCO signal must be amplified in order to drive the50- external load at 5 dBm. The ultimate noise requirementis 165 dBc/Hz at 20-MHz offset from the carrier. Practically,

that noise will be dominated by the VCO which means that anyelements following the VCO must contribute very little noise.Consider a simple calculation of the RF driver’s base-currentnoise contribution. The RF driver amplifier in GMSK mode is asimple differential pair with a roughly 16-mA tail current. TheSNR at the input to the RF driver considering only the driver’sbase current noise with a noiseless tail current is

(9)

where is the rms signal amplitude at the input to thedriver and is the effective parallel impedance of theVCO’s tank. With a 500-mVp input amplitude, ,and , the SNR is about 162 dB/Hz, which wouldclearly not be acceptable. Thus, the VCO’s relatively highoutput impedance must be isolated from the RF driver with abuffer. The buffer also isolates the VCO’s tank from the inputcapacitance of the driver, which enhances the tuning range.

The VCO buffer is a simple emitter follower which is lightlycapacitively coupled to the tank. As seen in (9), special caremust be taken to minimize the noise current being injected intothe tank. In fact, the design of the VCO’s buffer should be anintegral part of the VCO design itself.

The GMSK driver is a simple open-collector fully switcheddifferential amplifier. If the tail current has a low-pass noisecharacteristic, that noise is upconverted to the carrier frequencyand results in a bandpass output noise characteristic. Simula-tions predict that, as long as the input amplitude is several hun-dred millivolts or larger, the output noise will be dominatedby upconverted bias current noise. The ratio of dc current tonoise current of a resistively degenerated current source (ne-glecting noise contributions from base resistance and from thebase-voltage source) is

(10)


Fig. 9. EDGE mode RF driver.

where is the voltage drop across the degenerationresistor. Due to voltage headroom constraints, the maximumpractical is 600 mV. If our target for this contributorto noise is 175 dB/Hz, the minimum bias current is 14 mA.We use 16 mA to ensure adequate SNR under all processconditions. Special care must be taken to lowpass filter thebase voltage source and to ensure that the base voltage sourcehas sufficiently low impedance to make the current source’sbase current noise negligible. We reuse the capacitors fromthe envelope path filter to provide a sufficiently low-frequencyfilter of the GMSK driver’s bias voltage.

C. RF Path: EDGE Modes

A simplified schematic of the RF path used for EDGEmodes—with the EDGE-specific components emphasized—isshown in Fig. 9. The VCO and VCO buffer are the same asthose in Fig. 8. The RF driver consists of Q1–6. Q7–8 is theGMSK-mode driver described in the previous section withthe tail current source omitted since it is a high impedancein EDGE mode. Q9–10 is a dummy driver that is includedto ensure balance. Q7–10 are shown here to emphasize theimportance of balance. The output signal is

(11)where is the carrier frequency, is the PM, and is theamplitude of the input signal. The envelope information is repre-sented as . Note that, although the circuit appears to bebalanced, the envelope is always positive so is always greaterthan . is 16 mA. The maximum instantaneous outputpower is achieved when mA and . On average,

is about 0.707 16 mA since the peak-to-average ratioof the EDGE signal is 3 dB. Coarse power control—in three

6-dB steps—is provided by digitally deselecting fingers of Q5and Q6. Additional power control is provided in the envelopedetector circuits with 1-dB step resolution for a total range of38 dB. The amplitude path also provides an additional 30 dB ofanalog-controlled attenuation for power ramping.

At first glance, it may appear that the EDGE-mode RF path issimilar to a linear modulator since Q5/6 are essentially a lineartransconductor. The difference is that a linear modulator re-quires a complex mixer and a quadrature local oscillator and sois inherently noisier than this implementation of a polar modu-lator. Further, since Q5/Q6 are not, on average, in their balancedstate, they are less noisy than a balanced transconductor con-suming the same current.

Recall that the phase-modulated carrier has much wider band-width than the desired output signal. Leakage from the EDGEdriver’s input to the output can result in a failure of the transmitmask requirement. The input signal amplitude is 500 mV andthe amplitude at the collectors is about 800 mVp (2 dBm in 200

). Recall from Section II that the phase-modulated carrier failsthe transmit mask by 25 dB and our transmit spectrum goal by31 dB. Thus, the isolation required at maximum gain is 35 dB.The isolation requirement is increased as the output power isreduced. We use very careful layout to ensure that the couplingfrom the driver’s input to the output is perfectly balanced.

Imperfect matching of the capacitance at the collectors of Q5and Q6 provides another path for the phase-modulated carrierto leak to the output. The rectification at those nodes creates afrequency component at twice the input frequency, which mixeswith the input frequency to produce an input frequency compo-nent at the output. Minimizing those capacitances and ensuringadequate matching solves the problem.

Imperfect matching of and is yet another mechanismby which the phase-modulated carrier can leak to the output asshown in Section II. System simulations predict that the dc offset


Fig. 10. Envelope-filter simplified schematic.

Fig. 11. Die photograph.

in the envelope path must be less than 0.2% relative to the peakof the envelope signal. This corresponds to a dc offset referred tothe bases of Q5 and Q6 of less than 1 mV. The desired matchingin and is achieved by using large interdigitated devicesand as much degeneration as voltage headroom will allow.

The envelope path circuits—described in the next sec-tion—cannot achieve the desired offset so a calibration isrequired. A low-input-offset ( 0.25 mV) comparator measuresthe dc offset between the bases of Q5 and Q6. The offset isminimized by an 8-b DAC using a successive approximationalgorithm.

D. Envelope Path Filter Implementation

A simplified single-ended representation of the amplitudepath filter is shown in Fig. 10. The filter has two primaryrequirements, wideband noise suppression and delay matching

Fig. 12. Transmitter output spectrum (EDGE mode).

of the amplitude path to the PM path. The PM path is a type-IIPLL which has the following generic transfer function:

(12)

which yields the following group delay

(13)

It can be seen from this equation that the group-delay charac-teristic of the PLL is near zero at low frequency offsets which isthe region of interest. Thus, the amplitude path filter must main-tain the same low group-delay characteristics.

The filter implementation mimics the PLL with twointegrators and a zero for compensation. The first integrator isformed by the cell Q1/R2 and load capacitor C2. The secondintegrator is formed by the cell Q2/R4 and load capacitor


(a)

(b)

Fig. 13. (a) Transmit mask versus frequency (low band; 400-kHz offset). (b) Transmit mask versus frequency (high band; 400-kHz offset).

C1. The zero is implemented at the filter input with R1/C1.In order to minimize the output noise of the filter, the voltageoutput is not buffered prior to the VGA input so as not to intro-duce any unfiltered wideband noise or additional current dissi-pation. As a result, the VGA input impedance must be accountedfor in the design of the filter.

As shown in Fig. 10, the output of the amplitude filter is avoltage input to the RF VGA. The signal of interest, however,is the collector current, , of the RF VGA, as described inSection III-C. That is, the transmit output AM is controlled bythe VGA output current . This current output mustbe a linear representation of the AM signal to prevent spectralmask degradation. System simulations predict an HD3 of 40dBc to prevent significant impacts on the 400-kHz mask. Thefinal Gm cell of the amplitude filter (Q2/R4) is a scaled version

of the RF VGA (Q3/R5). This results in voltage distortionat the output of the filter to predistort the input voltage to theVGA such that a linear relationship is maintained.

IV. MEASUREMENT RESULTS

The polar modulator IC is implemented in 0.5- m SiGeBiCMOS with a die area of 7.8 mm . A die photograph isshown in Fig. 11. A spectrum of the transmitter output inEDGE mode along with the transmit mask is shown in Fig. 12.Clearly, the transmitter has significant margin to the require-ments. The spectral integrity is maintained across all transmitbands in both GSM and EDGE modes, as shown in Fig. 13.

Fig. 14 shows a plot of the receive band noise measurementsfor both GSM and EDGE modes against the requirements of the


(a)

(b)

Fig. 14. (a) Receive band noise (low band). (b) Receive band noise (high band; 1910 MHz).

TABLE IISUMMARY OF TRANSMITTER PERFORMANCE

standard. The stability of the noise and spectral performance isdue to the calibration techniques employed, in particular, the PLLbandwidth control as described in Section III-A. A summary ofthe transmitter measured performance is shown in Table II.

V. CONCLUSION

In this paper, a polar modulator IC for EDGE was described.The polar modulator architecture eliminates the requirementfor external surface acoustic wave filters that would likelybe required with a linear transmitter because the RF path iscomposed of fully saturated—and thus low-noise—circuits.Implementation challenges were analyzed and the primarychallenge—phase-modulator bandwidth control—was ad-dressed by a calibration of the transmit PLL’s loop bandwidth.Measurement results prove that the solution meets the EDGEand GSM requirements with comfortable margin.

REFERENCES

[1] ETSI EN 300 910. GSM 05.05, 1999.[2] J. Strange and S. Atkinson, “A direct conversion transceiver for multi-

band application,” in RFIC Symp. Dig., 2000, pp. 25–28.[3] T. Yamawaki, M. Kokubo, K. Irie, H. Matsui, K. Hori, T. Endou, H.

Hagisawa, T. Furuya, Y. Shimizu, M. Katagishi, and J. R. Hildersley, “A2.7-V GSM RF transceiver IC,” IEEE J. Solid-State Circuits, vol. 32, pp.2089–2096, Dec. 1997.

[4] L. R. Kahn, “Single-sideband transmission by envelope elimination andrestoration,” in Proc. IRE, July 1952, pp. 803–806.

[5] D. Su and W. J. McFarland, “An IC for linearizing RF power ampli-fiers using envelope elimination and restoration,” IEEE J. Solid-StateCircuits, vol. 33, pp. 2252–2258, Dec. 1998.


[6] E. McCune and W. Sander, “EDGE transmitter alternative using non-linear polar modulation,” in Proc. Int. Symp. Circuits and Systems, vol.3, May 25–28, 2003, pp. III-594–III-597.

[7] W. B. Sander, S. V. Schell, and B. L. Sander, “Polar modulator for multi-mode cell phones,” in Proc. Custom Integrated Circuits Conf., Sept.2003, pp. 439–445.

[8] T. Sowlati, D. Rozenblit, E. MacCarthy, M. Darngaard, R. Pullela, D.Koh, and D. Ripley, “Quad-band GSM/GPRS/EDGE polar loop trans-mitter,” in Proc. Int. Solid State Circuits Conf., San Francisco, CA, 2004,paper 10.3.

[9] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lowerLC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, pp.1921–1930, Dec. 2001.

Michael R. Elliott received the B.S. degree from theUniversity of Missouri-Rolla in 1994 and the M.S.degree from Purdue University, West Lafayette, IN,in 1995, both in electrical engineering.

He joined Analog Devices, Inc., Greensboro, NC,in 1996 as an Analog Integrated Circuit Designer. Hisareas of interest include high-speed data converters,frequency synthesizers, and communications circuitsand systems.

Tony Montalvo received the B.S. degree in physicsfrom Loyola University, New Orleans, LA, in 1985,the M.S. degree in electrical engineering fromColumbia University, New York NY, in 1987 and thePh.D. degree in electrical engineering from NorthCarolina State University, Raleigh, in 1995.

From 1987 to 1991, he was a Flash Memory De-signer with AMD. From 1995 to 2000, he with waswith Ericsson, Research Triangle Park, NC, where hewas the Manager of the RF and Analog IC group.Since 2000, he has been the Director of the Analog

Devices Raleigh Design Center, Greensboro, NC. He is also an Adjunct Pro-fessor at North Carolina State University. He holds 15 patents and has authoredor coauthored 10 papers.

Dr. Montalvo has been on the ISSCC Program Committee since 2002. He wasnamed Outstanding Teacher in 1995 at North Carolina State University.

Brad P. Jeffries received the B.S. degrees in elec-trical engineering and computer engineering fromNorth Carolina State University, Raleigh, in 2000.

In 2000, he joined Analog Devices, Inc., Greens-boro, NC, where he has been involved in the designof communications integrated circuits.

Frank Murden received the B.S. degree from theUniversity of Louisville, Louisville, KY, and the M.S.degree from the University of Arizona, Tucson, bothin electrical engineering.

Since graduation, he has been with Analog De-vices, Inc., Greensboro, NC, doing a wide variety ofdesigns.

Jon Strange (M’00) received the B.Sc. degree inphysics from the University of Durham, Durham,U.K., in 1984 and the M.Sc. degree in microelec-tronics from the University of Edinburgh, Edinburgh,U.K., in 1985.

From 1985 to 1987, he was a Researcher withthe VLSI Department, Thorn-EMI Central ResearchLaboratories, and from 1988 to 1991 he held severaldesign and engineering management positions forLSI Logic. In 1991, he cofounded Mosaic MicroSystems, Ltd., an analog design consultancy special-

izing in RF and radio system IC design. Since 1996, he has been with AnalogDevices, Inc., Kent, U.K., were he is currently Engineering Director within theRF and Wireless Business Unit responsible for IC product design in the area ofradio systems integration. He has authored eight technical papers and has beengranted two U.S. patents, with four pending.

Mr. Strange receoved the the Chalmers Prize in physics in 1984.

Allen Hill received the B.S. degree from GuilfordCollege, Greensboro, NC.

He is an Applications Engineer with 23 years ex-perience at Analog Devices, Inc., Greensboro, wherehe is presently with the Communications Group ofthe High Speed Converters Division.

Sanjay Nandipaku (M’00) received the B. Tech. andM.S. degrees from the Indian Institute of Technology,Madras, in 1988 and 1991, respectively, both in elec-trical engineering.

His interests lie in the area of communicationsystem design, specializing in RF wireless systemsarea. He is currently an RF System Design Engi-neer with Analog Devices, Inc., Wilmington, MA,working on the development of architectures andproducts for mobile wireless market space. Prior tothis, he was a Research Engineer with the Center for

Development of Telematics, Bangalore, India, and the RF Group Lead withMidas Communication Technologies, Madras, India.

Johannes Harrebek was born in Aarhus, Denmark,on May 11, 1971. He received the M.Sc.E.E. degreefrom University of Aalborg, Aalborg, Denmark, in1995.

He was a Research and Development (R&D)RF Engineer with Cortech from 1995 to 1998 onDECT terminal development. In 1998, he joinedBosch Telecom, Denmark, as an R&D RF engi-neer on HSCSD GSM mobile phone developmentprojects with a focus on frequency synthesis andantenna design. From 2000 to 2001, he was with

the Department of GSM/EDGE Systems, Siemens Mobile, Denmark. Hejoined Analog Devices, Inc., in 2001 on the Analog Devices EDGE radioimplementation project and is now RF Systems Development Manager withAnalog Devices Wireless System Applications Center, Aalborg, Denmark,developing form factor reference designs on the latest Analog Devices wirelesssystems solutions.

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2190 IEEE JOURNAL OF SOLID-STATE CIRCUITS, …microel_group.unisalento.it/page8/page22/files/01362828.pdf2192 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004 Fig