A New Basic Unit for Cascaded Multilevel Inverter 1

A New Basic Unit for Cascaded Multilevel Inverter with the Capability of Reducing the Number of

Switches

Sara Laali* and Ebrahim Babaei

*Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

Abstract

In this paper, a new basic unit is proposed. Then, a cascaded multilevel inverter basded on series connection of the n number of new basic units is proposed. In order to generate all voltage levels (even and odd) at the output, three different algorithms to determine the magnitude of the dc voltage source are proposed. Reduction the number of power switches, driver circuits and dc voltage sources in addition to increasing the numbr of output voltage levels are some of the advantages of the proposed cascaded multilevel inverter. These results are obtained through comparison of the proposed inverter and its algorithms with the H-bridge cascaded multilevel inverter from the number of power electronic devices points of view. Finally, the ability of the proposed topology with its proposed algorithms in generation all voltage levels is verified thruogh laboratorary prototype experimental results on a 49-level inverter. Key words: Multilevel Inverters, H-Bridge Cascaded Multilevel Inverter, New Basic Unit

I. INTRODUCTION The multilevel inverters have received more attention in comparison with the traditional two level inverters. These inverters generate stepped waveform by using a number of dc voltage sources as inputs. With an increasing the number of dc voltage sources in input side, the sinusoidal like waveform can be generated at the output that leads to high power quality, lower harmonic component and electromagnetic interference. The other advantages of the multilevel inverters are lower voltage stress on power electronic switches and high efficiency. In addition, it is possible to use of these inverters in high power and medium voltage applications [1-3]. These inverters are utilized as high power static converters in middle and high voltage applications such as electric machines drive, dynamic voltage restoration, reactive power compensators and FACTS devices [4-6]. There are three main topologies and several derivation topologies for multilevel inverters. The main topologies are diode-clamped multilevel inverters, flying capacitor multilevel inverters and cascaded multilevel inverters [3], [6]. The cascaded multilevel inverter has received special attention due to the modularity, simplicity of the control, reliability and lower power electronic devices for generation

a specific output voltage level [4-5], [7-8]. The cascaded multilevel inverters are mainly classified into two groups: symmetric cascaded multilevel inverter and asymmetric cascaded multilevel inverter [5]. In symmetric cascaded multilevel inverter the magnitude of all dc voltage sources are equal, which causes higher number of insulated gate bipolar transistors (IGBTs), power diodes and dc voltage sources to generate high number of output levels. These features lead to increasing installation space and total cost of the inverter. These are the main disadvantages of the symmetric cascaded multilevel inverters while the same value for the dc voltage sources are the most significant advantage for them. Two symmetric cascaded multilevel inverters have been presented in [10-11]. It has been also presented H-bridge cascaded multilevel inverter in [9]. In [9], two different algorithms have been presented that lead to symmetric and asymmetric topologies. In order to increase the number of output voltage levels asymmetric cascaded multilevel inverters have been presented in literatures. In asymmetric topology, the magnitude of dc voltage sources is unequal. Therefore, there are different algorithms to determine the value of dc voltage sources. In [12-13] two other algorithms as asymmetric topologies have been presented for H-bridge cascaded

2 multilevel inverters. In addition, two other topologies for asymmetric cascaded multilevel inverters have been presented in [5] and [14]. The major advantage of the asymmetric cascaded topology is considerable increasing the number of output voltage levels by using low number of dc voltage sources and power switches but the high variety in the magnitude of the dc voltage sources is the most remarkable disadvantage of them. In this paper, a cascaded multilevel inverter based on the new basic unit is proposed. This inverter increases the number of output voltage level by using minimum number of power switches, driver circuits and dc voltage sources. Then, three different algorithms to generate all voltage levels are proposed. These advantages are confirmed by comparison the proposed inverter and its algorithms with the H-bridge cascaded multilevel inverter. Finally, the obtained experimental results on a 49-level inverter reconfirm the correct performance of the proposed topology in generation all voltage levels.

II. PROPOSED TOPOLOGY The new proposed basic unit is shown in Fig.1. As Fig. 1 shows, the proposed basic unit consists of two dc voltage sources, two bidirectional switches ( 3S , 4S ) and four

unidirectional ones ( 1S , 2S , 5S and 6S ) from voltage point

of view. The bidirectional switches conduct current and voltage in two direction but unidirectional switches conduct current in two direction and blocked voltage in one direction. In addition, each unidirectional switch consists of an IGBT with an anti-parallel power diode and a driver circuit, however the bidirectional ones include of two IGBTs with two anti-parallel power diodes and a driver circuits if the switch with common emitter configuration is used. Therefore, the number of driver circuit for the bidirectional switches is as same as unidirectional ones in the proposed basic unit. According to Fig. 1, the switches ( 1S , 3S ), ( 1S , 5S ), ( 3S , 5S ),

( 2S , 4S ), ( 2S , 6S ) and ( 4S , 6S ) should not be turned on

simultaneously, because short-circuit across the dc voltage sources would be produced. Table I shows the output voltage levels of the proposed unit based on different switching patterns. In this Table, 1 and 0 indicate the on and off states of the switches, respectively. As shown in Table I, the proposed basic unit is able to generate seven voltage levels (three positive levels, three negative levels and one zero level) at the output. It is also obvious that this basic unit is able to generate all positive and negative voltage levels at the output.

Fig.1. The proposed basic unit.

TABLE I.

THE OUTPUT VOLTAGE OF THE PROPOSED BASIC UNIT BASED ON DIFFERENT SWITCHING PATTERNS

State 1S 2S 3S 4S 5S 6S ov

1 1 0 0 1 0 0 1V+

2 0 0 1 0 0 1 2V+

3 1 0 0 0 0 1 1 2( )V V+ +

4 1 1 0 0 0 0

0 0 0 0 0 1 1

5 0 1 1 0 0 0 1V

6 0 0 0 1 1 0 2V

7 0 1 0 0 1 0 1 2( )V V +

A new cascaded multilevel inverter could be made by series connection of the n number of the basic unit. This new proposed cascaded multilevel inverter is shown in Fig. 2. The output voltage of the proposed inverter is equal to adding the output voltage of each unit and can be written as follows:

,1 ,2 ,( ) ( ) ( ) ( )o o o o nv t v t v t v t= + + + (1)

where n is the number of series connected of the basic unit.

Fig. 2. Series connection of n number of the basic unit.

In the proposed cascaded multilevel inverter, the number of switches ( )switchN , IGBTs ( )IGBTN , driver circuits ( )driverN

and dc voltage sources ( )sourceN are calculated as follows:

1V

1S 2S

3S 4S

2V5S 6S

ov

ov

1,nV

1,nS 2,nS

3,nS 4,nS

2,nV

5,nS 6,nS

,o nv

1,1V

1,1S 2,1S

3,1S 4,1S

2,1V5,1S 6,1S

,1ov

A New Basic Unit for Cascaded Multilevel Inverter 3

6switchN n= (2)

8IGBTN n= (3)

6driverN n= (4)

2sourceN n= (5)

It is important to note that in the basic proposed unit determination the magnitude of dc voltage sources has most significant influence in increasing the number of generated output voltage level, used power electronic devices and so the amount of installation space and total cost of the inverter. Therefore, to generate all voltage levels, three different algorithms to determine the value of used dc voltage source will be proposed.

A. First Proposed Algorithm ( 1P )

In this sub-section, the amplitude of the two used dc voltage in the basic units is written as follows: First unit:

1,1 dcV V= (6)

2,1 2 dcV V= (7)

thn unit:

1 2

1, ,1 1

2n

n dc i ji j

V V V

= =

= + (8)

2, 1,2n nV V= (9)

In this algorithm, the number of output voltage levels ( )levelN and the maximum amplitude of the producible

output voltage ,max( )oV are respectively equal to:

7nlevelN = (10)

,max7 1

2

n

o dcV V

=

(11)

B. Second Proposed Algorithm ( 2P )

In the second proposed algorithm, the magnitudes of the dc voltage sources are determined as follows:

11, 2

jj dcV V

= (12)

2, 2j

j dcV V= (13)

Considering this proposed algorithm, the number of output voltage levels and the maximum magnitude of the output voltage are calculated as follows:

1(3 2 ) 5nlevelN+= (14)

,max 3 (2 1)n

o dcV V= (15)

C. Third Proposed Algorithm ( 3P )

In this sub-section, the values of the dc voltage sources are selected as follows:

1,1 1,1 dcV V V= = (16)

11, 3 2, 3, ,

jj dcV V for j n

= = (17)

12, 2 3

jj dcV V

= (18)

In this condition, the number of output voltage levels and the maximum magnitude of the output voltage are written as follows:

13 4nlevelN+= (19)

1

,max3 5

2

n

o dcV V+

=

(20)

III. COMPARING THE PROPOSED GENERAL TOPOLOGY WITH THE H-BRIDGE TOPOLOGY The most important aim of introducing the new-cascaded multilevel inverter and its proposed algorithms is increasing the number of output voltage levels by using less number of power electronic devices such as switches, IGBTs, power diodes, driver circuits and so on. In this section, a comparison between the proposed topology and its algorithms with H-bridge cascaded multilevel inverter is done to investigate the advantages and disadvantages of the proposed cascaded inverter.

The proposed topology based on the first, second and third proposed algorithms are considered as 1 3P P in this

investigation, respectively. In [9], the H-bridge cascaded multilevel inverter and two different algorithms have been presented. One of them is known as the symmetric cascaded inverter ( 1 2 3 n dcV V V V V= = = = = ) and another is known

as asymmetric ones ( 11 2, 2 , 2n

dc dc n dcV V V V V V= = = ). In

this comparison, these two different algorithms are considered as 1R and 2R , respectively. In order to

increasing the number of output voltage levels by using minimum number of H-bridges, two other algorithms is presented in [12-13] and are considered by 3 4R R in this

comparison ( 3R for 1 2 3, 2dc n dcV V V V V V= = = = = and

4R for 1 2 3, 3dc n dcV V V V V V= = = = = ). Fig. 3 indicates

the H-bridge cascaded multilevel inverter.

4 Fig. 4 compares the number of power electronic switches in the proposed cascaded multilevel inverter based on its proposed algorithms with the H-bridge cascaded inverter. As shown in this figure, the number of required power switches in the proposed cascaded inverter based on the first proposed algorithm is lower than the H-bridge cascaded inverter. In addition, this proposed algorithm has even better performance between other presented algorithms for the proposed topology.

Fig. 3. The H-bridge cascaded multilevel inverter

Fig. 4. Variation of switchN or driverN versus levelN

As mentioned before and based on the used power switches in the proposed topology and H-bridge cascaded inverter, the number of power switches in the proposed cascaded multilevel inverter is equal to the number of driver circuits. As a result, this topology needs less number of driver circuits than H-bridge cascaded inverter.

Because of using bidirectional switches in the proposed topology, it is necessary to compare the number of required IGBTs in this topology with the H-bridge cascaded multilevel inverter. This comparison is shown in Fig. 5. As Fig. 5 shows, the proposed cascaded topology based on the first proposed algorithm uses lower number of IGBTs than H-bridge cascaded inverter. However, the unidirectional switches are only used in the cascaded multilevel inverter. The first proposed algorithm has also best performance between other proposed algorithms in the number of required IGBTs points of view. As mentioned before, the numbers of power diodes are equal to the number of IGBTs. As a result, the number of power diodes in the proposed inverter is lower than H-bridge cascaded inverter.

Fig. 6 compares the number of dc voltage sources in the proposed topology with the H-bridge cascaded multilevel inverter. As it is obvious, the number of used dc voltage sources in the proposed topology especially based on the first

proposed algorithm, is lower than the H-bridge cascaded inverter and other presented algorithms for the proposed topology.

Fig. 5. Variation of IGBTN versus levelN

Fig. 6. Variation of sourceN versus levelN

Table II shows the comparison of the value of the blocked voltage on power switches, IGBTs and driver circuits of the proposed topology with the H-bridge cascaded inverter. As shown in this Table, the value of blocked voltage on IGBTs is completely depends on the magnitude of used dc voltage sources.

TABLE II

THE COMPARISON OF THE BLOCKED VOLTAGE ON IGBT IN THE PROPOSED TOPOLOGY AND CASCADED

MULTILEVEL INVERTER

Topology Algorithms blockV

H-bridge cascaded inverter

Presented in [9] (symmetric)

4 dcnV

Presented in [9] (asymmetric)

4(2 1)n dcV

Presented in [12] (asymmetric)

4(2 1) dcn V

Presented in [13] (asymmetric)

4(3 2) dcn V

Proposed topology

First proposed algorithm ( 1P )

8 (7 1)3

ndcV

Second proposed algorithm ( 2P )

16 (2 1)n dcV

Third proposed algorithm ( 3P )

(8 3 14)n dcV

100levelN

1R

3R 4R

2R 3P2P

1P

switchN80

120

160

200

060 8020 40

40

ordriverN

1P2R3P 2P

1R3R

4R

100

200

160

120

8060

80IGBTN

levelN200

40

40

1P2P3P 2R

3R4R

1R

50

30

10

020 40 60 80 100

20

40

levelN

sourceN

1V 2V nV1,1S 3,1S

2,1S 4,1S

1,2S

2,2S

3,2S

4,2S

1,nS

2,nS

3,nS

4,nS

ov+ oi

A New Basic Unit for Cascaded Multilevel Inverter 5

As above comparisons indicate, the lower number of required power electronic switches, driver circuits, IGBTs, power diodes and dc voltage source are the most important advantages of the proposed cascaded multilevel inverter that cause the reduction in the installation space and total cost of the inverter.

IV. EXPERIMENTAL RESULTS The correct performance of the proposed cascaded multilevel inverter in generation all voltage levels at the output is verified through experimental results on a 49-level inverter based on the basic proposed unit and shown Fig. 2. This inverter consists of two basic units, four dc voltage sources, four bidirectional switches and eight unidirectional switches. The magnitude of its dc voltage sources are determined by using first proposed algorithm. Therefore, by assuming the value of 1,1 10V V= , so the amplitude of the dc voltage

sources in the first and second units based on (7), (8) and (9) are equal to 2,1 20V V= , 1,2 70V V= , and 2,2 140V V= ,

respectively. According to (10) and (11) this inverter is able to generate 49 levels (twenty-four positive levels, twenty-four negative levels and one zero level) with the maximum amplitude of 240V at the output. It is important to note that the IGBTs used on the prototype are HGTP10N40CID (with an internal anti-parallel diode). The 89C52 microcontroller by ATMEL Company has been used to generate all switching patterns. The connected load to the inverter is considered a resistive-inductive load with the values of 60R = and

55L mH= . In this paper, the fundamental frequency

switching control method is used. The main reason to select this control method is its low switching frequency than other control methods that leads to reduction in switching losses

The experimental output voltage waveforms of the first and second units are shown in Fig. 7(a) and Fig. 7(b), respectively. As this figues show, each unit is able to generat a step waveform with the pasitive and negative amplitude. In addition, the maximum amplitude of output voltage in each unit is equal to adding the magnitude of the used dc voltage surces.

(a)

(b)

Fig. 7. The output voltages; (a) first bridge; (b) second bridge

Moreover, the experimental output voltage and current waveforms are indicated in Fig. 8. As it is obvious from Fig. 8, this inverter generates 49 levels with the maximum amplitude of 240V and 3.87A at the output. In addition, the step generated output voltage waveform consists of all pasitive and negative voltage levels and is looklike sinosuidal one. There are two differences between voltage and current waveforms while compare to each other. The current waveform is more looklike to a sinosuidal one than the voltage waveform. In addition, there is a phase shift between voltage and current. These differences are because of the resistive-inductive load feature that acts as a low pass filter.

As mentioned before, the basic proposed unit consists of two bidirectional switch and four unidirectional ones from voltage point of view. In order to investigate these facts in the proposed cascaded multilevel inverter, the blocked voltage on each switch of the first basic unit are shown in Fig 9 as instance. It is poited out that all of the obtained results are based on the first proposed algorithm. Fig. 9(a), 9(b), 9(c) and 9(d) show the blocked voltage on switches 1,1S , 2,1S ,

5,1S and 6,1S , respectively. As shown in Figs. 9(a) and 9(b),

the values of the blocked voltage on the switches 1,1S and

2,1S are 10V or 30V, which are depends on the switching

pattern. Moreover, the Fig. 9(c) and 9(d) show the blocked voltage on the switches 5,1S and 6,1S that are either 20V or

30V. It is clear that, the magnitudes of the blocked voltage on switches are either positive or zero, so there is any negative amount on them. In addition, the amount of blocked voltage is equal to add of the magnitude of the used dc voltage sources in the first basic unit. As a result, the existence of four unidirectional switches is reconfirmed in the proposed cascaded multilevel inverter. Fig. 9(e) and Fig. 9(f) show the blocked voltage by the switches 3,1S and 4,1S , respectively.

As shown in these figures, the values of the blocked voltage by them are either 10V or 20V based on different switching patterns. Moreover, there are positive and negative amount of voltages on power switches. This fact verifies that the

2.5ms

0

100V

2.5ms

10V

0

6 switches 3,1S and 4,1S are bidirectional ones.

Fig. 8. Voltage and current output waveforms.

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 9. The blocked voltage on the power switches in the first basic unit; (a) 1,1S ; (b) 2,1S ; (c) 5,1S ; (d) 6,1S ; (e) 3,1S ; (f)

4,1S .

It is important to note that these values are directly depends on the considered algorithm to determine the magnitude of dc voltage sources and by changing the selected algorithms these magnitudes will be different but their positive and negative values will be also same.

V. CONCLUSION In this paper, a new basic unit for cascaded multilevel inverters is proposed. Then, three different algorithms to determine the magnitude of the dc voltage sources are proposed. Comparisons between the H-bridge cascaded multilevel inverter and proposed inverter show the significant advantages of the proposed topology in the number of switches, driver cicuits, IGBTs, power diodes and dc voltage sources. In addition, it is obtained that the first proposed algorithm has the best performance from all proposed algorithms and the H-bridge cascaded inverter. On the other hand, if it is required to generate minimum 49 levels at the output, the proposed topology based on the first proposed algorithm and equations (2) to (5) needs 12switchN = ,

16IGBTN = , 12DriverN = and 4sourceN = while in the same

conditions, the H-bridge cascaded inverter based on binary method that is shown by 2R requires

24switch IGBT DriverN N N= = = and 6sourceN = . Finally, in

order to verify the capability of the proposed cascaded inverter in generation all voltage levels, the experimental results on a 49-level inverter is used.

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A New Basic Unit for Cascaded Multilevel Inverter 7

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Sara Laali was born in Tehran, Iran in 1984. She received the B.S. degree in electronics engineering from Islamic Azad University, Tabriz Branch, and the M.S. degree in electrical engineering from Islamic Azad University, South Tehran Branch, Iran, in 2008 and 2010, respectively.

In 2010, she joined the Department of Electrical Engineering, Adiban Higher Education Institute. Now, she is PhD student in electrical engineering at the faculty of Electrical and Computer Engineering, University of Tabriz.

Her major fields of interest include the analysis and control of power electronic converters, multilevel converters, and FACTS devices.

Ebrahim Babaei was born in Ahar, Iran in 1970. He received his B.S. and M.S. in Electrical Engineering from the Department of Engineering, University of Tabriz, Tabriz, Iran, in 1992 and 2001, respectively, graduating with first class honors. He received his Ph.D. in Electrical Engineering from the Department of Electrical and

Computer Engineering, University of Tabriz, Tabriz, Iran, in 2007. In 2004, he joined the Faculty of Electrical and Computer Engineering, University of Tabriz. He was an Assistant Professor from 2007 to 2011 and has been an Associate Professor since 2011. He is the author of more than 280 journal and conference papers. He also holds 16 patents in the area of power electronics and has more applications pending. Dr. Babaei has been the Editor-in-Chief of the Journal of Electrical Engineering of University of Tabriz since 2013. In 2013, he was the recipient of the Best Researcher Award from of the University of Tabirz. His current research interests include the analysis and control of power electronic converters and their applications, power system transients, and power system dynamics.

A New Basic Unit for Cascaded Multilevel Inverter with the Capability of Reducing the Number of SwitchesAbstract