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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI
K.K BIRLA GOA CAMPUS
SECOND SEMESTER (2013-14) Comprehensive Examinations -
PART-B
Analog Electronics (EEE/INSTR C364/F341)
Date: 08-05-2014 Time: 120 min Maximum Marks: 70 Closed Book
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Instructions: (i) Answer All questions.
(ii) Supply voltages for the op-amp is 15V and Vsat = 13V. (iii)
VD(ON) = 0.7 V.
(iv) Any required data not explicitly given, may be suitably
assumed and stated.
(v) All the answers and diagrams should be written using PEN
only. Anything
written using PENCIL will not be evaluated.
(vi) Over written answers and multiple answers will not be
evaluated.
Q1. For the circuit shown in Figure 1, (i) obtain an expression
for the output voltage
(ii) Draw the input and output waveforms for the following input
combinations.
(a) V1 = 2V , V2 = 5 sin (2103 t)V , and V3 = 2V
(b) V1 = 5 sin (2103 t) V, V2 = 2 V, and V3 = - 3V [8]
Q2. Obtain an expression for the current I through the resistor
r in the circuit shown in Figure 2. [8]
Q3. Sketch the output voltage waveform as a function of input
voltage (for both positive and
negative values) for the circuit shown in Figure 3. [8]
Figure 1
Figure 2
Vin= 5 sin (2103t)
Figure 3
VO
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Q4. Find R1 and Rf in the integrator shown in Figure 4 so that
the peak gain is 20dB and the
gain is 3 dB down from its peak when = 10,000 rad/s. Use a
capacitance of 0.01uF. [8]
Q5. Design an analog computer setup to solve the differential
equation:
with the initial condition [10]
Q6. Design a timer circuit to control the heater using 12V
relay. The relay is driven by the
output of the timer and the heater is connected to the relay
output. The lowest time duration
is 1 sec and highest time duration is 100 sec. [8]
Q7. Design an Astable Multivibrator using 741 op-amp such
that
(a) Charging time can be varied from 0.1msec to 5msec (b)
Discharging time can be varied from 0.15msec to 15msec (c) The peak
to peak output voltage required is 7V. [10]
Q8. Design a voltage regulator using IC723 to provide the output
voltage of 5 V at 1.5 A.
Foldback current limiting is to be provided so that Iknee = 1.6
A and Isc = 300 mA. Assume
the input voltage is 13 V. Refer Figure 4 for the pin
configuration. [10]
**** ALL THE BEST ****
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Figure 4
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Q1.
Vo= -V1 + V2+V3
(a)
Vo= -2 + 5 sin 2 (103)t + 2
=5 sin 2 (103)t V
(b)
Vo= - 5 sin 2 (103)t +2 -3 V
= - 5 sin 2 (103)t 1 V
Q2
R
V
VV
R
V
R
V
R
VV
VVV
R
VV
R
VV
R
V
8
3I
IRV3
V3 8 V1
(2) and (1) Using
(2)----- 3522
2
30332
-(1)--- 32241
32
2
21
2
20
Q3
During positive half cycle
D1 is reverse biased,
V0= RL/(RL+10k+20k)=10k/(10k+10k+20k)=Vi/4=1.25 sin (2103)t
During negative half cycle,
T
Time (s)
0.00 1.00m 2.00m 3.00m 4.00m
VG1
-5.00
5.00
VM1
-5.00
5.00
T
Time (s)
0.00 1.00m 2.00m 3.00m 4.00m
VG1
-5.00
5.00
VM1
-6.00
4.00
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V0=- 20k/10k(-Vi)= 25 sin (2103)t=10 sin (2103)t
Q4
Gain = 20 log (RF/R1)
RF/R1= 10
c =1/(RFC) =1/(RF0.01F)=10k
RF= 10k
Hence R1= 1k
Q5
T
Time (s)
0.00 1.00m 2.00m 3.00m 4.00m
VG1
-5.00
5.00
VM1
-2.00
10.00
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Q6
Ton= 1.1 RAC
Let C= 100 F
RA(min)= Ton/1.1C= 1sec/(1.1100F)= 9.09 k
RA(max)= Ton/1.1C= 100sec/(1.1100F)= 909 k
Q7
If we use R2= 10k then R2/R1=0.86
Then R1= 11.6 k
When V0 is positive then D1 will conduct and capacitor charges
with time constant T1= R3C
Similarly when V0 is negative then D2 will conduct and capacitor
discharges with time constant
T1= R4C
Let C=0.01 F
R3(min)= T1(min)/C=0.1msec/0.01=1 k
For T1= 5 msec , R3(max)= 5msec/0.01F= 50 k
Thus R3 is series connection of 1 k resistor and 50 k
potentiometer.
For discharging interval,
R4(min)= 0.15/0.01 1.5 k
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R4(max)= 15 msec/0.01F= 150k
Thus R4 is series connection of 1.5 k resistor and 150 k
potentiometer.
Q8
Ilimit = Vsense/Rsc= 0.6/Rsc
Rsc= 0.6/1.5A=0.4
VR2= 5V
Vref= 7.15 V
VR2=Vref (R2/R1+R2)
5V= 7.15 (R2/(R1+R2))
R2/(R1+R2)=0.699
Let R1= 1k then R2= 2.32 k
92.03
4
92.13
43
43
3
6.06.0
6.0
R
R
R
RR
RR
RVregVreg
Isc
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