A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Revision 1.05 - Fab C

**PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE

PAGETITLE

2

3,4

5

6

7,8

10

11

12,13

9

18

19

20

21

22

23

24

25

1COVER SHEET

BLOCK DIAGRAM

PGA370 PART 1 & 2

AGTL TERMINATION

CLOCK GENERATOR

GMCH PART 1 & 2

DIMM 1 & 2

17

15

16

26

INTERNAL DEBUG HEADERSDECOUPLING CAPACITORS

PU/PDR & UNUSED GATES

AGP

ICH PART 1 & 2

PCI 1 & 2

AUDIO I/O

AC97 CODEC

VIDEO BUS & CONNECTOR

LPC I/O CONTROLLER & FDCL

KB, MS, GAME & IR

ATX POWER & H/W MONITOR

DIMM 3

27

28

PCI 3

14

FRONT PANEL & CNR

29

30

VREGS: DUALS, 3.3SB, 2.5, VCMOS

WOR, WOL & 2S1P

USB 0-3

31

FWH & UDMA100 IDE 1-2

Intel® Pentium® III and FC-PGA Celeron™ Processor/815E ChipsetUniversal Socket 370 Platform Customer Reference Board Schematics

32

SYSTEM CONFIGURATION

VREGS: VCCVID, V1_8SB

VREGS: VDDQ, VCC1_8, AND VTT

THERMTRIP 33

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel orotherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditionsof Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relatingto sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arisingfrom future changes to them.

The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate frompublished specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your productorder.

I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and wasdeveloped by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including PhilipsElectronics N.V. and North American Philips Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may beobtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel®, Pentium®, Pentium® III, Celeron™, are trademarks or registered trademarks of Intel Corporation or its subsidiaries inthe United States and other countries.

*Other brands and names may be claimed as the property of others.

Copyright© 2001, Intel Corporation

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Title Page

1 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VRM

CTR

L

AD

DR

DA

TA

AD

DR

CLOCK

DA

TA

CTR

L

USB

IDE Primary

IDE Secondary

370-PIN SOCKET PROCESSOR

GMCH

ICH2

3 DIMMModules

AGPConnector

Digital Video

Out Connector

PC

I CO

NN

1

PC

I CO

NN

3

BLOCK DIAGRAM

FirmWare Hub

SIO

CNR

PCI CNTRL

PCI ADDR/DATA

AC’97 LINK

Keyboard

MouseFloppy Game Port Serial 1

GTL BUS

AudioCodec

Connector

ParallelSerial 2

USB PORT 1-4

UDMA/100

PC

I CO

NN

2

Note: PCI3Connector isnot populatedon the board

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Block Diagram

2 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

370 - Pin Socket Part 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

370-pin Socket Part 1

3 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

HA#[3..31]

HD#[0..63]

HA#3

HD#55

HD#52

HD#41

HD#34HD#33HD#32

HD#25

HD#22

HD#12

HD#2

HA#27

HA#18

HA#11

HD#35

HD#10

HD#6

HA#16

HD#43

HD#31

HD#24

HA#12

HD#42

HD#20

HD#30HD#29

HD#5

HD#3

HA#20

HD#60

HD#58

HD#48

HD#45

HD#40HD#39

HD#28

HD#56

HD#36

HD#27

HD#21

HD#15

HA#29

HA#25

HA#22

HA#14

HA#9

HD#38

HD#1HD#0

HA#13

HA#6HA#5

HD#23

HD#4

HA#21

HA#19

HA#10

HA#8

HA#4

HD#50

HD#47

HD#44

HA#31

HA#28

HA#23

HD#62HD#61

HD#57

HD#18

HD#16

HD#7

HD#59

HD#54HD#53

HD#49

HD#37

HD#8

HA#30

HA#26

HD#63

HD#51

HD#46

HD#26

HD#11

HD#9

HA#17

HA#7

HA#24

HA#15

HD#19

HD#17

HD#14HD#13

CPU_VID0

CPU_VID4CPU_VID3CPU_VID2CPU_VID1

RS#17RS#27

RS#07

HA#[3..31] 7

HD#[0..63] 7

HREQ#1 7HREQ#2 7HREQ#3 7HREQ#4 7

HREQ#0 7

JPR_VID0 29,32

JPR_VID4 29,32

JPR_VID2 29,32JPR_VID3 29,32

JPR_VID1 29,32

VCCVID

VCC3_3

VTT

VTT

RP4

1K/8P4R

1357 8

642

R372 1k

RP3

10K/8P4R

1 3 5 78642

R371

10K

U3A

Socket 370_9

W1T4N1M6U1S3T6J1S1P6Q3M4Q1L1N3U3H4R4P4H6L3G1F8G3K6E3E1

F12A5A3J3C5F6C1C7B2C9A9D8

D10C15D14D12

A7A11C11A21A15A17C13C25A13D16A23C21C19C27A19C23C17A25A27E25F16

AH26AH22AK28

AM

34A

H2

AD

2Z

2V

2M

2D

18H

2D

2A

L3

AG

5A

C5

Y5

U5

Q5

L5 G5

D4

B4

AM

6A

J7E

7B

8A

M10

AJ1

1E

11B

12A

M14

AJ1

5E

15B

16A

M18

AJ1

9E

19F

20B

20A

M22

AJ2

3D

22F

24B

24A

M26

AJ2

7D

26F

28B

28A

M30

D30

AF

32A

B32

X32

T32

P32

F32

B32

AH

34A

D34

Z34

V34

R34

M34

H34

D34

AK36

X36

T36

P36

K36

F36

A37

AC

33Y

37

AK8AH12AH8AN9AL15AH10AL9AH6AK10AN5AL7AK14AL5AN7AE1Z6AG3AC3AJ1AE3AB6AB4AF6Y3AA1AK6Z4AA3AD4X6AC1W3AF4

AL35AM36AL37AJ37

AK18AH16AH18AL19AL17C33C31A33A31E31C29E29A29

AH20AK16AL21AN11AN15G35AL13U37U35S37S33E23AN21AA35AA33

B26

C3

AK

2A

F2

AB

2T

2P

2K

2F

4E

5A

M4

AE

5A

A5

W5

S5

N5

J5 F2

D6

B6

AM

8A

J9E

9B

10A

M12

AJ1

3E

13B

14A

M16

AJ5

AJ1

7E

17B

18A

M20

AJ2

1D

20F

22A

M24

AJ2

5D

24F

26A

M28

AJ2

9D

28A

K34

F30

B30

AM

32A

H32

Z32

V32

R32

M32

H32

AF

34A

B34

X34

T34

P34

K34

F34

B34

AH

36B

22V

36R

36H

36D

36D

32A

D32

AH

24F

14K

32A

A37

Y35

HD#0HD#1HD#2HD#3HD#4HD#5HD#6HD#7HD#8HD#9HD#10HD#11HD#12HD#13HD#14HD#15HD#16HD#17HD#18HD#19HD#20HD#21HD#22HD#23HD#24HD#25HD#26HD#27HD#28HD#29HD#30HD#31HD#32HD#33HD#34HD#35HD#36HD#37HD#38HD#39HD#40HD#41HD#42HD#43HD#44HD#45HD#46HD#47HD#48HD#49HD#50HD#51HD#52HD#53HD#54HD#55HD#56HD#57HD#58HD#59HD#60HD#61HD#62HD#63

RS#0RS#1RS#2 G

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GND/VID4

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

HA#3HA#4HA#5HA#6HA#7HA#8HA#9

HA#10HA#11HA#12HA#13HA#14HA#15HA#16HA#17HA#18HA#19HA#20HA#21HA#22HA#23HA#24HA#25HA#26HA#27HA#28HA#29HA#30HA#31HA#32HA#33HA#34HA#35

VID0VID1VID2VID3

REQ#0REQ#1REQ#2REQ#3REQ#4DEP0#DEP1#DEP2#DEP3#DEP4#DEP5#DEP6#DEP7#

VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5VTT1_5

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

IDV

CC

VID

VC

CV

ID

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GTLREF Inputs ( 1 cap for every 2 inputs )

GTLREF Generation CircuitUse 0603 Packages and distribute

370 - Pin Socket

within 500 mils of processor

Part2

Place Site w/in 0.5"Do Not stuff C

of clock pin (W37)

Rds_on approx. 100mOhm @5Vgs

CMOSREF generation circuitPlace near AB36

GTLREFA to CPU. GTLREF to GMCH.

Debug only!

Debug only! Do NOT placejumper before removingR375

66M

1 0100M

BSEL#10

BSEL#0

rsvd

FSB

0

1

1

1 133M

0

Debug sites only.

Do not stuff R330

Stuff resistor

only on non-UMB

platforms.

Tua

No-stuff R199 - see p.33.

Stuff either R5 or R415. See p33.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

370-pin Socket Part 2

4 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

GTLREFA

PLL2

SLEWCNTR

FLUSH#

RTTCNTR

PLL1

ITP_VTT

ITP_DBRESET

ITP_CPURESET

AG1_VTT/NC

GTLREFA

CMOSREF

TUALDET

NCHCTRLP

DYN_OE

RESET2#

A20M# 12

VTIN2 21,25

BPRI# 7

HITM# 7

BR0# 5

THRMDN 21,25

BNR# 7

FERR# 12

STPCLK# 12

INTR 12

HLOCK# 7

HTRDY# 7

IGNNE# 12

CPUSLP# 12

HIT# 7

NMI 12

DRDY# 7

BSEL#1 29,32

DEFER# 7

INIT# 12,17

HADS# 7

BSEL#0 29,32

SMI# 12

DBSY# 7

APICD112

CPUHCLK6APICCLK_CPU6

CPU_PWGD12,33

ITPRDY#5

ITPCLK6

GTLREF 7,32

VTTPWRGD26

APICD012

TUAL56,7,26

TUAL5#

TUAL5 6,7

CPURST#7,33

CMOSREF

GTLREFA 32

DBRESET#25

THERMTRIP# 33

N639540333

VCC2_5

VTT

VTT

V3SB

VCCVID

V3SB

VTT VCC2_5

VTT

VTT

VTT

VCC5

VCC5

VTT

VTT

VCMOS

Q27FDN335N

Q262N3904

R344

1k

R338

75 1%

R406

1k

R339

150 1%

BC228

0.1uF

R3432.2k

Q252N7002

R3412.2k

R340

1k

R330 X0

R373330

FB30BEAD1 2

R346

1k

PR7

75,1%

R8

330

PR1

56,%1

R33

90.9,1%

BC12

0.1UF

BC18

0.1UF

R199

1.8k R4

1K

C12

10PF

R5

39 R3

1K

R6

39

R7

150 R2

150

MC7

4.7UF

R13

330

BC1

0.1UF

R275

22

+

C6

33uF (C size)

BC16

0.1UF

BC7

0.1UF

R345 1k

R14

150

PR8

150,1%

PR5

110,%1

R1

150

PR6

150,1%

BC17

0.1UF

R15

150

PR4

150,1%

L2

4.7UH/SMD-0805

C3

X18PF

R315 0

R319

243,1%

J2

XHEADER_15X2

2 14 36 58 7

10 912 1114 1316 1518 1720 1922 2124 2326 2528 2730 29

2 14 36 58 710 912 1114 1316 1518 1720 1922 2124 2326 2528 2730 29

R9

680

R316 0R317 0

R318 243,1%

R342 1k

R314

1K

U3B

Socket 370_9

X2

AG1

C37E21

AJ33AJ31

AN29

AL29AL31

AH28

S35

W33U33

E27

AN35AN37AN33AL33AK32

J37A35

G33E37C35E35

N33N35N37Q33Q35Q37

AK30

AM2F10

W35Y1R2

G37L33

J35L35J33

W37Y33

AK26AH4

X4

AB

36A

D36

Z36

E33

F18

K4

R6

V6

AD

6A

K12

AK

22

AH14AN17AN25AN19AK20AN27AL23AL25AL27AN31AE37

AE33AG35AH30AJ35M36L37AG33AC35AG37AE35

AC37AL11AN13AN23

B36AK24V4

AN3AK4

AJ3AF36

AL1

RESVD21(BR1#)

EDGCTRL/VRSEL

CPUPRES#VCOREDET

BSEL0#BSEL1#

BR0#

THRMDNTHRMDP

THERMTRIP#

RTTCNTR

PLL1PLL2

SLEWCNTR

TDITDOTRST#TCKTMS

PREQ#PRDY#

BP2#BP3#BPM0#BPM1#

RSRVD6RSRVD7RSRVD8RSRVD9RSRVD10RSRVD11

RSRVD12/JBSEL1#

RSRVD13RSRVD15RSRVD16RSRVD17RSRVD18RSRVD19RSRVD20

PICD0PICD1PICCLKBCLKCLKREFPWRGOODRESET#RESET2#

V_C

MO

SV

1_5

V2_

5

VR

EF

0V

RE

F1

VR

EF

2V

RE

F3

VR

EF

4V

RE

F5

VR

EF

6V

RE

F7 BNR#

BPRI#TRDY#

DEFER#LOCK#DRDY#HITM#

HIT#DBSY#

ADS#FLUSH#

A20M#STPCLK#

SLP#SMI#

LINT0/INTRLINT1/NMI

INIT#FERR#

IGNNE#IERR#

RSP#AP0#AP1#RP#

BINIT#AERR#BERR#

DYN_OEVTTPWRGD

RSVD - NCTUALDET

RSRVD21

R374

14

R375 0

JP6

JUMPER

C163

0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VTT Decoupling

Debug cap sites - place near processorDo not populate in assembly - debug sites only.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VTT Decoupling

5 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

ITPRDY# 4

BR0# 4

VTT

VTT

VTT

R12 150

R23 56

MC23

4.7UF

MC22

4.7UF

BC34

0.1UF

BC35

0.1UF

BC36

0.1UF

BC37

0.1UF

BC38

0.1UF

BC24

0.1UF

BC23

0.1UF

BC5

0.1UF

BC14

0.1UF

BC22

0.1UF

BC9

0.1UF

BC15

0.1UF

BC2

0.1UF

BC13

0.1UF

BC3

0.1UF

C164820uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Clock power gate

Rds_on = 100 mOhm.

Ensure that the buffer used will disableits PLL and tristate outputs when norefclk is present; otherwise, must gatepower here, too.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Clock Generator

6 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

MEMV3PCIV3

L_VCC2_5

AV3 USBV3

PCLK_REF

MEMCLK4MEMCLK1

MEMCLK8MEMCLK5

MEMCLK11MEMCLK6

MEMCLK0

MEMCLK11

MEMCLK7

MEMCLK10

MEMCLK[0..7]

MEMCLK9MEMCLK8

MEMCLK4

MEMCLK3MEMCLK2MEMCLK1MEMCLK0

MEMCLK2

MEMCLK10

MEMCLK5MEMCLK6

MEMCLK3 MEMCLK7

MEMCLK9

MEMCLK[8..11]

AGPCLK_CONN11

ICH_3V6613GMCH_3V668

SLP_S3#13,21,28

R_SMBDATA32R_SMBCLK32

ICH_CLK1413

FMOD129

PCLK_0/ICH12

FMOD029

GMCHHCLK 7

SIO_CLK24 21

APICCLK_CPU 4

MEMCLK[8..11] 10

APICCLK_ICH 12

MEMCLK[0..7] 9

DCLK_WR 7

USBCLK 13DOTCLK 8

PCLK_8 17

PCLK_2 14

PCLK_7 21PCLK_3 15

PCLK_1 14

VTTPWRGD1226

TUAL5 4,7,26

ITPCLK 4CPUHCLK 4

VCC2_5

VCC3_3

VCC_CLOCK

VCC_CLOCKVCC_CLOCK

VCC_CLOCK

VCC3_3

VCC_CLOCK

BC227

0.1UF

BC226

0.01UF

MC18

4.7UF

PFB2

BEAD

1 2

BC31

0.1UF

BC32

0.01UF

BC56

0.1UF

BC55

0.01UF

PFB4

BEAD

1 2

BC59

0.01UF

BC57

0.01UF

BC58

0.1UF

BC62

0.01UF

BC61

0.1UF

MC29

4.7UF

MC28

4.7UF

PFB5

BEAD

1 2

R347

0

BC60

0.1UF

R348

130Q28

2N7002

BC26

0.01UF

BC25

0.1UF

MC21

4.7UF

C3318PF

C3518PF

R58 33

R45 33R46 33

RN19 22/8P4R1357

2468

R57 33

R320 33

RN20 22/8P4R1357

2468

R50 22

R62 22R63 22

Y3

14.318MHZ

R44 22

R51 22

C19

X10PF

C21

X10PF

C20

X10PF

R277 33

CN4

X10P/8P4C

1 3 5 782 4 6

1 3 5 782 4 6 CN5

X10P/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

C34

X10PF

C31

X10PF

C23

X10PF

C22

X10PF

CN6

X10P/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

C120

X10PF

C41

X10PF

C42

X10PF

C40

X10PF

C39

X10PF

U6

ICS9250-28

54531

51504746

45424138

37363332

2627

3 55 8 13 17 19 24 30 34 39

2 5 9 14 20 25 31 35

6

74

56

101112

1516

212223

29

1828

40 44 49

43 48 52

CPUCLK_0CPUCLK_1

IOAPIC

SDRAM0SDRAM1SDRAM2SDRAM3

SDRAM4SDRAM5SDRAM6SDRAM7

SDRAM8SDRAM9

SDRAM10SDRAM11

48MHZ_048MHZ_1

GN

DL

GN

DL

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VD

DL

VD

DV

DD

VD

DV

DD

AV

DD

VD

DV

DD

X1

X2REF0

VD

DL

3V66-03V66-13V66-2

PCICLK0PCICLK1

PD#SCLKSDATA

SDRAM12

FS0FS1

VD

DV

DD

VD

D

GN

DG

ND

GN

D

C29

X10PF

R64 33

R290 33R67 33

R65 33R66 33

R49 33

R47 33

RN34

33/8P4R

1357

2468

R48 33

C25

X10PF

C24

X10PF

C28

X10PF

C30

X10PF

C133

X10PF

Q29FDN359AN

R72 10

PFB11

BEAD

1 2

R249 8.2K

U29

ICS9112B-17

1 671011

16

125

413

231415

98

REF CLKB1CLKB2CLKB3CLKB4

CLKOUT

GNDGND

VDDVDD

CLKA1CLKA2CLKA3CLKA4

FS1FS2

R312 X33

C132

X18PF

R303

10K

R302

10K

PFB12

BEAD

1 2

BC222

0.01UF

BC221

0.1UF

MC66

4.7UF

R60 10

BC28

0.01UF

BC27

0.1UF

BC29

0.01UF

BC30

0.1UF

MC20

4.7UF

MC19

4.7UF

PFB1

BEAD

1 2

BC33

0.01UF

BC21

0.1UF

BC63

0.01UF

BC64

0.1UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Host Interface

SM_WE#SM_MAA9SM_CAS#SBA7SM_BS0SM_BS1SM_MAA10SM_MAA11SM_MAA12

SM_RAS#

Host Freq : HI=100 LO=66FSB P-MOS Kicker : HI=NON-Cu LO=CuHost Freq : HI=133 LO=100/66LM FREQ : HI=133 LO=100

SM/LM muxing strap , active low

IOQ depth : HI=4 LO=1ALLZ : LO=ALLZ HI=Normal

XOR chain : LO=XOR HI=Normal

SYSTEM MEMORY

Do Not Stuff C

Place Site w/in

0.5" of clock

ball(v6)

Place close

to GMCH

Backside decouping , should beplaced under chipset memory signalfield

Backside decouping , should beplaced under chipset AGP signalfield

Debug sites only.

Place

near GMCH

LO = Future 0.13u Socket 370 processorsHI = Pentium(R) III Processor or Intel(R)

Celeron(tm) Processor w/CPUID = 068Xh

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

GMCH Part 1

7 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

HD#[0..63]

HA#[3..31]

HREQ#1

HD#61

HD#25

HREQ#0

HD#58HD#57

HD#51

HD#33

HD#24

HD#13

HD#49

HD#32

HD#29

HA#31

HD#62

HD#48

HD#30

HD#9

HD#0

HA#30

HD#39

HD#10

HD#5HD#4

RS#0

HD#53

HD#42

HD#28

HD#63

HD#55

HD#40

HD#26

HD#16

HD#8

HD#3

HD#38HD#37

HD#1

HD#47

HD#43

HD#11

HD#56

HD#54

HD#44

HD#41

HD#27

HD#19

HA#29

HD#22

HREQ#4

HD#45

HD#23

HD#17

HD#14

HD#52

HD#46

HD#34

HD#20

HD#18

HD#2

HREQ#3

HD#60

HD#35

HD#31

HD#15

HD#7

HREQ#2

HD#59

HD#6

HD#50

HD#36

HD#21

HD#12

HA#3HA#4HA#5HA#6HA#7HA#8HA#9

HA#16

HA#12HA#13

HA#11

HA#14

HA#10

HA#15

HA#17HA#18HA#19HA#20HA#21HA#22HA#23

HA#26HA#27

HA#25

HA#28

HA#24

RS#2RS#1

SM_MAA4SM_MAA5SM_MAA6SM_MAA7

SM_MD28

SM_MD9

SM_MD6

SM_CKE1

SM_MAA11

SM_MAA3

SM_MD50

SM_MD42

SM_MD32

SM_MD7

SM_CSA#2

SM_MD54

SM_MD45

SM_MD15

SM_CSB#1

SM_MD61

SM_MD48

SM_MD16

SM_MD0

SM_CSA#0

SM_MAA0

SM_DQM5

SM_MD63

SM_MD36

SM_MD24

SM_MD19

SM_CSB#0

SM_MD41

SM_MD33

SM_MD21

SM_MD3

SM_CKE0

SM_CSB#3

SM_MAA8

SM_MD51

SM_MD35

SM_MD29

SM_MD13

SM_MD10

SM_CSA#1

SM_MAA12

SM_MAA2

SM_MD55

SM_MD53

SM_MD43

SM_MD12

SM_CKE3

SM_CSA#3

SM_MAA9

SM_DQM2

SM_MD59SM_MD58

SM_MD56

SM_MD46

SM_MD2

SM_DQM4

SM_MD62

SM_MD37

SM_MD17

SM_MAA1

SM_DQM0

SM_MD39

SM_MD22

SM_DQM7

SM_MD34

SM_MD26

SM_MD1

SM_MD52

SM_MD40

SM_MD31SM_MD30

SM_MD11

SM_MD8

SM_MD5

SM_CKE2

SM_CSB#2

SM_DQM1

SM_MD49

SM_MD44

SM_MD14

SM_MD4

SM_DQM3

SM_MD60

SM_MD57

SM_MD47

SM_MD23

SM_MD38

SM_MD27

SM_MD20

SM_MD18

SM_DQM6

SM_MD25

SM_MAA10

SM_MD[0..63]

SM_MAA[0..12]

SM_DQM[0..7]

SM_WE#

SM_MAB#[4..7]

SM_CKE[0..3]

SM_MAC#[4..7]

SM_MAC#7SM_MAC#6

SM_MAB#5SM_MAB#6

SM_MAC#4

SM_MAB#4

SM_MAB#7

SM_MAC#5

SM_CSA#4SM_CSA#5

SM_CSB#5SM_CSB#4

SM_CKE4SM_CKE5

SM_CKE[4..5]

SM_CSA#[0..3]

SM_CSA#[4..5]

SM_CSB#[0..3]

SM_CSB#[4..5]

SM_MAA9

SM_CAS#

SM_MAA10

SM_RAS#

SM_MAA12

HD#[0..63] 3

CPURST#4,33HLOCK#4DEFER#4

HADS#BNR#4BPRI#4DBSY#4DRDY#4HIT#4HITM#4HTRDY#4

HA#[3..31]3SM_BS09,10SM_BS19,10

SM_RAS#9,10SM_CAS#9,10SM_WE#9,10

DCLK_WR6

PCIRST#16,17,21,30GMCHHCLK6

SM_MAA[0..12]9,10

SM_DQM[0..7]9,10

SM_MD[0..63] 9,10SM_MAB#[4..7]9

SM_CKE[0..3]9

SM_MAC#[4..7]10

SM_CKE[4..5]10

SM_CSA#[4..5]10

SM_CSA#[0..3]9

SM_CSB#[4..5]10

SM_CSB#[0..3]9

R_BSEL#0 29

R_REFCLK 29

HREQ#03HREQ#13HREQ#23HREQ#33HREQ#43

RS#03RS#13RS#23

GTLREF32

TUAL54,6,26

VTT

VCC3SBY

VCC3SBY

VDDQ

VTT

VTT

BC72

0.1UF

BC73

0.1UF

C38X18PF

RN37

10/8P4R

1357

2468

C36

22PF

PR9 40.2,1%

RN36 10/8P4R

1357

2468

RN38 10/8P4R1357

2468

R68 X10K

R77 X10K

BC188

X0.1UF

BC190

X0.1UF

BC191

X0.1UF

BC189

X0.1UF

BC192

X0.1UF

BC193

X0.1UF

BC194

X0.1UF

BC195

X0.1UF

U7A

U6AA10

AA7H3

AA5L4

M3G1N4M5J3J1K1L3K3

R4P1T2R3N5P5R1U1P2T1T3P3T5R5V5Y2V3W1U4V2W3W4U5Y5Y3U3Y1W5V1

M1N1M2L5N3

K2L1H1

AA1AB2AF2AD4AB1AB3AA3AC4AC1AF3AD1AE3AD2AD3AF1AA4AD6AC3AE1AB6AF4AE5AC8AB5AF5AC6AF6AD11AF8AD8AD5AB7AF7AD7AB8AE7AE9AB9AF9AD10AF12AB11AB10AD9AC10AF10AD14AD12AB12AE11AE15AF11AF13AB14AF14AB13AB15AE13AC14AD13AD15AF16AF15AC12

GTLREFAGTLREFB

HCLKRESET#CPURST#HLOCK#DEFER#ADS#BNR#BPRI#DBSY#DRDY#HIT#HITM#HTRDY#

HA#3HA#4HA#5HA#6HA#7HA#8HA#9HA#10HA#11HA#12HA#13HA#14HA#15HA#16HA#17HA#18HA#19HA#20HA#21HA#22HA#23HA#24HA#25HA#26HA#27HA#28HA#29HA#30HA#31

HREQ#0HREQ#1HREQ#2HREQ#3HREQ#4

RS#0RS#1RS#2

HD#0HD#1HD#2HD#3HD#4HD#5HD#6HD#7HD#8HD#9

HD#10HD#11HD#12HD#13HD#14HD#15HD#16HD#17HD#18HD#19HD#20HD#21HD#22HD#23HD#24HD#25HD#26HD#27HD#28HD#29HD#30HD#31HD#32HD#33HD#34HD#35HD#36HD#37HD#38HD#39HD#40HD#41HD#42HD#43HD#44HD#45HD#46HD#47HD#48HD#49HD#50HD#51HD#52HD#53HD#54HD#55HD#56HD#57HD#58HD#59HD#60HD#61HD#62HD#63

U7B

82815 GMCH

B13D11

G7

D13B16F12A16B12A12C11A11D12C13E11A13B7

B15A15C14A14

B10A10C10

A9

D15A17D14E14E13B17

F9F8

D10D9B9A8

C16D18E16

D8E8E9D7C8C7

F7G10

D16F15A7A6

A18C17

B6A5

D23C23D22F21E21G20F20D20F19E19D19E18B18F18G18D17A3A1C1F2G3D6C5B4D4C2D3E4F5G4J6K5A26A25B24A24B23A23C22A22D21B21A21C20B20A20C19A19A4A2B1E1G2E6D5C4B3D2E3F4F6G5H4J4

SBS0SBS1

SRCOMP

SMAA0SMAA1SMAA2SMAA3SMAA4SMAA5SMAA6SMAA7SMAA8SMAA9SMAA10SMAA11SMAA12

SMAB#4SMAB#5SMAB#6SMAB#7

SMAC4SMAC5SMAC6SMAC7

SCSA#0SCSA#1SCSA#2SCSA#3SCSA#4SCSA#5

SCSB#0SCSB#1SCSB#2SCSB#3SCSB#4SCSB#5

SRAS#SCAS#SWE#

SCKE0SCKE1SCKE2SCKE3SCKE4SCKE5

SCLKRESVD

SDQM0SDQM1SDQM2SDQM3SDQM4SDQM5SDQM6SDQM7

SMD0SMD1SMD2SMD3SMD4SMD5SMD6SMD7SMD8SMD9

SMD10SMD11SMD12SMD13SMD14SMD15SMD16SMD17SMD18SMD19SMD20SMD21SMD22SMD23SMD24SMD25SMD26SMD27SMD28SMD29SMD30SMD31SMD32SMD33SMD34SMD35SMD36SMD37SMD38SMD39SMD40SMD41SMD42SMD43SMD44SMD45SMD46SMD47SMD48SMD49SMD50SMD51SMD52SMD53SMD54SMD55SMD56SMD57SMD58SMD59SMD60SMD61SMD62SMD63

R90 8.2K

R89 8.2K

R88 10K

FB31BEAD

1 2

PR42

63.4 1%

PR43

150,1%

R34910k

Q302N7002

R407

56

C168

0.1uFR61

90.9,1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A APower and Ground

Display Cache, Video, andHUB Interface

of clock ball(AA21)

Do Not Stuff C

Place as close as

Possible to GMCH

and via straight

to VSS plane

Place R as

Close as

possible to

GMCH

Place Site w/in 0.5"

OCLK = 0.5"RCLK = 1.5"

NOTE : Place as close as

Possible to GMCH

and via straight

to VSS plane

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

GMCH Part 2

8 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

GAD13

GAD15

GAD7

GAD26

GAD2

GAD5

GAD25

GAD21

GAD0

GAD23

GAD28

GAD22

GAD10

GAD24

GAD31

GAD20GAD19GAD18

GAD30

GAD16

GAD1

GAD3

GAD8

GAD29

GAD9

GAD17

GAD12

GAD14

GAD27

GAD6

GAD11

GAD4

GAD[0..31]

OCLKRCLK

FTD7FTD6

FTD11

FTD3FTD2

HL7

HL9

FTD1

FTD5

HL5

HCOMP

HL4

HL10

HL2

FTD10FTD9

FTD4

HL3

FTD8

HL0

HL6

SBA[0..7]

HL1

HL[0..10]

FTD[0..11]

FTD0

HL8

GRCOMP

HUBREF_GMCH

GAD[0..31]11

GCBE#011GCBE#111GCBE#211GCBE#311

GDEVSEL#11GFRAME#11

GIRDY#11GTRDY#11GSTOP#11GPAR11GREQ#11GGNT#11PIPE#11

ADSTB011ADSTB0#11ADSTB111ADSTB1#11SBSTB11SBSTB#11

ST011ST111ST211

RBF#11WBF#11

GMCH_AGPREF 11

FTCLK0 16

FTHSYNC 16

3VFTSCL 16

3VDDCCL 16

FTD[0..11] 16

VID_BLUE 16

VID_RED 16CRT_HSYNC 16

HL[0..10] 12

SBA[0..7] 11

SL_STALL 16

HLSTB 12

FTBLNK# 16

FTVSYNC 16

CRT_VSYNC 16

HLSTB# 12

VID_GREEN 16

FTCLK1 16

3VFTSDA 16

3VDDCDA 16

GMCH_3V66 6

DOTCLK 6

CONN_AGPREF11,32

SBA0 11SBA1 11SBA2 11SBA3 11SBA4 11SBA5 11SBA6 11SBA7 11

VDDQ

VCC1_8VCC3SBYVDDQ

VCC1_8

VCC1_8

VCC1_8

PR15

40.2,1%

PR14 15.1%

C61

15PF/5%,MPO

PR13

174,1%

PR23

1K,1%

PR21

82,1%

PR24

82,1%

PR22

1K,1%

C69

560PF

C72

560PF

PR16

301,1%

PR18

40.2,1%

C58

10PF

BC89

0.1UF

PR17

301,1%

BC90

0.1UF

U7D

82815 GMCH

AF24AE25

W6Y9

Y18AA6AA8

AA11AA13AA15AA17AA19AB16AB20AC22AD19

C25E24F23G22

J7K6M6P6T6V7

G26

AA21Y7

E23AF26AF25

B2B5B8

B11B14B19B22B25E2

F10F14F17G6G8

G19H2H5H7

K20Y24L21

M23U25N25R21U20U23W20

AB4E7AC2AC5AC7AC9AC11AC13AC15AC17AC19AC21AC25AE2AE4AE6AE8AE10AE12AE14AE16AE18AE20B26C3C6C9C12C15C18C21C24D1E5E10E12E15E17E20E22F1F3F11F13T21U2U7K24V4V6V20V22W2W7W23W25Y4Y6Y8Y10Y17Y19AA2AA9AA12AA14AA16

GNDGND

VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8VCC_1.8

VCC1_8VCC1_8VCC1_8VCC1_8VCC1_8

VCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBYVCC3SBY

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

U7E

Solano

P11P12P13P14P15P16R2R6

R11R12R13R14R15R16R23R25

T4T11T12T13T14T15T16L15L16L22M4

M11M12M13M14M15M16L25

N2N6N11N12N13N14N15N16N23AA23F16F25G9G17G21G23P24H6H22J2J5J23J25K4K7K21L2L6L11L12L13L14AA25P4

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

R251 22

U7C

82815 GMCH

K26J22K25J21L24J20L26K23K22M25M24M26M21N24N22N26T26T22U24T23U26T24V24U21V25V21V26W21W24W22W26Y21

H23N21T25Y26

R26P26P23P21P25R24

AE26AD25AC26

M22L23U22V23Y23

AA24

AD24AC24AC23

AD26AB24

J24J26R22P22

AD16AF17AE17AD17AF18AD18AF20AD20AC20AF21AE21AD21AB19AC18AE19AF19AC16AB17

AB21AA20

AA18AB18

AE24Y20AD23

AF22AF23AD22AE22AE23

F22H24H26H25G24F24E26E25D26D25D24C26H21G25F26H20

AB22AB25AB23AB26AA22AA26Y22Y25

GAD0/LDQM0GAD1/LMD4GAD2/LMD7GAD3/LMD3GAD4/LMD6GAD5/LMD2GAD6/LMD5GAD7/LMD1GAD8/LMD0GAD9/LMA4GAD10/LDQM1GAD11/LMA2GAD12/LMD8GAD13/LMA5GAD14/LMD9GAD15/LMA1GAD/16/LMA8GAD17/LMD14GAD18/LMA11GAD19/LMD15GAD20/LMA9GAD21/LMD16GAD22/LCS#GAD23/LMD17GAD24/LCKEGAD25/LMD18GAD26/LCAS#GAD27/LMD19GAD28/LTCLK1GAD29/LMD20GAD30/LTCLK0GAD31/LMD21

GCBE#0/LMA3GCBE#1/LMD10GCBE#2/LMD13GCBE#3/LRDS#

GFRAME#/LMA10GDEVSEL#/LMD11GIRDY#/LMD12GTRDY#/LMA7GSTOP#/LMA0GPAR/LMA6GREQ#/LMD27GGNT#PIPE#/LMD24

ADSTB0ADSTB0#ADSTB1ADSTB1#SBSTBSBSTB#

ST0/LMD28ST1/LDQM3ST2/LMD29

RBF#/LMD30WBF#AGPREFGRCOMPOCLOCKRCLOCK

LTVDATA0LTVDATA1LTVDATA2LTVDATA3LTVDATA4LTVDATA5LTVDATA6LTVDATA7LTVDATA8LTVDATA9

LTVDATA10LTVDATA11

BLANK#TVCLKIN/SL_STALL

CLKOUT0CLKOUT1TVVSYNCTVHSYNC

LTVCKLTVDA

DDDADDCK

DCLKREFIWASTE

IREF

VSYNCHSYNC

REDGREEN

BLUE

HCLKHL0HL1HL2HL3HL4HL5HL6HL7HL8HL9

HL10HUBREF

HLSTBHLSTB#HCOMP

SBA0/LMD31SBA1/LMD25SBA2/LDQM2SBA3/LMD26SBA4/LMD23SBA5/LWE#

SBA6/LMD22SBA7/LGM_FREQ_SEL

L6 22nH

C169

33uF

C170

0.1uF

C171

0.01uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CH6-12

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

DIMMs 1 and 2

9 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

SM_CKE0

SM_MAA2 SM_MAA2

SM_DQM7

SM_MD48

SM_MD29

SM_BS0

SM_DQM5

SM_MD55

SM_MD2

SM_MAA0

SM_CKE2

SM_MD44

SM_MD39

SM_MD41

SM_MD57

SM_MD34

SM_MD40

SM_MD56

SM_MD21

MEMCLK6

SM_MD8

SM_MD4

SM_CKE3

MEMCLK1

SM_DQM2

SM_MD37

SM_MD32

SM_MD17

SM_MD36

SM_MD15

SM_MAB#6

SM_MD52

SM_CSA#0

SM_MD12

SM_MD24

SM_MD19

SM_MD3

SM_MD60

SM_MAA11

SM_MD27

SM_CSA#2

SM_MD31

SM_CAS#

SM_MAA10

SM_MD54

SM_MD16

SM_MAB#4SM_MAA3

SM_MD44

MEMCLK0

SM_MD49

SM_DQM4

SM_CSB#2

SM_MD51

SMBDATA

SM_MD46

SM_RAS#

SM_MD15

SM_MD20

SM_MD61

SM_MD20

SM_MD63

SM_CSB#1

SM_DQM1

SM_MD51

SM_MD32

SM_MD58

MEMCLK4

SM_MD18

SM_MD57

SM_MD9

SM_MAA1

SM_MAB#5

SM_MD10

SM_MD27

SM_MD18

SM_DQM6

SM_MD23

SM_MD17

SM_MD5

SM_MD24

SM_MD42

SM_MD34

SM_MD62

SM_MD11 SM_MD43

SM_MD25

SM_MD59

SM_MAA9

SM_CSA#1

SM_MD8

SM_MD1

SM_MD5

SM_MD26

SM_MAA8

SM_MD21

SM_MD42

SM_MD6

SM_MD12SM_MD45

SM_MD54

SM_CSB#3

SM_MD3

SM_MD14

SM_DQM5

SM_CSB#0

SM_MD56

SM_WE#

SM_MAA8

SM_MD35

SM_DQM4

SM_MD60

SM_MD45

SM_MD26

SM_MD48

SM_MAA12

SM_MD25

SM_MD61

SM_MAA7

SM_MD10

SM_MD40

SM_WE#

SM_MD41

SM_MD22

SM_BS0

MEMCLK7MEMCLK3

SM_MD55

SM_MAA1

SM_MD35

SM_DQM7

SM_MD38SM_MD39

SM_MD19

SM_MAA9

SM_MD7

SM_CSA#3

SM_MD47

SM_RAS#

SMBDATA

SM_MD62

SM_MAA12

MEMCLK2

SM_MD53

SM_MAA10

SM_MD7

SM_MD0

SM_CAS#

SM_MAA4

SM_CKE1

SM_MD2

SM_MD14

SM_MD22

SM_MAA11

SM_MD13

SM_MD23

SM_MAA6

SM_MD28

SM_MD58

SM_MD50

SM_MD4

SM_MAA0

SM_DQM6

MEMCLK5

SM_DQM3

SM_MAA3

SM_MD30

SM_MAA5

SM_MD47SM_MD46

SM_MD50

SM_MD0

SM_MD63

SM_MD6

SM_MD36

SM_BS1

SM_DQM0

SM_MD43

SM_MD28

SMBCLK

SM_MD13

SMBCLK

SM_MD33

SM_MAB#7

SM_MD30

SM_MD16

SM_MD38

SM_MD52

SM_DQM3

SM_MD49

SM_MD9

SM_DQM2

SM_DQM1

SM_MD29

SM_MD37

SM_MD31

SM_MD59

SM_MD11

SM_MD53

SM_BS1

SM_DQM0

SM_MD1SM_MD33

MEMCLK[0..7]

SM_CKE[0..3]

SM_CSA#[0..3]

SM_CSB#[0..3]

SM_DQM[0..7]

SM_MAB#[4..7]

SM_MD[0..63]

SM_MAA[0..12]

SM_WE#

SM_RAS#

SM_CAS#

SM_BS0

SM_BS1

SMBDATASMBCLK

DM_SA_PU 10

SM_MAA[0..12] 7,10

SM_MD[0..63] 7,10

SM_MAB#[4..7] 7

SM_DQM[0..7] 7,10

MEMCLK[0..7] 6

SM_CKE[0..3] 7

SM_CSA#[0..3] 7

SM_CSB#[0..3] 7

SM_WE# 7,10

SM_RAS# 7,10

SM_CAS# 7,10

SM_BS0 7,10

SM_BS1 7,10

SMBDATA 10,13,21,24,30,32SMBCLK 10,13,21,24,30,32

VCC3SBY

VCC3SBY VCC3SBYVCC3SBYVCC3SBY

R282.2K

DIMM2

DIMM168

123456789

101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384

858687888990919293949596979899100101102103104105106107

109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168

108

VSSDQ0DQ1DQ2DQ3VDDDQ4DQ5DQ6DQ7DQ8VSSDQ9DQ10DQ11DQ12DQ13VDDDQ14DQ15CB0CB1VSSCB8CB9VDDWE#/WE0#DQM0DQM1CS0#DU/OE0#VSSA0A2A4A6A8A10/APBA1/A12VDDVDDCLK0/DUVSSDU/OE2#CS2#DQM2DQM3DU/WE2#VDDCB10CB11CB2CB3VSSDQ16DQ17DQ18DQ19VDDDQ20NCVREF/DUCKE1VSSDQ21DQ22DQ23VSSDQ24DQ25DQ26DQ27VDDDQ28DQ29DQ30DQ31VSSCLK2/NCNCWPSDASCLVDD

VSSDQ32DQ33DQ34DQ35VDD

DQ36DQ37DQ38DQ39DQ40

VSSDQ41DQ42DQ43DQ44DQ45VDD

DQ46DQ47

CB4CB5VSS

CB13VDD

CAS#/DUDQM4DQM5CS1#

RAS#/DUVSS

A1A3A5A7A9

BA0/A11A11/A13

VDDCLK1/DU

A12/DUVSS

CKE0/DUCS3#

DQM6DQM7

A13/DUVDD

CB14CB15CB6CB7VSS

DQ48DQ49DQ50DQ51VDD

DQ52NC

VREF/DUREGE

VSSDQ53DQ54DQ55

VSSDQ56DQ57DQ58DQ59VDD

DQ60DQ61DQ62DQ63

VSSCLK3/NC

NCSA0SA1SA2VDD

CB12

DIMM1

DIMM168

123456789

101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384

858687888990919293949596979899100101102103104105106107

109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168

108

VSSDQ0DQ1DQ2DQ3VDDDQ4DQ5DQ6DQ7DQ8VSSDQ9DQ10DQ11DQ12DQ13VDDDQ14DQ15CB0CB1VSSCB8CB9VDDWE#/WE0#DQM0DQM1CS0#DU/OE0#VSSA0A2A4A6A8A10/APBA1/A12VDDVDDCLK0/DUVSSDU/OE2#CS2#DQM2DQM3DU/WE2#VDDCB10CB11CB2CB3VSSDQ16DQ17DQ18DQ19VDDDQ20NCVREF/DUCKE1VSSDQ21DQ22DQ23VSSDQ24DQ25DQ26DQ27VDDDQ28DQ29DQ30DQ31VSSCLK2/NCNCWPSDASCLVDD

VSSDQ32DQ33DQ34DQ35VDD

DQ36DQ37DQ38DQ39DQ40

VSSDQ41DQ42DQ43DQ44DQ45VDD

DQ46DQ47

CB4CB5VSS

CB13VDD

CAS#/DUDQM4DQM5CS1#

RAS#/DUVSS

A1A3A5A7A9

BA0/A11A11/A13

VDDCLK1/DU

A12/DUVSS

CKE0/DUCS3#

DQM6DQM7

A13/DUVDD

CB14CB15CB6CB7VSS

DQ48DQ49DQ50DQ51VDD

DQ52NC

VREF/DUREGE

VSSDQ53DQ54DQ55

VSSDQ56DQ57DQ58DQ59VDD

DQ60DQ61DQ62DQ63

VSSCLK3/NC

NCSA0SA1SA2VDD

CB12

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

DIMM 3

10 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

SM_MD[0..63]

SM_CSB#[4..5]

SM_MAA[0..12]

SM_CKE[4..5]

SM_CSA#[4..5]

SM_DQM[0..7]

SM_MAC#[4..7]

SM_CSA#4

SM_MD56

SM_MAA11

SM_MD49

SM_MD61

SM_MD38

SM_MD19

SM_MAA10SM_MAA9

SMBDATA

SM_MD12

SM_MD10

SM_MD34

SM_MD46

SM_MD35

SM_MD45

SM_MD18

SM_DQM5

SM_BS1

SM_DQM2

SM_MD39

SM_MD44

SM_MD55

SM_MD43

SM_MD53

SM_MD8

SM_MAA2

SM_MD6SM_MD5

SM_MD7

SM_MD15

SM_MD29

SM_CSB#4

SM_DQM7

SM_MAC#4

SM_MD4

SM_MAC#5

SM_MD13

SM_MD36

SM_CSB#5

SM_MD21

SM_MD11

SM_CKE4

SM_MD63

SM_DQM4

MEMCLK9

SM_MD16

SM_MD28

SM_MD27

SM_DQM3

SM_MAA0SM_MAA3

SM_MD40

MEMCLK8

SM_MAC#6

SM_DQM0

SM_MD60

SM_MD22

MEMCLK10

SM_MD20

SM_MAA1

SM_MD23

SM_MD0SM_MD1

SM_WE#

SM_BS0

SM_MD54

SM_MD59

SM_MD32

SM_MD58

SM_MD42

SM_MD31

SM_MAC#7

SM_MD62

SM_MD9

SM_MD51

SM_MD2

SM_CSA#5

SM_MD30

SM_MAA8

SM_MD41

SM_MD52

SM_DQM1

SM_MD26

SM_MD17

SM_MD47

MEMCLK11

SM_MD14

SM_MD48

SMBCLK

SM_CKE5

SM_MD25

SM_MD50

SM_MAA12

SM_MD57

SM_MD37

SM_MD3

SM_MD24

SM_DQM6

SM_MD33

SMBDATA

SM_RAS#

SM_CAS#

SM_BS1

SMBCLK

SM_WE#

SM_BS0

MEMCLK[8..11]

SM_CAS#

SM_RAS#

SM_BS07,9

SM_BS17,9

SM_CAS#7,9

SM_CSB#[4..5]7

SM_WE#7,9

SM_CSA#[4..5]7

SM_MD[0..63]7,9

SM_MAC#[4..7]7

SM_DQM[0..7]7,9

SM_RAS#7,9

SM_MAA[0..12]7,9

SMBCLK9,13,21,24,30,32SMBDATA9,13,21,24,30,32

DM_SA_PU9

MEMCLK[8..11]6

SM_CKE[4..5]7

VCC3SBY VCC3SBY

DIMM3

DIMM168

123456789

101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384

858687888990919293949596979899100101102103104105106107

109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168

108

VSSDQ0DQ1DQ2DQ3VDDDQ4DQ5DQ6DQ7DQ8VSSDQ9DQ10DQ11DQ12DQ13VDDDQ14DQ15CB0CB1VSSCB8CB9VDDWE#/WE0#DQM0DQM1CS0#DU/OE0#VSSA0A2A4A6A8A10/APBA1/A12VDDVDDCLK0/DUVSSDU/OE2#CS2#DQM2DQM3DU/WE2#VDDCB10CB11CB2CB3VSSDQ16DQ17DQ18DQ19VDDDQ20NCVREF/DUCKE1VSSDQ21DQ22DQ23VSSDQ24DQ25DQ26DQ27VDDDQ28DQ29DQ30DQ31VSSCLK2/NCNCWPSDASCLVDD

VSSDQ32DQ33DQ34DQ35VDD

DQ36DQ37DQ38DQ39DQ40

VSSDQ41DQ42DQ43DQ44DQ45VDD

DQ46DQ47

CB4CB5VSS

CB13VDD

CAS#/DUDQM4DQM5CS1#

RAS#/DUVSS

A1A3A5A7A9

BA0/A11A11/A13

VDDCLK1/DU

A12/DUVSS

CKE0/DUCS3#

DQM6DQM7

A13/DUVDD

CB14CB15CB6CB7VSS

DQ48DQ49DQ50DQ51VDD

DQ52NC

VREF/DUREGE

VSSDQ53DQ54DQ55

VSSDQ56DQ57DQ58DQ59VDD

DQ60DQ61DQ62DQ63

VSSCLK3/NC

NCSA0SA1SA2VDD

CB12

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CH6-18

Place closeto GMCH

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

AGP

11 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

GREQ# GGNT#

ST0 ST1ST2

PIPE#

WBF#SBA0 SBA1

SBA2 SBA3SBSTB SBSTB1#

SBA4 SBA5SBA6 SBA7

ADSTB1 ADSTB1#

GIRDY# GFRAME#

GDEVSEL# GTRDY#GSTOP#

GPERR#

GSERR# GPAR

ADSTB0 ADSTB0#

GFRAME#

GPERR#

PIPE#WBF#

ADSTB1ADSTB1#

ADSTB0

GAD[0..31]

GAD2

GAD25

GAD23

GAD19

GAD12

GAD5

GAD21

GAD18

GAD13

GAD9

GAD1

GAD22GAD20

GAD11

GAD4

GAD16

GAD7

GAD8

GAD27

GAD31GAD29

GAD0

SBA[0..7]

GAD6

GAD17

GAD3

GAD14

GAD15

GAD10

GAD30GAD28

GAD26GAD24

SBA0SBA1SBA2SBA3

ADSTB0#

GSERR#

GDEVSEL#

GPAR

GTRDY#GIRDY#

GSTOP#

ST0

GREQ#

ST1

GGNT#

ST2

SBA7SBA6

SBSTBSBSTB#

SBA4SBA5

RBF#

RBF#

CON_AGPREF

AGPUSBN 18

PIRQ#A 14,15,30

GGNT# 8

ST1 8

PIPE# 8

TYPEDET# 26

PCI_RST# 14,15,30

GFRAME# 8

GTRDY# 8GSTOP# 8PCI_PME# 12,14,15,22

GPAR 8

GCBE#0 8

ADSTB0# 8

ADSTB1# 8

WBF# 8

SBSTB# 8

GCBE#3 8

AGP_OC#18

AGPUSBP18

PIRQ#B14,15,30AGPCLK_CONN6

GREQ#8

ST08ST28

RBF#8

SBSTB8

ADSTB18

GCBE#28

GIRDY#8

GDEVSEL#8

GCBE#18

ADSTB08

GMCH_AGPREF8

GAD[0..31]8

SBA[0..7]8

CONN_AGPREF 8,32

VDDQ

V3SB

VCC3_3VCC5

VCC12

VDDQ

VCC12

VDDQ

R3358.2K

R3328.2KR3338.2KR3348.2K

PR20

301,1%

Q132N7002

AGP1

AGP4XU_20

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49B50B51B52B53B54B55B56B57B58B59B60B61B62B63B64B65B66

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32A33A34A35A36A37A38A39A40A41A42A43A44A45A46A47A48A49A50A51A52A53A54A55A56A57A58A59A60A61A62A63A64A65A66

OVRCNT#5V_A5V_BUSB+GND_KINTB#CLKREQ#/DQ27VCC3.3_FST0/DQ28ST2/DQ29RBF#/DQ30GND_LRESV_HSBA0/DQ31VCC3.3_GSBA2/DQM2SB_STBGND_MSBA4/DQ23SBA6/DQ22RESVGND_N3.3VAUX1VCC3.3_HAD31/DQ21AD29/DQ20VCC3.3_IAD27/DQ19AD25/DQ18GND_OAD_STB1AD23/DQ17VDDQ_FAD21/DQ16AD19/DQ15GND_PAD17/DQ14C/BE2#/DQ13VDDQ_GIRDY#/DQ123.3VAUX2GND_QRESV_KVCC3.3_JDEVSEL#/DQ11VDDQ_HPERR#GND_RSERR#C/BE1#/DQ10VDDQ_IAD14/DQ9AD12/DQ8GND_SAD10/DQM1AD8/DQ0VDDQ_JAD_STB0AD7/DQ1GND_TAD5/DQ2AD3/DQ3VDDQ_KAD1/DQ4VREF_CG

12VTYPEDET#

RESV_AUSB-

GND_AINTA#RST#GNT#

VCC3.3_ADQM3/ST1

RESV_BDQ24/PIPE#

GND_BWBF#

DQ25/SBA1VCC3.3_B

DQ26/SBA3SB_STB#

GND_CWE#/SBA5

M_FREQ_SEL/SBA7RESV_CGND_D

RESV_DVCC3.3_C

TCLK0/AD30TCLK1/AD28

VCC3.3_DCAS#/AD26

AD24GND_E

AD_STB1#RAS#/C/BE3#

VDDQ_AA0/AD22A9/AD20

GND_FA11/AD18A8/AD16VDDQ_B

A10/FRAME#RESV_EGND_G

RESV_FVCC3.3_EA7/TRDY#

CS#/STOP#PME#

GND_HA6/PAR

A1/AD15VDDQ_CA5/AD13A2/AD11

GND_IA4/AD9

A3/C/BE0#VDDQ_D

AD_STB0#DQ5/AD6

GND_JDQ6/AD4DQ7/AD2VDDQ_E

DQM0/AD0VREF_GC

PR19

200,1%

RN49

8.2K/8P4R

1357

2468

RN48

8.2K/8P4R

1357

2468

RN43

8.2K/8P4R

1357

2468

RN44

8.2K/8P4R

1357

2468

RN46

8.2K/8P4R

1357

2468

RN45

8.2K/8P4R

1357

2468

R106

2.2K

RN42

8.2K/8P4R

1357

2468

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NPOP

Place R as

Close as

possible to

ICH

Place as close as

Possible to ICH

and via straight

to VSS plane

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

ICH2 Part 1

12 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

AD[0..31]

HL[0..10]

HL10

HL4

HL9

HUBREF_ICH

HL2HL1

HL8

HL0

HL5

HL7

HL3

HL6

AD24AD23

AD20

AD17

AD9

AD22

AD10

AD12

AD26AD25

AD1

AD4

AD28

AD3AD2

AD27

AD19

AD8

AD31

AD11

AD30

AD15

AD0

AD13AD14

AD6

AD29

AD16

AD21

AD18

AD7

AD5

U12_RN69-1

U12_RN69-7

U12_RN69-3U12_RN69-5

AD[0..31]14,15

IGNNE# 4

A20M# 4

STPCLK# 4SMI# 4

KBRST# 21,30

CPUSLP# 4

NMI 4

INIT# 4,17INTR 4

FERR# 4

ICH_IRQ#D 30

ICH_IRQ#B 30ICH_IRQ#C 30

CPU_PWGD 4,33

HLSTB# 8

IRQ15 17IRQ14 17

SERIRQ 21,30

PREQ#5 30

PGNT#1 14

APICD1 4

PGNT#2 15

PREQ#0 14,30

HLSTB 8

PREQ#4 30

APICD0 4

PREQ#2 15,30PREQ#1 14,30

PREQ#3 30

APICCLK_ICH 6

PGNT#0 14

HL[0..10] 8

ICH_IRQ#A 30

PCLK_0/ICH6

PCI_PME#11,14,15,22

C_BE#014,15

ICH_IRQ#F30

C_BE#114,15

IRDY#14,15,30

PAR14,15

ICH_IRQ#H30

FRAME#14,15,30

GPIO2730

TRDY#14,15,30

PERR#14,15,30

DEVSEL#14,15,30

PLOCK#14,15,30ICHRST#30

ICH_IRQ#G30

C_BE#214,15

STOP#14,15,30

ICH_IRQ#E30

SERR#14,15,30

C_BE#314,15

PCI_REQ#A30

P66DET17

GPIO2317

LAN_RXD0 24LAN_RXD1 24LAN_RXD2 24

LAN_TXD0 24

LAN_CLK 24LAN_RSTSYNC 24

LPC_PME#21,30EXTSMI#24

GPI830S66DET17

LAN_TXD2 24

PRI_DWN#24,29

HUBREF_ICH 32

LAN_TXD1 24

A20GATE 21,30

VCC1_8

VCC1_8

V1_8SBV3SB V3SBVCC1_8 V3SBVCC3_3 V1_8SBVCC1_8

U12A82801BA ICH2

AA4AB4

Y4W5W4Y5

AB3AA5AB5

Y3W6W3Y6Y2

AA6Y1V2

AA8V1

AB8U4W9U3Y9U2

AB9U1

W10T4

Y10T3

AA10

AA3AB6

Y8AA9

W11V3

AB7W8V4W1

AA15AA7W2W7

Y15

M3L2

E14

E15

E16

E17

E18

F18

G18

H18

J18

P18

R18

R5

T5

U5

V5

D11A12R22A11C12C11B11B12C10B13C13

A4B5A5B6B7A8B8A9C8C6C7

A6A7A3B4

P1P2P3N4

F21C16N20N19P22N21

R2R3T1AB10

M2M1R4T2

D10

E5

K19

L19

P5

V9

D2

Y7

N3N2N1

AA11Y14W14

AB15A15D14C14

L1B14A14

AB14AA14

A13

C5

M4

P4L3

R1L4

A1

A10

A2

A21

A22

AA

1A

A2

AA

21A

A22

AB

1A

B2

AB

21A

B22

B1

B10

B2

B21

B22

B3

B9

C2

C3

C4

C9

D3

D5

D6

D7

D8

D9

E6

E7

E8

E9

J10

J11

J12

J13

J14

J9 K1

K10

K11

K12

K13

K14

K9

L10

L11

L12

L13

L14

L9 M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P9

P10

P11

P12

P13

P14

G2G1H1

F3F2F1

G3H2

V6

V7

V8

U18

T18

F5

G5

V17

V18

V14

V15

V16

H5

J5

Y11

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C_BE#0C_BE#1C_BE#2C_BE#3

PCICLKFRAME#DEVSEL#IRDY#TRDY#STOP#PCIRST#PLOCK#PARSERR#

PCI_PME#

REQ#A/GPI0GNT#A/GPO16

VC

C3_

3_2

VC

C3_

3_3

VC

C3_

3_4

VC

C3_

3_5

VC

C3_

3_6

VC

C3_

3_7

VC

C3_

3_8

VC

C3_

3_10

VC

C3_

3_11

VC

C3_

3_12

VC

C3_

3_13

VC

C3_

3_14

VC

C3_

3_15

VC

C3_

3_16

VC

C3_

3_17

A20M#CPUSLP#

FERR#IGNNE#

INIT#INTRNMI

SMI#STPCLK#

RCIN#A20GATE

HL0HL1HL2HL3HL4HL5HL6HL7HL8HL9

HL10

HLSTBHLSTB#HCOMP

HUBREF

PIRQ#APIRQ#BPIRQ#CPIRQ#D

IRQ14IRQ15

APICCLKAPICD1APICD0SERIRQ

REQ#0REQ#1REQ#2REQ#3

GNT#0GNT#1GNT#2GNT#3

VC

C1_

8_1

VC

C1_

8_2

VC

C1_

8_3

VC

C1_

8_4

VC

C1_

8_5

VC

C1_

8_6

VC

CA

PERR#

PIRQ#E/GPI2PIRQ#F/GPI3PIRQ#G/GPI4

GPI7GPI8GPI12GPI13GPO18GPO19GPO20GPO21GPOD22GPO23GPIOD27GPIOD28

CPUPWRGOD

HL11

PIRQ#H/GPI5

REQ#4REQ#B/GPI1/REQ#5

GNT#4GNT#B/GPO17/GNT#5

VS

S0

VS

S1

VS

S2

VS

S3

VS

S4

VS

S5

VS

S6

VS

S7

VS

S8

VS

S9

VS

S10

VS

S11

VS

S12

VS

S13

VS

S14

VS

S15

VS

S16

VS

S17

VS

S18

VS

S19

VS

S20

VS

S21

VS

S22

VS

S23

VS

S24

VS

S25

VS

S26

VS

S27

VS

S28

VS

S29

VS

S30

VS

S31

VS

S32

VS

S33

VS

S34

VS

S35

VS

S36

VS

S37

VS

S38

VS

S39

VS

S40

VS

S41

VS

S42

VS

S43

VS

S44

VS

S45

VS

S46

VS

S47

VS

S48

VS

S49

VS

S50

VS

S51

VS

S52

VS

S53

VS

S54

VS

S55

VS

S56

VS

S57

VS

S58

VS

S59

VS

S60

VS

S61

VS

S62

VS

S63

VS

S64

VS

S65

VS

S66

VS

S67

VS

S68

VS

S69

VS

S70

LAN_RXD0LAN_RXD1LAN_RXD2

LAN_TXD0LAN_TXD1LAN_TXD2

LAN_CLKLAN_RSTSYNC

VC

C3_

3_18

VC

C3_

3_19

VC

C3_

3_20

VC

CP

S1

VC

CP

S2

VC

CP

X1

VC

CP

X2

VC

CU

SB

1V

CC

US

B2

VC

CC

S1

VC

CC

S2

VC

CC

S3

VC

CA

X1

VC

CA

X2

GPI6

C101

10PF

PR25

301,1%

PR26

301,1%

PR27

40.2,1%

BC119

0.01UF

RN69 22/8P4R1357

2468

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Target 20ms afterVCC_CLOCK ispowered

Debug only - donot stuff

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

ICH2 Part 2

13 33

Thursday, November 29, 2001Thursday, November 29, 2001

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Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

PDA0

SDA0

PDD5PDD6

SDD1SDD0

SDD4

PDD1

PDD7

PDD11

SDD10

SDD14

PDD2

SDD7

PDA2

SDD12

SDD2

SDD5

PDD4

SDA2

PDD8

PDD12

PDA1

SDA1

PDD13

SDD3

SDD13

PDD14PDD15

SDD11

SDD15

PDD9PDD10

SDD8

SDD6

SDD9

PDD0

PDD3

SDD[0..15]

PDD[0..15]

RTCX1VBIAS

RTCX2RTCRST#

PDA[0..2]

SDA[0..2]

R174_JP1

ICH_PWROK SDCS#1 17

AC_RST#24,29

SDCS#3 17

PDIOR# 17

PDIOW# 17

AC_SDIN124,30

SDDACK# 17

SDIOW# 17

PDREQ 17

SDIOR# 17

PIORDY 17

PDCS#1 17

AC_SDIN019,24,30

AC_BITCLK19,24

PDCS#3 17

SIORDY 17

PDDACK# 17SDREQ 17

USBCLK6ICH_3V666

ICH_SPKR19,24,29

AC_SYNC19,24

SDD[0..15] 17

PDD[0..15] 17

ICH_RI#22,30

SLP_S3#6,21,28

PWRBTN#21,33

OVT#21,30

SLP_S5#28

RSMRST#21

LAD317,21LAD217,21

LDRQ#021

LFRAME#17,21

LAD117,21LAD017,21

SMBALERT#30

SMBDATA9,10,21,24,30,32SMBCLK9,10,21,24,30,32

SUSCLK21

USBP1P18USBP1N18

USBP0N18

USBP2P18

USBP3P18USBP3N18

USBP2N18

EE_CS24

EE_SHCLK24 SMLINK1 15,30SMLINK0 15,30

USBP0P18

USBOC#0-118

AC_SDOUT19,24,29

ICH_CLK146

PDA[0..2] 17

SDA[0..2] 17

USBOC#2-318

CASEOPEN#21,25

GPIO2530

EE_DOUT24EE_DIN24

PWROK21,25

VRM_PWRGD 27

VCC5

VCC3_3

VCC5

VCCRTC VCC5SBY

V3SB

V3SB

VCC3_3VCC_CLOCK

VCC3_3 VCMOS

VCC3_3

BC197

0.1UF

R325 1K

D19

BAT54C

12

3

12

3

R324 1K

D18

SS12/SMD

R403

1K

BC125

0.1UF

C91

1.0UF

CP2

47PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

RN70 15/8P4R1357

2468

R129 1K

CP1

47PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

RN71 15/8P4R1357

2468

C88

X18PF

C113

1.0UF

BAT1

BATTERY

C103

18PF

C104

1.0UF

R149 10M

C110

0.047UF

R181 1K

Y2

32.768KHZ

R162

10M

C102

18PF

R187

1K

R174 15KJP1

CCM0S

1

32

Q162N7002

U33

741G08 AND

1

2

3

4

5

A

B GN

D

YVcc

R141 10C96

X10PR134 1K

D8 SS12/SMD

D12

SS12/SMD

R164

560K

R271

560K

U12B

82801BA ICH2

AA13W16

AB18R20

W21AA17

R21Y17

AA16AB16AB17

T19

M19P20D4

T21U22T22T20

V22P19R19P21Y22W22N22

Y12W12

AB13AB12AB11

Y13W13

AB19AA19

W17Y18

Y20W19

E21C15E19D15

F20F19E22A16D16B16

G22B18F22B17G19D17G21C17G20A17

H19H22J19J22K21L20M21M22L22L21K22K20J21J20H21H20

D18B19D19A20C20C21D22E20D21C22D20B20C19A19C18A18

U21

M20

K2

V19

D13

D12

W15V21

Y16

W18Y19

AB20AA20

Y21W20

K4K3J4J3

U19V20B15U20

AA18

AA12

THRM#SLP_S3#SLP_S5#PWROK

PWRBTN#RI#RSMRST#SUS_STAT#

SMBDATASMBCLKSMBALTER#/GPI11INTRUDER#

CLK14CLK48CLK66

VBIASRTCX1RTCX2RTCRST#

AC_RST#AC_SYNCAC_BITCLKAC_SDOUTAC_SDIN0AC_SDIN1SPKR

LAD0/FWH0LAD1/FWH1LAD2/FWH2LAD3/FWH3LFRAME#/FWH4LDRQ#0LDRQ#1

USBP1PUSBP1N

USBP0PUSBP0N

OC#1OC#0

PDCS#1SDCS#1PDSC#3SDCS#3

PDA0PDA1PDA2SDA0SDA1SDA2

PDDREQSDDREQ

PDDACK#SDDACK#

PDIOR#SDIOR#PDIOW#SDIOW#PIORDYSIORDY

PDD0PDD1PDD2PDD3PDD4PDD5PDD6PDD7PDD8PDD9

PDD10PDD11PDD12PDD13PDD14PDD15

SDD0SDD1SDD2SDD3SDD4SDD5SDD6SDD7SDD8SDD9

SDD10SDD11SDD12SDD13SDD14SDD15

VC

CR

TC

V5R

1V

5R2

V5R

_SU

S

VC

PU

2V

CP

U1GPIO25

GPIO24

RSM_PWROK

USBP2PUSBP2NUSBP3PUSBP3N

OC#2OC#3

EE_CSEE_DINEE_DOUTEE_SHCLK

SMLINK0SMLINK1

VRMPWRGDTP0

SUSCLK

FS0

R376 43k

C172

1.0uF

R377 0

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

PCI 1 and 2

14 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

AD30

AD28AD26

AD24

AD22AD20

AD18AD16

AD15

AD13AD11

AD9

AD6AD4

AD2AD0

AD31AD29

AD27AD25

AD23

AD21AD19

AD17

PERR#

AD14

AD12AD10

AD8AD7

AD5AD3

AD1

ACK64#

PIRQ#BPIRQ#D

PCI_RST#

PCI_PME#AD30

AD28AD26

AD24R_AD17

AD22AD20

AD18AD16

FRAME#

TRDY#

STOP#

PARAD15

AD13AD11

AD9

C_BE#0

AD6AD4

AD2AD0

PIRQ#CPIRQ#A

AD31AD29

AD27AD25

C_BE#3AD23

AD21AD19

AD17C_BE#2

IRDY#

DEVSEL#

PLOCK#PERR#

SERR#

C_BE#1AD14

AD12AD10

AD8AD7

AD5AD3

AD1

ACK64#

AD17R_AD16 AD16

AD[0..31]

C_BE#[0..3]

C_BE#3

C_BE#2

C_BE#1

C_BE#0

PIRQ#B11,15,30PIRQ#D15,30

PCLK_16

PREQ#012,30

IRDY#12,15,30

DEVSEL#12,15,30

PLOCK#12,15,30

SERR#12,15,30

AD[0..31]12,15

C_BE#[0..3]12,15

PIRQ#A 11,15,30PIRQ#C 15,30

PGNT#0 12

PCI_PME# 11,12,15,22

FRAME# 12,15,30

TRDY# 12,15,30

STOP# 12,15,30

PAR 12,15

ACK64#15,30

PGNT#1 12PREQ#112,30

PCLK_26PCI_RST# 11,15,30

PERR#12,15,30

REQ64#1 30 REQ64#2 30

VCC3_3

VCC5

VCC12VCC12-

VCC5

VCC3_3VCC3_3

VCC5

VCC12VCC12-

VCC5

VCC3_3

V3SBV3SB

R133100

R142100

PCI1

PCI_CON_32BIT

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32A33A34A35A36A37A38A39A40A41A42A43A44A45A46A47A48A49

A52A53A54A55A56A57A58A59A60A61A62

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49

B52B53B54B55B56B57B58B59B60B61B62

TRST#+12VTMSTDI+5V

INTA#INTC#

+5VRESERVED

+5V(I/O)RESERVED

GNDGND

RESERVEDRST#

+5V(I/O)GNTGND

PME#AD30+3.3VAD28AD26GNDAD24

IDSEL+3.3

AD22AD20GNDAD18AD16+3.3V

FRAME#GND

TRDY#GND

STOP#+3.3V

SDONESBO#GNDPAR

AD15+3.3VAD13AD11GNDAD9

C/BE#0+3.3V

AD6AD4

GNDAD2AD0

+5V(I/O)REQ64#

+5V+5V

-12VTCKGNDTDO+5V+5VINTB#INTD#PRSNT#1RESERVEDPRSNT#2GNDGNDRESERVEDGNDCLKGNDREQ#+5V(I/O)AD31AD29GNDAD27AD25+3.3VC/BE#3AD23GNDAD21AD19+3.3VAD17C/BE#2GNDIRDY#+3.3VDEVSEL#GNDLOCK#PERR#+3.3VSERR#+3.3VC/BE#1AD14GNDAD12AD10GND

AD8AD7+3.3VAD5AD3GNDAD1+5V(I/O)ACK64#+5V+5V

PCI2

PCI_CON_32BIT

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32A33A34A35A36A37A38A39A40A41A42A43A44A45A46A47A48A49

A52A53A54A55A56A57A58A59A60A61A62

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49

B52B53B54B55B56B57B58B59B60B61B62

TRST#+12VTMSTDI+5V

INTA#INTC#

+5VRESERVED

+5V(I/O)RESERVED

GNDGND

RESERVEDRST#

+5V(I/O)GNTGND

PME#AD30+3.3VAD28AD26GNDAD24

IDSEL+3.3

AD22AD20GNDAD18AD16+3.3V

FRAME#GND

TRDY#GND

STOP#+3.3V

SDONESBO#GNDPAR

AD15+3.3VAD13AD11GNDAD9

C/BE#0+3.3V

AD6AD4

GNDAD2AD0

+5V(I/O)REQ64#

+5V+5V

-12VTCKGNDTDO+5V+5VINTB#INTD#PRSNT#1RESERVEDPRSNT#2GNDGNDRESERVEDGNDCLKGNDREQ#+5V(I/O)AD31AD29GNDAD27AD25+3.3VC/BE#3AD23GNDAD21AD19+3.3VAD17C/BE#2GNDIRDY#+3.3VDEVSEL#GNDLOCK#PERR#+3.3VSERR#+3.3VC/BE#1AD14GNDAD12AD10GND

AD8AD7+3.3VAD5AD3GNDAD1+5V(I/O)ACK64#+5V+5V

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

PCI 3

15 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

AD22AD20

AD18AD16

AD15

AD9

AD6AD4

AD2AD0

AD31AD29

AD27AD25

AD23

AD21AD19

AD17

PERR#

AD14

AD12AD10

AD8AD7

AD5AD3

AD1

ACK64#

C_BE#3

C_BE#2

C_BE#1

AD18

C_BE#0

AD30

R_AD18AD24

AD11AD13

AD28AD26

AD[0..31]

C_BE#[0..3]

PIRQ#B11,14,30

PCLK_36

IRDY#12,14,30

DEVSEL#12,14,30

SERR#12,14,30

AD[0..31]12,14

C_BE#[0..3]12,14

PIRQ#C 14,30PIRQ#A 11,14,30

PGNT#2 12

PCI_PME# 11,12,14,22

FRAME# 12,14,30

TRDY# 12,14,30

STOP# 12,14,30

PAR 12,14

ACK64#14,30

PCI_RST# 11,14,30

PREQ#212,30

PIRQ#D14,30

PERR#12,14,30PLOCK#12,14,30

REQ64#3 30

SMLINK1 13,30SMLINK0 13,30

VCC3_3

VCC5

VCC12VCC12-

VCC5

VCC3_3V3SB

R148100

PCI3

PCI_CON_32BIT

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32A33A34A35A36A37A38A39A40A41A42A43A44A45A46A47A48A49

A52A53A54A55A56A57A58A59A60A61A62

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49

B52B53B54B55B56B57B58B59B60B61B62

TRST#+12VTMSTDI+5V

INTA#INTC#

+5VRESERVED

+5V(I/O)RESERVED

GNDGND

RESERVEDRST#

+5V(I/O)GNTGND

PME#AD30+3.3VAD28AD26GNDAD24

IDSEL+3.3

AD22AD20GNDAD18AD16+3.3V

FRAME#GND

TRDY#GND

STOP#+3.3V

SDONESBO#GNDPAR

AD15+3.3VAD13AD11GNDAD9

C/BE#0+3.3V

AD6AD4

GNDAD2AD0

+5V(I/O)REQ64#

+5V+5V

-12VTCKGNDTDO+5V+5VINTB#INTD#PRSNT#1RESERVEDPRSNT#2GNDGNDRESERVEDGNDCLKGNDREQ#+5V(I/O)AD31AD29GNDAD27AD25+3.3VC/BE#3AD23GNDAD21AD19+3.3VAD17C/BE#2GNDIRDY#+3.3VDEVSEL#GNDLOCK#PERR#+3.3VSERR#+3.3VC/BE#1AD14GNDAD12AD10GND

AD8AD7+3.3VAD5AD3GNDAD1+5V(I/O)ACK64#+5V+5V

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Place 100pF capnear DVO pin 40

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VGA Header and DVO Debug Header

16 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

DDCCL

DDCDA

HS

VS

BV

GV

RVMONOPU

MON2PU

F5_FB11

FTD[0..11]

5VHSYNC5VVSYNC

5VDDCDA

5VFTSDA

5VDDCCL

U8_VCC

5VFTSCL

FTD5

FTD3

FTD11

FTD1

FTD8

FTD6

FTD4

FTD7

FTD2

FTD9FTD10

FTD0

FTVREF

3VDDCDA8

SL_STALL 8

3VDDCCL8

CRT_VSYNC8

FTVSYNC 8

3VFTSCL8

FTCLK1 8

CRT_HSYNC8

FTHSYNC 8

FTCLK0 8

VID_RED8

VID_GREEN8

VID_BLUE8

FTD[0..11]8

PCIRST#7,17,21,30

FTBLNK# 8

3VFTSDA8 VCC3SBY VCC1_8

VCC5

VCC5 VCC1_8

VCC5

VCC5

VCC1_8

VCC5 VCC3_3 VCC1_8

C138

1.0uF

C139

1.0uF

C140

1.0uF

C143

1.0uF

C141

2.2uF

C142

1.0uF

C144

2.2uF

R329 2.2KR328 2.2K

C135

100PF

U8QST3384

3478

111417182122

242569101516192023

121

13

1A11A21A31A41A52A12A22A32A42A5

VCC1B11B21B31B41B52B12B22B32B42B5

GNDBEA#BEB#

D11

G1

D10

G2

D9

G3

D8

G4

D7

D6

G5

ST

#

ST

BG

6

D5

G7

D4

G8

D3

D2

G9

D1

G10

D0

G11

D/B

G12

Y C

CV

BS

SP

0

SP

1

SP

2

SP

3

5V1

5V2

3V1

3V2

3V3

3V4

VD

D1

VD

D2

VD

D3

VD

D4

VR

EF

PD

#

RS

T#

SD

A5

SC

L5

SD

A

SC

L

I/C HS

VS J3

DVO CONNECTOR

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

R85 33

C55

22PF

U28

PAC-VGA201/QSOP

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16VCC3

VCC1

VIDEO_1

VIDEO_2

VIDEO_3

GND

POWER_UP

VCC2 DDC_OUT1

DDC_OUT2

SYNC_IN1

SYNC_OUT1

SYNC_IN2

SYNC_OUT2

SD1

SD2

PR12

75,1%

C50

3.3PF

C49

X10PF

BC68

0.22UF

C47

3.3PF

C43

3.3PF

PR11

75,1%

PR10

75,1%

C53

10PF

C54

10PF

R87 33

C57

22PF

C56

10PF

C48

10PF

R84

1K

R322 10

R321 10

BC223

0.22UF

C134

100PF

VFB1

BEAD

1 2

FB11

BEAD

12

VGA1

VGA_CONN

61

1172

1283

1394

14105

15

R73

1K

F5

FUSE_1.0A

R3501k

R97

4.7K

R96

4.7K

VFB2

BEAD

1 2

R3511k

VFB3

BEAD

1 2

C46

X10PF

R326 22

C45

X10PF

R327 22

BC225

0.22UF

BC224

0.22UF

RN41 2.2K/8P4R

1357

2468

D4

1N4148

BC86

0.1UF

R95

4.7K

C136

0.01uF

C137

100pF

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IDEFWH

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

FWH and UDMA100 IDE

17 33

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Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

IDERST_IDE1_PIN1PDD8

PDD6 PDD9PDD5 PDD10PDD4 PDD11PDD3 PDD12PDD2 PDD13PDD1 PDD14PDD0 PDD15

PDA1PDA0

IDERST_IDE2_PIN1

SDD6SDD5SDD4SDD3SDD2SDD1SDD0

SDA1SDA0

SDA2

IDERST#

FPGI4

SDD11

SDD13

SDD9SDD10

SDD8

SDD15SDD14

SDD12

IDERST#SDD7

SDD[0..15]

SDA[0..2]

PDD7

PDA2

PDD[0..15]

PDA[0..2]

PDREQ13

PDIOR#13PDIOW#13

PIORDY13PDDACK#13

IRQ1412

PDCS#3 13

SDD[0..15]13

SDCS#113

SDA[0..2]13

SDIOW#13

SIORDY13SDDACK#13

IRQ1512

SDCS#3 13

SDIOR#13

IDEACTS#24

IDEACTP#24PDCS#113

SDREQ13

PCIRST#7,16,21,30

INIT# 4,12

LAD3 13,21

PCLK_8 6

GPIO2312

LAD013,21LAD113,21LAD213,21

LFRAME# 13,21

IDERST#30

PDD[0..15]13

PDA[0..2]13

S66DET 12

P66DET 12

VCC3_3

VCC3_3

VCC3_3

VCC3_3VCC3_3

VCC3_3

R79

4.7K

R112 33

R76

4.7K

R75 8.2K

R113 33

R83 8.2K

IDE2

PIN_2X20

13579

11131517192123252729

24681012141618202224262830

3133353739

3234363840

BC175

0.1UF

BC177

0.1UF

BC178

0.1UF

BC173

0.1UF

R211 8.2K

C51

47PF

C44

47PF

R207

0

R80

10K

IDE1

PIN_2X20

13579

11131517192123252729

24681012141618202224262830

3133353739

3234363840

R70

10K

U23

FWH32

123456789

10111213141516 17

181920212223242526272829303132VPP

RST#FGPI3FGPI2FGPI1FGPI0WP#TBL#ID3ID2ID1ID0FWH0FWH1FWH2GND FWH3

RFURFURFURFURFU

FWH4INIT#VCCGND

VCCAGNDA

ICFGPI4

CLKVCC

R206 8.2K

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JP4 Pin 3 near USB2 Pin 5

JP4 Pin 4 near USB2 Pin 7

JP5 Pin 3 near USB2 Pin 6

JP5 Pin 4 near USB2 Pin 8

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

USB

18 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

USBP0P13USBP1N13USBP1P13

USBP0N13

USBOC#0-113

AGPUSBN11AGPUSBP11

USBP3N13USBP2P13

CNRUSBN24

USBOC#2-313

USBP3P13

CNRUSBP24

AGP_OC#11

CNR_OC#24

USBP2N13

VCC5DUAL

VCC5DUAL

V3SB

JP4

HEADER5

1

32

45

JP5

HEADER5

1

32

45

USB2

HEADER5X2

1 23 45 67 89 10

FB28 BEAD

1 2

BC4

470PF

+ EC18

100UF

RN7215K/8P4R

1 3 5 7

2 4 6 8

FB24 BEAD

1 2 FB23 BEAD

1 2 FB22 BEAD

1 2

CP3

47PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

F4 FUSE_1.0A

FB21 BEAD

1 2

FB8 BEAD

1 2

CP4

47PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

FB26 BEAD

1 2

FB27 BEAD

1 2

USB1

USB_CON2

12345678

VCC0DATA0-DATA0+GND0VCC1DATA1-DATA1+GND1

R268 X0

FB29 BEAD

1 2

RN7315K/8P4R

1 3 5 7

2 4 6 8

+ EC39

100UF

R269 X0 F7 FUSE_1.0A

FB25 BEAD

1 2

R266330K

C122

470PF

R267330K

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AC’97CODEC

"SINGLE POINT CONNECTION"

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

AC’97 Codec

19 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

CX

3D

MONO_OUT

VR

EF

RX

3D

FIL

T_R

FIL

T_L

AF

ILT

2

AF

ILT

1

XT

AL_

OU

T

XTAL_IN

R154_MC58

VR

EF

OU

T

PC_BEEPR336_MC56

AC97SPKR24 EAPD 20

AUD_VREFOUT 20

AC_SYNC 13,24AC_BITCLK 13,24

AC_SDIN0 13,24,30

PRI_DWN_RST# 29AC_SDOUT 13,24,29

LINE_IN_L20

LNLVL_OUT_R20

CD_R20

CD_REF20

MIC_IN20

LINE_IN_R20

CD_L20

LNLVL_OUT_L20

AUX_R20AUX_L20

ICH_SPKR13,24,29

VCC3_3 VCC5 VCC5_AUDIO

MC53

1UF

C97

22PF

C98

22PF

BC129

0.1UF

BC139

0.1UF

BC140

0.1UF

C99

X10PF

MC48

2.2UF

MC46

4.7UF

C95

2700PF

C94

2700PF

MC54

1UF

MC51

0.1uF NPOP

MC52

1UF

MC55

0.1UF

MC56 1UF

MC58 1UF

U15

CS4299

4 1 7 9 38 42 25 26 40 44 43

122423212220181917161415133736354139

29 30 32 31 33 34 27 28 3 2

1158106

46454847

DV

SS

1

DV

DD

1

DV

SS

2

DV

DD

2

AV

DD

2

AV

SS

2

AV

DD

1

AV

SS

1

NC

40N

C44

NC

43

PC_BEEPLINE_IN_RLINE_IN_LMIC1MIC2CD_RCD_LCD_REFVIDEO_RVIDEO_LAUX_LAUX_RPHONEMONO_OUTLINE_OUT_RLINE_OUT_LLNLVL_OUT_RLNLVL_OUT_L

AF

ILT

1

AF

ILT

2

FIL

T_L

FIL

T_R

RX

3D

CX

3D

VR

EF

VR

EF

OU

T

XT

L_O

UT

XT

L_IN

RESET#SDATA_OUT

SDATA_INSYNC

BIT_CLK

CS1CS0

CHAIN_CLKEAPD

BC136

0.1UF

R337220K

R154 100

PFB6

BEAD

12

R254

1K

R252

1K

R253 X0

Y1

24.576MHZ

R336 1K

R155220K

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CD Analog InputLine_In Analog Input

Microphone Input

Stereo HP/Spkr out

"SINGLE POINT CONNECTION"

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Audio I/O

20 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

R119_FB15

R120_MC41 JK3_MICIN

CD_ING

JK2_LINE_IN_R

JK2_LINE_IN_L

AUX_INL

AUX_INR

R122_FB17MC44_R122

R121_FB16MC42_R121

CD_INR CDIN_R

CD_INLCDIN_L

C87_C77

U11_BYPASSU11_OUTB

U11_OUTA

SPKROUT_R

U11_INB

MC47_R132

SPKROUT_L

CDIN_REF

C74_JK1

MC45_R127 U11_INALNLVL_OUT_R19

AUD_VREFOUT19

LINE_IN_R19

LINE_IN_L19

CD_R 19

CD_L 19

CD_REF 19

MIC_IN19

AUX_L 19

AUX_R 19

LNLVL_OUT_L19

EAPD19

VCC5_AUDIO

C90100PF

R12820K

BC123

0.1UF

R126 20K

C87 100PF

R127

20K

+

C78

100UF

R119

2.2K

R120

1K

C80

100PF

C75

100PF

MC42

1UF

R125220K

R124220K

R115

1K

R117

1K

R116

1K

AUX1

2.54_WAFER_4

1

32

4

C850.01UF

CD2

2.54_WAFER_4

1

32

4

CD1

2mm_WAFER_4

1

32

4

JK2

PHONEJACK

JK3

PHONEJACK

JK1

PHONEJACK

R1221K

R1211K

C86

100PF

MC41

1UFC76

100PF

MC43

1UFMC39

1UF

MC37

1UF

MC38

1UF

C81

100PF

C79

100PF

C83

100PF

C84

100PF

MC36

1UF

MC44

1UF

MC45

1UF

U11

LM4880

1234

8765

OUTAINABYPASSGND

VDDOUTB

INBSHUTDN

+

C77

100UF

R104

22

R105

22

C74

100PF

R132

20K

MC47

1UF

FB13

BEAD

1 2

FB14

BEAD

1 2

FB17

BEAD

1 2

FB16

BEAD

1 2

FB15

BEAD

1 2

R118220K

C82

100PF

MC401UF

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

W83627HF

FDD Signals Trace 8 or 10 mil

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Super I/O and FDC

21 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

WD#

DIR#

DS1#

WE#

MOA#

HEAD#

STEP#

DSB#DSA#MOB#

RWC#

IOAVCC

SUSLED 24KDAT 23KCLK 23

KEYLOCK# 24RI#0 22DCD#0 22

RXD0 22DTR#0 22RTS#0 22DSR#0 22CTS#0 22

STB# 22AFD# 22ERR# 22

SLIN# 22

ACK# 22BUSY 22PE 22

VTIN24,25VTIN125

FANIO325FANIO225FANIO125

FANPWM225FANPWM125

BEEP24

MCLK 23MDAT 23

PS_ON 25

IRRX 23IRTX 23RI#1 22DCD#1 22

RXD1 22DTR#1 22RTS#1 22DSR#1 22CTS#1 22

CASEOPEN# 13,25

SUSCLK 13

TXD1 22

KBRST# 12,30

PAR_INIT# 22

MIDI_IN23

J1BUTTON223J2BUTTON223

J2BUTTON123J1BUTTON123

JOY1Y23JOY2Y23

MIDI_OUT23

JOY2X23JOY1X23

SMBDATA9,10,13,24,30,32

SLP_S3# 6,13,28

A20GATE 12,30

PWROK 13,25

SLCT 22

PCIRST# 7,16,17,30

HM_VREF25VTIN325

THRMDN4,25

SMBCLK9,10,13,24,30,32

OVT#13,30

PWRBTN# 13,33

TXD0 22

RSMRST# 13

PDR0 22PDR1 22PDR2 22PDR3 22PDR4 22PDR5 22PDR6 22PDR7 22

LAD213,17LAD313,17

LAD113,17LAD013,17

SIO_CLK246LPC_PME#12,30PCLK_76

LDRQ#013

VID027,29,32VID127,29,32VID227,29,32

-5VIN25-12VIN25+12VIN25+3.3VIN25

VCORE25

LFRAME#13,17

VID327,29,32

SERIRQ12,30

PANSWIN 24,32

VTT_SENSE25

VCC5

VCC5

VCC5SBY

VCC3_3

VCC5

VCC5

VCCRTC

VCC5SBY

V3SB

R1660

R185300R193300

R15710K

BC155.1U

BC162.1U

BC154

0.1UF

BC161

0.1UF

BC1720.1UF

FB19

BEAD

1 2

FDC1

HEADER_17X2

13579

11131517192123252729

24681012141618202224262830

3133

3234

BC1510.1UF

FB20

BEAD

1 2

R16710K

U17

W83627HF

1 2 3 4 5 6 7 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

3940414243444546474849505152535455565758596061626364

6566676869707172737475767778798081828384858687888990919293949596979899100

101

102

103104105106107108109110111112113114115116117118119120121122123124125126127128

8 15

DR

VD

EN

0D

RV

DE

N1

IND

EX

#M

OA

#D

SB

#D

SA

#M

OB

#

ST

EP

#W

D#

WE

#V

CC

TR

AK

0#W

P#

HE

AD

#D

SK

CH

G#

CLK

INP

ME

#V

SS

PC

ICLK

LDR

Q#

SE

RIR

QLA

D3

LAD

2LA

D1

LAD

0V

CC

3VLF

RA

ME

#LR

ES

ET

#S

LCT

PE

BU

SY

AC

K#

PD

7P

D6

PD

5P

D4

PD3PD2PD1PD0

SLIN#INIT#ERR#AFD#STB#VCC

CTSA#DSRA#RTSA#DTRA#

SINASOUTA

VSSDCDA#

RIA#KBLOCK#

GA20MKBRST

VSBKCLKKDAT

SUSLED/GP35

MC

LKM

DA

TP

SO

UT

#P

SIN

#C

IRR

X/G

P34

RS

MR

ST

#/G

P33

PW

RO

K/G

P32

PW

RC

TL#

/GP

31S

US

CIN

/GP

30V

BA

TS

US

CLK

INC

AS

EO

PE

N#

VC

CC

TS

B#

DS

RB

#R

TS

B#

DT

RB

#S

INB

SO

UT

BD

CD

B#

RIB

#V

SS

IRT

X/G

P26

IRR

X/G

P25

WD

TO

/GP

24P

LED

/GP

23S

DA

/GP

22S

CL/

GP

21A

GN

D-5

VIN

-12V

IN+

12V

INA

VC

C+

3.3V

INV

CO

RE

BV

CO

RE

AV

RE

FV

TIN

3

VTIN2VTIN1OVT#VID4VID3VID2VID1VID0FANIO3FANIO2FANIO1VCCFANPWM2FANPWM1VSSBEEPMSI/GP20MSO/IRQIN0GPSA2/GP17GPSB2/GP16GPY1/GP15GPY2/P16/GP14GPX2/P15/GP13GPX1/P14/GP12GPSB1/P13/GP11GPSA1/P12/GP10

DIR

#

RD

AT

A#

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Parallel Port

WAKE ON MODEM

COM1

COM2

WAKE ON LAN

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Serial, Parallel, WOL, and WOR

22 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

RI0

RI1

DCD0DTR0CTS0TXDD0RTS0RXDD0DSR0RI0

DCD1DTR1CTS1TXDD1RTS1RXDD1DSR1RI1

DSR0RXDD0

RXDD1

TXDD1DCD1

RTS1

DTR1

DTR0

TXDD0RTS0

CTS0

DCD0

RI1

RI0

CTS1DSR1

DCD#021DTR#021CTS#021

TXD021RTS#021

DSR#021RI#021

DCD#121DTR#121CTS#121

TXD121RTS#121

DSR#121RI#121

RXD021

RXD121

PDR721

PDR121

STB#21

PDR021

PDR321

PDR421

PDR521

PAR_INIT#21

SLIN#21

ACK#21

BUSY21

PE21

SLCT21

ERR#21

PDR221

PDR621

AFD#21

PCI_PME#11,12,14,15

ICH_RI#13,30

VCC5

VCC12- VCC12 VCC5

VCC5SBY

U5

PAC-S1284

1

2

3 26

4

5

6

7

8

9

10

11

12

13

14

28

27

15

25

24

23

22

21

20

19

18

17

16

P1

P2

SI1 SO1

SI2

SI3

SI4

SI5

P3

SI6

P4

SI7

P5

SI8

SI9

P8

P7

P6

SO2

SO3

SO4

GND

SO5

VCC

SO6

SO7

SO8

SO9

R107

10K

R109

10K

U10

GD75232

2345678

1

19181716151413

9

1011

12

20

RA1RA2RA3DY1DY2RA4DY3

12V

RY1RY2RY3DA1DA2RY4DA3

RA5

-12VGND

RY5

5V

CN2

100PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6CN3

100PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

CN9

100PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6CN11

100PF/8P4C

1 3 5 782 4 6

1 3 5 782 4 6

COM2

HEADER_5X2

13579

2468

10

COM1

CONNECTOR_DB9

594837261

BC99.1U

BC54.1U

U9

GD75232

2345678

1

19181716151413

9

1011

12

20

RA1RA2RA3DY1DY2RA4DY3

12V

RY1RY2RY3DA1DA2RY4DA3

RA5

-12VGND

RY5

5V

R1102.2K

BC49.1U

R1082.2K

R2294.7K

R230

100

LPT1

LPT

13251224112310229

218

207

196

185

174

163

152

141

D2

SS12/SMD

D6

SS12/SMD

D7

SS12/SMD

Q142N3904

Q152N3904

Q21

2N3904

WOL1

HEADER_3*1(2MM)

1

32

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Game Port

KeyboardMouse

IR

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

PS/2, Game, and IR

23 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

MIDI_OUTPUT

JOY_1YJ2BUT2

JOY_2Y

CN1_U1

MIDI_INPUTJ1BUT2

JOY_2XJOY_1XJ2BUT1J1BUT1

JOY2X21

J2BUTTON221

MIDI_OUT21

J1BUTTON121

J1BUTTON221

JOY1X21

JOY1Y21JOY2Y21

J2BUTTON121

MIDI_IN21

KDAT21

KCLK21

MDAT21

MCLK21

IRRX21

IRTX21

VCC5VCC5 VCC5VCC5 VCC5VCC5 VCC5

VCC5

VCC5DUAL

R934.7K

R92

4.7K

R99

4.7K

C6822PF

C73

470PFC641000PF

F6 XFUSE_1.0A

C62

470PF

R98 47

C59

470PFC6322PF

C711000PF

R103 0

C671000PF

R1024.7K

C6522PF

C6622PF

C601000PF

CN10

470PF/8P4C

13578 246

13578 246

R944.7K

C70

470PFJ1

GAME_PORT

8157

146

135

124

113

10291

CN8

470PF/8P4C

13578 246

13578 246

R1014.7K

FB12

BEAD

12

R91 47

R18 0

R17 0

CN1

470PF8P4C

13578

246

13578

246

IR1

HEADER_1X5

1

32

45

FB1

BEAD

1 2

FB3

BEAD

1 2

FB5

BEAD

1 2

FB2

BEAD

1 2

FB4

BEAD

1 2

FB6

BEAD

1 2

F1 XFUSE_1.0A

F2 XFUSE_1.0AU1

KB/MOUSE

123456

131415

1617

789101112

C1

2.2UF

C2

2.2UF

RN4 4.7K/8P4R

1357

2468

RN40 1K/8P4R

1357

2468

RN39 1K/8P4R

1357

2468

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDD LED

PWR_SW

KEYLOCK

SMI_SW

SPEAKER

RESET

GREEN LED

RESERVE

PC_BEEP SELECTION

3-4 ON1-2 ON

CONTROLLED by AC97 CODEC

JP2TRADITIONAL

Reset

Switch

Power

Switch

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Front Panel Headers and CNR

24 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

R237_2

R243_PN1

R240_PN1

R238_PN1

R237_PN2

R242_PN1

SMBDATA

D15_PN1

SMBCLK

IDEACTS#17

BEEP21

KEYLOCK#21

PANSWIN21,32

IDEACTP#17

HWRST#25,32

SUSLED21

EXTSMI#12

ICH_SPKR13,19,29

AC97SPKR19

AC_SDIN1 13,30AC_SDIN0 13,19,30

AC_RST# 13,29

CNR_OC#18

AC_SDOUT13,19,29AC_SYNC13,19

AC_BITCLK13,19

PRI_DWN#12,29SMBCLK9,10,13,21,30,32 SMBDATA 9,10,13,21,30,32

CNRUSBN 18

CNRUSBP 18

EE_CS 13

LAN_TXD0 12LAN_TXD2 12

LAN_CLK 12LAN_RXD1 12

LAN_RXD012

LAN_TXD112LAN_RSTSYNC12

LAN_RXD212

EE_SHCLK13EE_DOUT 13EE_DIN13

VCC5

VCC5SBY VCC5

VCC5

V3SB

VCC5

VCC12VCC5SBYVCC12- VCC5V3SB

VCC5SBY

VCC3_3

VCC5SBY

VCC5VCC5

VCC5

BC1840.1UF

R236

33

SP1

BUZZER

R24410K

R238220

R2400

BC185

0.1UF

R243150

R242220

PN1

HEADER_14

1234567891011121314

R23310K

PN2

HEADER_14

1234567891011121314

R234150

R23510K

R232 68

R231 68

R237

0

C119

0.1UF

R24720K

JP2

XHEADER 2X2

1 23 4

R25510K

R22310K

R256 0

R226 2.2K

R27215K

C125

47PF

R27315K

C126

47PF

SMB2

SMBCON

1

32

45

R239 330

SMB1

SMBCON

1

32

45

R24110K

CNRSLOT1

CNR

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19

B20B21B22B23B24B25B26B27B28B29B30

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19

A20A21A22A23A24A25A26A27A28A29A30

RESERVEDRESERVEDRESERVEDGNDRESERVEDRESERVEDGNDLAN_TXD1LAN_RSTSYNCGNDLAN_RXD2LAN_RXD0GNDRESERVED+5VDUALUSB_OC#GND-12V+3.3VD

GNDEE_DOUTEE_SHCLKGNDSMB_A0SMB_SCLPRIMARY_DN#GNDAC97_SYNCAC97_SD_OUTAC97_BITCLK

RESERVEDRESERVED

GNDRESERVEDRESERVED

GNDLAN_TXD2LAN_TXD0

GNDLAN_CLK

LAN_RXD1RESERVED

USB+GNDUSB-+12VGND

+3.3VDUAL+5VD

GNDEE_DINEE_CS

SMB_A1SMB_A2

SMB_SDAAC97_RESET#

RESERVEDAC97_SD_IN1AC97_SD_IN0

GND

R2462.2K

D15 1N4148

D14 1N4148

D16

LED

Q192N3904

Q202N3904

Q222N3904

SW2

SW_4

1 2

3 4

1 2

3 4

SW3

SW_4

1 2

3 4

1 2

3 4

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CPU FAN

CHASSIS FAN

PWR FAN

Temperature Sensing

If case is opened,this switch should be closed.

Voltage Sensing

"power use"

"system use"

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

ATX Power and HW Monitor

25 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

+12CHFAN

+12CPUFAN

ATXPWROK

FANIO1 21FANPWM121

FANIO2 21

FANIO3 21

HM_VREF21

THRMDN4,21

VTIN121

VTIN24,21

+3.3VIN 21

-5VIN 21

+12VIN 21

VCORE 21

-12VIN 21

VTIN321

PWROK 13,21

CASEOPEN#13,21

HWRST#24,32

PS_ON21

DBRESET#4

FANPWM221

VTT_SENSE 21

VCC12-

VCC_5-

VCC5 VCC5SBYVCC12

VCC12

VCCVID

VCC12-

VCC_5-

VTT

VCC12

VCC3_3

VCC12

VCC12

VCC5

VCC5

VCC5

VCCRTC

VCC3_3 VCC5VCC5SBY V3SB

VCC5SBY

VCC5SBY

VCC5SBY

V3SB VCC5SBY

V3SBV3SBU19E

74LVC06A

11 10

R189

4.7K

ATXPR1

ATX_PWCON

2345678910

11121314151617181920

1

3.3VGND+5V

GND+5V

GNDPWROKAUX5V

+12V

3.3V-12VGNDPS_ONGNDGNDGND-5V+5V+5V

3.3V

R218

4.7K

R217 1K

R216 510

+EC38

22UF

FAN3

HEADER_3

1

32

R11

4.7K

R10 1K

R16 510

FAN1

HEADER_3

1

32

Q17

2N7002

Q1

2N7002+EC3

22UF

R210

30K

FAN2

HEADER_3

1

32

R100

1K

+EC35

22UF

C118

3300PF

PR37

28K,1%

PR32

120K,1%

PR34

232K,1%

R214

10KPR35

56K,1%

R208

10K

R209

10K

PR33

56K,1%

S1

HEADER_2PIN

R245 100

R213 10M

R19

1K

R212

1K

PR39

10K,1%

PR36

10K,1%

tRT1

10K_1%-THRM/0603

U20F

74LVC14A

1213

U19F

74LVC06A

13 12

R19015K

U19A

74LVC06A

1 2

714

BC164.1U

U20C

74LVC14A

65

C115

2.2UF

R19233K

tRT2

X10K_1%-THRM/0603

JP3

HEADER_21 2

U20D

74LVC14A

89

PR38

10K,1%

D13

1N4148

D1

1N4148

D5

1N4148

D101N4148

Q182N2907

Q22N2907

U19B

74LVC06A

3 4

U20A

74LVC14A7

1421

R3231K

BC165.1U

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Target isreally 1.85V

2.0ms delaynominal

ASSERTED LOW!

Empty for ADM1051AJR

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VRegs: Vddq, Vcc1_8, and Vtt

26 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

VR1_FB

U32-2

U31_FORCE2

U31_SENSE1

U31_SENSE2

U31_SHDN1#

R355_C147

U31_SHDN2#

D24_U32

U31_FORCE1

Q49_B

Q48_B

TUAL54,6,7

VTTPWRGD12 6

VTTPWRGD 4

VTTPWRGD5# 27

TYPEDET#11

VCC3_3

VCC3_3

VCC3_3

VCC5

V1_8SB

VCC5

V1_8SB

VCC12

VTT

VCC12VCC5SBY

VCC5

VCC5

VCC5VTT

VCC1_8

VDDQ

VCC3_3

VCC3_3

D23 BAT54C

12

3

12

3

R366732 1%

R3681k 1%

Q49NPN

Q48PNP

Q432N7002

Q442N7002

R3782.2k

R3791k

C17410 uF

U32B

LM393 Ch2

5

67

IN+ 2

IN- 2OUT 2

R38020k

C1730.1 uF

C150

100uF

C151

100uF

C152

4.7uF

C153

4.7uF

C149

0.1uF

C156

100uF

C157

100uF

C158

4.7uF

C159

4.7uF

C155

0.1uF

ADM1051A

U31

8

4

53

7

16

2

VCC

GND

SHDN1#SHDN2#

FORCE 1

FORCE 2SENSE 1

SENSE 2

Q39PHD55N03LT

Q40MTD3055VLT4

R3543.3k

C148

0.1uF

R3563.3k

R35910k

R364

49.9 1%

R357

0

R358

1M - NPOP

R367

10 1%

Q41FDN335N

R3550

C147

1.0uF

R402

470

R360

100 1%

R3615620 1%

R401

220

R400

220

C160

22uF Tantalum

D24BAT54C

12

3

12

3

C162

0.1uF

R3811k

U32A

LM393 Ch1

21

8

4

3

IN- 1OUT 1

VCC

GND

IN+ 1

VR1

LT1587-ADJ

32

1

VINVOUT

ADJ

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

New V1_SB Circuitry

This takes the place of

the old V1_8SB circuit.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VRegs: VCCVID, V1_8SB

27 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

Q45_L7

Q46_R386

Q45_L8

U34_C188

VID0

VID2VID3

U34_C182R382_U34

U34_R384

VCCVID_FB

VID1

VID4U34-17

U34_R391

U34-18

U34_1415

VID[0:4]29,32 VRM_PWRGD 13VTTPWRGD5#26

VCC12

VCC5

VCC5

VCCVID

V1_8SB

V3SB

R404

32.4 1%

R405

38.3 1%

C1830.1uF

C1844.7uF

C1940.1uF

R392 0

U34

ADP3170

161

432

5

181796

20

1415

13

8

12

111019

7

VCCVID3

VID0VID1VID2

VID25

DRVHDRVL

FBPWRGD

GND

LRDRVLRFB

COMP

SD

CT

CS+CS-

PGND

REF

R382 10 (805)

C197

C188

100pFR390

25.5k 1%R391 0

R393

154k 1%

C1930.001uF

C17510uF

C1773300uF

C1783300uF

C1790.1uF

C1804.7uF

C1760.1uF

C1814.7uF

L7 1.7uH

Q45SUD50N03-07

Q46SUD50N03-07

R385 4.7 (805)R386 2.2 (805)

R388

2.2 (805)

C1894700pF

L8 1.2uH

R389 2 mOhm (2512)

R383220

R384220

C182 0.001uF

C185820uF

C190820uF

C186820uF

C191820uF

C1921000uF

C1871000uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Stuff this box

Do not stuff this box.

Debug note:Stuff only one box.

1206 pack

1210 pack

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

VRegs: Duals, 3.3SB, 2.5, VCMOS

28 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

U2_R20

U2_C4

U2_Q5

U2_Q8

U2_Q7U2_Q4

Q3_Feedback

Q42_Feedback

SLP_S5#13SLP_S3#6,13,21

VCC3_3VCC12VCC5SBY

VCC3SBYV3SB VCC5SBY

VCC5DUALVCC5SBY

VCC5 VCC2_5

VCC3_3

VCC5

VCMOSVCC3_3

VCC1_8

R3691.13 1%

R3709.31 1%

C5

1UFC18

1UFR2010K

C4

0.1UF

C8

1UF

+ EC6

10UF

PR3

100,1%

PR2

100,1%

+ EC5

100UF

C7

0.1UF

U2

RT9641

141

3

49

6752

13

15

16

11

10

12

812

V

5VS

B

3V3DLSB

3V3DLFAULT/MSET

S3S5EN5VDLEN3VDLSS

DRV2

VSEN2

5VDLSB

DLA

5VDL

GN

D

Q3

LM1117ADJ

3

1

2VIN AD

J

VOUT

Q5NDS356AP/SOT23

+EC17

100UF

+EC11

10UF

+EC14

1500UF+EC20

10UF

+EC19

100UF

+EC10

100UF

+EC15

100UF

+EC22

100UF

Q8

FDS8936 / SI9936

1

2

3

4 5

6

7

8S1

G1

S2

G2 D2

D2

D1

D1

Q7

HUF76121D3S/TO252Q4

NZT651/SOT223

PR44

49.9 1%

+ EC43

10UF

Q42

LT1117ADJ

3

1

2VIN AD

J

VOUT

PR45

10 1%

+ EC42

10UF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SW 5

OFF FORCE CPU FREQ STRAP TO SAFE MODE(1111)USE CPU FREQ STRAP IN ICH REGISTER

AC_SDOUTON

STRAP(SPKR)

OFF REBOOT ON 2ND WATCHDOG TIMEOUT

SW 6NO REBOOT ON 2ND WATCHDOG TIMEOUTON

ON

SW 7OFF

ON BOARD AC97 CODECPRIMARY CODECDISABLE

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

System Config DIP Switches

29 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

SW1_R262SW1_R263 ICH_SPKR 13,19,24

AC_RST#13,24

PRI_DWN#12,24 PRI_DWN_RST# 19

JPR_VID03,32

JPR_VID13,32

JPR_VID33,32

JPR_VID43,32

JPR_VID23,32

VID221,27,32VID321,27,32VID427,32

VID021,27,32VID121,27,32

BSEL#14,32

BSEL#04,32

R_BSEL#07R_REFCLK7 FMOD1 6

FMOD0 6

AC_SDOUT 13,19,24

VCC3_3

VCC5SBY

VCC3_3 V3SB

V3SB

RP51K/8P4R

1 3 5 78642

RP61K/8P4R

1 3 5 78642

R153

10K

U19C

74LVC06A

5 6

R394 8.2k

R395 8.2k

R262 8.2KR263 8.2K

SW1 DIPSW-812345678

161514131211109

RN592.2K/8P4R

1 3 5 7

2 4 6 8

D17

1N4148

1 2 3

19 20 21

4 5 6

7 8 9

10 11 12

13 14 15

16 17 18

J5

7x3 JPR HDR

23456789101112131415161718192021

123456789

101112131415161718192021

1

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PCI ICH2

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Pullup/Pulldown Rs and Unused Gates

30 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

R188_U18

SERR#12,14,15PLOCK#12,14,15STOP#12,14,15DEVSEL#12,14,15

IRDY#12,14,15FRAME#12,14,15

PERR#12,14,15

TRDY#12,14,15

PREQ#112,14PREQ#012,14

PREQ#212,15

ACK64#14,15

SMBALERT#13

KBRST#12,21A20GATE12,21

PCI_REQ#A12OVT#13,21

AC_SDIN113,24

AC_SDIN013,19,24

ICH_IRQ#C12

ICH_IRQ#G12

ICH_IRQ#D12

ICH_IRQ#F12

ICH_IRQ#A12ICH_IRQ#B12

ICH_IRQ#H12

ICH_IRQ#E12

PIRQ#C14,15PIRQ#B11,14,15

PIRQ#D14,15

PIRQ#A11,14,15

SMLINK113,15SMLINK013,15

SERIRQ12,21

GPIO2712GPIO2513

ICH_RI#13,22

REQ64#114REQ64#214REQ64#315

ICHRST#12 PCIRST# 7,16,17,21

PCI_RST# 11,14,15

IDERST# 17

PREQ#412PREQ#512PREQ#312

SMBDATA9,10,13,21,24,32

LPC_PME#12,21

SMBCLK9,10,13,21,24,32

GPI812

VCC5 V3SB

VCC3_3

V3SB

VCC3_3

VCC3_3

V3SB

VCC3_3

VCC3_3

VCC3_3

VCC3_3 VCC3_3

VCC3_3 VCC5

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC5SBY

RP2

2.7K/10P8R

12346789

10

5R1R2R3R4R5R6R7R8

C

C

RN55

8.2K/8P4R

1357

2468

RN54

8.2K/8P4R

1357

2468

RN60

4.7K/8P4R

1357

2468

RN51

8.2K/8P4R

1357

2468RN66

2.7K/8P4R

1357

2468

RN64

2.7K/8P4R

1357

2468

RN58

2.7K/8P4R

1357

2468

RN77

8.2K/8P4R

1357

2468

R152 10K

R147 10K

RN74

0/8P4R

1357

2468

RN76

X0/8P4R

1357

2468

RN75

8.2K/8P4R

1357

2468

R276 8.2K

U18A

74LVC07A

1 2

147

BC163.1U

R1881K

R1981K

R1971K

U18B

74LVC07A

3 4

147

R1961K

U18C

74LVC07A

5 6

147

U20B

74LVC14A

43U18E

74LVC07A

11 10

147

U18F

74LVC07A

13 12

147

U18D

74LVC07A

9 8

147

U19D

74LVC06A

9 8

U20E

74LVC14A

1011

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

" GMCH : 0.1U//0.01U at each conner and each side-center "

" GMCH : Near Display Cache Quadrant "

" Display Cache : Near the Power Pins "

" GMCH : Near System Mem Quadrant "

" DIMM0 : Near Power Pins "

" DIMM1 : Near Power Pins "

" ICH : 0.1U//0.01U at each conner " " ICH : Near Power Pins "" ICH : Near Power Pins "

" misc. "

" ATX POWER " " ATX POWER " " ATX POWER "" ATX POWER "" ATX POWER "

" ICH : Near Power Pins "

" Within 70 mils of GMCH "

" DIMM2 : Near Power Pins "

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Decoupling Caps

31 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

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Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

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Page:Doc:

VCC1_8

VCC3SBY

VCC3SBY

VCC3SBY

VCC1_8V3SBVCC3_3

VCC3_3

VCC3_3 VCC5 VCC_5-VCC12-VCC12

VCCVID

V1_8SB

VCC3SBY

VDDQ

VDDQ

H3 HOLE A1234 5

678

H4 HOLE A1234 5

678

MC5

4.7UF/X7R

MC6

4.7UF/X7R

MC8

4.7UF/X7R

MC3

4.7UF/X7R

MC9

4.7UF/X7R

MC4

4.7UF/X7R

MC10

4.7UF/X7R

MC2

4.7UF/X7R

MC13

4.7UF/X7R

MC1

4.7UF/X7R

MC14

4.7UF/X7R

MC24

4.7UF

MC15

4.7UF/X7R

BC78

0.1UF

H5 HOLE A1234 5

678

MC49

4.7UF/X7R

BC71

0.1UF

H6 HOLE A1234 5

678

MC50

4.7UF/X7R

BC43

0.1UF

MC64

4.7UF/X7R

BC44

0.1UF

MC65

4.7UF/X7R

BC42

0.1UF

BC50

0.1UF

BC81

0.1UF

BC45

0.1UF

BC75

0.01UF

BC105

0.01UF

BC95

0.01UF

BC96

0.01UF

BC114

0.01UF

BC79

0.01UF

BC46

0.01UF

BC47

0.01UF

BC101

0.1UF

BC102

0.1UF

MC33

4.7UF

MC32

4.7UF

MC35

4.7UF

MC34

4.7UF

BC103

0.1UF

BC104

0.1UF

BC112

0.1UF

BC111

0.1UF

BC110

0.1UF

BC108

0.1UF

BC87

0.01UF

BC82

0.01UF

BC80

0.01UF

BC74

0.01UF

BC88

0.01UF

BC51

0.01UF

BC52

0.01UF

BC65

0.01UF

BC48

0.01UF

BC76

0.1UF

BC66

0.1UF

MC16

4.7UF

MC11

4.7UF

MC31

4.7UF

MC30

4.7UF

BC19

0.1UF

BC39

0.1UF

BC10

0.1UF

BC8

0.1UF

MC27

4.7UF

MC17

4.7UF

H7 HOLE A1234 5

678

MC12

4.7UF

BC40

0.1UF

BC67

0.1UF

BC11

0.1UF

BC77

0.1UF

BC20

0.1UF

MC25

4.7UF

BC84

0.1UF

BC121

0.1UF

BC138

0.1UF

BC132

0.1UF

BC131

0.1UF

BC149

0.01UF

BC124

0.01UF

BC147

0.01UF

BC150

0.01UF

BC116

0.1UF

BC113

0.1UF

BC115

0.1UF

MC57

2.2UF

BC122

0.1UF

BC106

0.1UF

BC109

0.1UF

BC107

0.1UF

BC100

0.1UF

BC128

0.1UF

BC158

0.01UF

BC160

0.01UF

BC159

0.01UF

BC144

0.01UF

BC145

0.1UF

BC146

0.1UF

BC169

0.01UF

BC171

0.01UF

BC183

0.01UF

BC170

0.01UF

BC182

0.01UF

BC186

0.01UF

BC187

0.01UF

BC181

0.01UF

EC33

22UF

BC85

0.1UF

BC83

0.1UF

EC27

22UF

BC41

0.1UF

BC53

0.1UF

BC69

0.1UF

BC70

0.1UF

EC28

22UF

BC156

0.1UF

BC142

0.1UF

EC36

22UF

BC168

0.1UF

BC180

0.1UF

EC26

22UF

BC167

0.1UF

BC179

0.1UF

BC143

0.1UF

BC157

0.1UF

BC91

0.01UF

BC93

0.01UF

BC98

0.01UF

BC97

0.01UF

BC92

0.01UF

BC208

0.1UF

BC212

0.1UF

BC211

0.1UF

BC210

0.1UF

BC209

0.1UF

MC59

2.2UF

BC207

0.1UF

H1 HOLE A1234 5

678

BC206

0.1UF

BC205

0.1UF

BC204

0.1UF

MC60

4.7UF

MC26

4.7UF

BC94

0.01UF

BC216

0.1UF

BC213

0.1UF

BC214

0.1UF

BC215

0.1UF

BC217

0.1UF

BC218

0.1UF

MC61

4.7UF

MC62

4.7UF

MC63

4.7UF

H8 HOLE A1234 5

678

H9 HOLE A1234 5

678

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Internal Debug headers

32 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

R_SMBCLKJPR_VID0JPR_VID2

VID3

JPR_VID4

VID1

VID4VID2VID0

R_SMBDATA

JPR_VID1JPR_VID3

VID[4:0]21,27,29

R_SMBCLK 6

GTLREF 4,7 GTLREFA 4 HUBREF_ICH 12 CONN_AGPREF 8,11

JPR_VID[4:0]3,29

BSEL#1 4,29BSEL#0 4,29

R_SMBDATA 6

PANSWIN21,24

HWRST#24,25 SMBDATA 9,10,13,21,24,30SMBCLK 9,10,13,21,24,30

VTT VTT VCC1_8 VCC3SBY VDDQ

J4

2x15 HDR

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 30

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 30

J6

HEADER_3

1

32

J7

HEADER_3

1

32

J8

HEADER_3

1

32

J9

HEADER_3

1

32

J10

HEADER_3

1

32

R396 0

R397 0

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

No-stuff C198 - debug site only

Stuff either R5 or R415. See p4.

Intel(R) 815E Chipset Universal Socket 370 CRB

1.05

Thermtrip

33 33

Thursday, November 29, 2001Thursday, November 29, 2001

Document:

Page Name:

Revision:Platform Applications Engineering

1900 Prairie City RoadFolsom, CA 95630

Last Revised:

Page No:

of

Page:Doc:

Q52_R416

N6395404

Q51_Q52

THERMTRIP#4

PWRBTN# 13,21

CPURST#4,7

CPU_PWGD4,12

N6395403 4

VCC1_8 VCC1_8 V3SB

R412 1K

R413510

R4141.3k

C198X0.01uF

R415 0

Q522N3904

R416

2.2k

Q502N3904

Q512N3904

R408

0

R409

4.7k

R410

1K

R411

20k