2012_2013 IEEE_VLSI_DSP_PROJECT_TITLES.pdf

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2012 IEEE VLSI PROJECT TITLES

IMAGE PROCESSING

1. Cognition and Removal of Impulse Noise With Uncertainty

2. Fast Higher-Order MR Image Reconstruction Using Singular-Vector Separation

3. Image Deblurring Using Derivative Compressed Sensing for Optical Imaging

Application

4. New Families of Fourier Eigen functions for Steerable Filtering

5. Scalable Coding of Encrypted Images

6. A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet

Transform

7. Design and Implementation of a Pipelined Datapath for High-Speed Face

Detection Using FPGA

8. Chaos-Based Security Solution for Fingerprint Data During Communication and

Transmission

9. An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color

Image Fusion

10. Interference Removal Operation for Spread Spectrum Fingerprinting Scheme

11. Robust Watermarking of Compressed and Encrypted JPEG2000 Images

12. Spread Spectrum Magnetic Resonance Imaging

13. VLSI Architecture of Arithmetic Coder Used in SPIHT

ARITHMETIC CORES

1. Investigating the Impact of Logic and Circuit Implementation on Full Adder

Performance

2. Optimizing Floating Point Units in Hybrid FPGAs

3. Low-Power and Area-Efficient Carry Select Adder

COMMUNICATION SYSTEMS

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1. A Highly-Integrated 3–8 GHz Ultra-Wideband RF Transmitter With Digital-

Assisted Carrier Leakage Calibration and Automatic Transmit Power Control

2. High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-

Search Algorithm

3. Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-

Decision Reed-Solomon Decoding

4. Power Management of MIMO Network Interfaces on Mobile Systems

5. Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error

Correction

6. A Fourier Based Method for Approximating the Joint Detection Probability in

MIMO Communications

7. Low Complexity Transmitter Architectures for SFBC MIMO-OFDM Systems

8. On the Reduction of Additive Complexity of Cyclotomic FFTs

9. A Mutual Distortion and Impairment Compensator for Wideband Direct-

Conversion Transmitters Using Neural Networks

10. Segmentation of Source Symbols for Adaptive Arithmetic Coding

11. Cooperative Beam forming for Cognitive Radio Networks-A Cross-Layer Design

12. Dynamic Resource Allocation in MIMO-OFDMA Systems with Full-Duplex and

Hybrid Relaying

13. Good Synchronization Sequences for Permutation Codes

14. Low Latency Coding- Convolutional Codes vs LDPC Codes

15. Low-Complexity Iterative Channel Estimation for Turbo Receivers

16. Spectrum Sensing in the Presence of Multiple Primary Users

17. The Design of Hybrid Asymmetric-FIR Analog Pulse-Shaping Filters Against

Receiver Timing Jitter

18. Uncoordinated Beam forming for Cognitive Networks

19. 3D MIMO-OFDM Channel Estimation

20. Interleaved Product LDPC Codes

21. Secure Communication in the Low-SNR Regime

22. Blind Signal Processing for Impulsive Noise Channels



23. Curvature Based ECG Signal Compression for Effective Communication on

WPAN

24. Distributed Coordination Protocol for Ad Hoc Cognitive Radio Networks

25. A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA

Transmitter

26. A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time

Filter for m-WiMAX

27. A Novel Filter-Bank Multicarrier Scheme to Mitigate the Intrinsic Interference

Application to MIMO Systems

28. Differential Coding for MAC Based Two-User MIMO Communication Systems

29. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

30. New S-BandBand pass Filter (BPF) With Wideband Passband for Wireless

Communication Systems

31. Transmission of 4-ASK Optical Fast OFDM With Chromatic Dispersion

Compensation

32. VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband

Transmitter

33. A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA

Transmitter

AUDIO/SPEECH SIGNAL PROCESSING

1. Enhancement of Single-Channel Periodic Signals in the Time-Domain

2. Multi-View and Multi-Objective Semi-Supervised Learning for HMM-Based

Automatic Speech Recognition

3. Musical-Noise-Free Speech Enhancement Based on Optimized Iterative Spectral

Subtraction

4. Robustness and Regularization of Personal Audio Systems

5. Speaker and Noise Factorization for Robust Speech Recognition



6. State-Space Frequency-Domain Adaptive Filtering for Nonlinear Acoustic Echo

Cancellation

7. Vocal Tract Length Normalization for Statistical Parametric Speech Synthesis

8. A Dual-Channel Time-Spread Echo Method for Audio Watermarking

9. A Low-Complexity Design for an MP3 Multi-Channel

10. Telephone Channel Compensation in Speaker Verification Using a Polynomial

Approximation in the Log-Filter-Bank Energy Domain

11. Enhancement of Residual Echo for Robust Acoustic Echo Cancellation

12. A Wiener Filter Approach to Microphone Leakage Reduction in Close-

Microphone Applications

CRYPTOGRAPHY TECHNIQUE

1. Efficient FPGA Implementations of Point Multiplication on Binary Edwards &

Generalized Hessian Curves Using

2. Construction of Optimum Composite Field Architecture for Compact High-

Throughput AES S-Boxes

3. Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear

Arithmetic Codes

4. A Formal Approach to Designing Cryptographic Processors Based on GF(2^m)

Arithmetic Circuits

5. SIGNAL PROCESSING

6. A Highly-Digital VCO-Based ADC Using Phase Interpolator & Digital

Calibration

7. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation

Selection

8. Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency

Multiplier

9. Resource-Efficient FPGA Architecture and Implementation of Hough Transform



10. A Low-Power Low-Cost Design of Primary Synchronization Signal Detection

11. A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio

Receivers

12. Hardware Implementation of Nakagami and Weibull Variate Generators

13. Pipelined Parallel FFT Architectures via Folding Transformation

14. A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS-

LMS Adaptive Filter

15. A Single-Pass-Based Localized Adaptive Interpolation Filter for Video Coding

16. An Optimization-Based Parallel Particle Filter for Multitarget Tracking

17. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions

Based on Fast FIR Algorithm

18. Hierarchical Design of an Application-Specific Instruction Set Processor for

High-Throughput and Scalable FFT Processing

19. Non-Causal Time-Domain Filters for Single-Channel Noise Reduction

20. On the BIBO Stability Condition of Adaptive Recursive FLANN Filters With

Application to Nonlinear Active Noise Control

21. Pipelined Parallel FFT Architectures via Folding Transformation

22. The Design of Hybrid Symmetric-FIR_Analog Pulse-Shaping Filters

23. Universal Switching FIR Filtering

24. Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-

Recovery Logic

25. Fixed-Point Implementation of Cascaded Forward–Backward Adaptive Predictors

26. Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type-3

POWER ELECTRONICS

1. Design and Implementation of a New Multilevel Inverter Topology

2. Digital Filters for Fast Harmonic Sequence Component Separation 3Ph

3. Spread Spectrum Modulation by Using Asymmetric-Carrier Random PWM



4. A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis

Control

5. Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-

Recovery Logic

6. A Filter Bank and a Self-Tuning Adaptive Filter for the Harmonic and Inter

harmonic Estimation in Power Signals

7. A Shifted SVPWM Method to Control DC-Link Resonant Inverters and Its FPGA

Realization

8. Fully FPGA-Based Sensorless Control for Synchronous AC Drive Using an

Extended Kalman Filter

9. Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-

Width Modulators

10. Time-Domain Design of Digital Compensators for PWM DC-DC Converters

(S/H)

11. Optimal State-Feedback Control of Bilinear DC-DC Converters With Guaranteed

Regions of Stability (S/H)

12. Nonisolated ZVZCS Resonant PWM DC-DC Converter for High Step-Up and

High-Power Applications (S/H)

13. Modified Soft-Switched Three-Phase Three-Level DC-DC Converter for High-

Power Applications Having Extended Duty Cycle Range (S/H)

14. Duty Cycle Exchanging Control for Input-Series-Output-Series Connected Two

PS-FB DC-DC Converters (S/H)

15. Double-Input Converters Based on H-Bridge Cells: Derivation, Small-Signal

Modeling, and Power Sharing Analysis (S/H)

16. Design and Performance of a Bidirectional Isolated DC-DC Converter for a

Battery Energy Storage System(S/H)

17. DC Link Active Power Filter for Three-Phase Diode Rectifier (S/H)

18. Analysis of PWM Z-Source DC-DC Converter in CCM for Steady State (S/H)

19. An Active Current Reconstruction and Balancing Strategy With DC-Link Current

Sensing for a Multi-phase Coupled-Inductor Converter (S/H)



20. A Voltage-Controlled PFC Cuk Converter-Based PMBLDCM Drive for Air-

Conditioners (S)

21. A Novel Single-Stage High-Power-Factor AC-to-DC LED Driving Circuit With

Leakage Inductance Energy Recycling (S/H)

22. A Novel Loaded-Resonant Converter for the Application of DC-to-DC Energy

Conversions (S/H)

23. A New Control Approach Based on the Differential Flatness Theory for an

AC/DC Converter Used in Electric Vehicles (S)

24. A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS (S/H)

25. An Improved Pulse Width Modulation Method for Chopper-Cell-Based Modular

Multilevel Converters (S/H)

26. Average Inductor Current Sensor for Digitally Controlled Switched-Mode Power

Supplies (S/H)

27. Coupling Effect Reduction of a Voltage-Balancing Controller in Single-Phase

Cascaded Multilevel Converters (S/H)

28. Digitally Implemented Average Current-Mode Control in Discontinuous

Conduction Mode PFC Rectifier (S/H)

29. Multilayer Control for Inverters in Parallel Operation Without

Intercommunications (S/H)

30. No-Load Power Reduction Technique for AC or DC Adapters (S/H)

31. Positive Feed-Forward Control Scheme for Distributed Power Conversion System

With Multiple Voltage Sources (S)

32. Two-Switch Dual-Buck Grid-Connected Inverter With Hysteresis Current Control

(S)

33. A Low-Power AC-DC Single-Stage Converter With Reduced DC Bus Voltage

Variation(S/H)

34. A Resonant Controller With High Structural Robustness for Fixed-Point Digital

Implementations (S/H)

35. DC-DC Converter With Digital Adaptive Slope Control in Auxiliary Phase for

Optimal Transient Response and Improved Efficiency (S/H)



Note: S- SIMULATION

MISCELLANEOUS SYSTEM

1. Dual-Layer Adaptive Error Control for Network-on-Chip Links

2. Return Data Interleaving for Multi-Channel Embedded CMPs Systems

3. A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

4. Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA

5. Viterbi-Based Efficient Test Data Compression


Documents

2012_2013 IEEE_VLSI_DSP_PROJECT_TITLES.pdf