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8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
1/15
CONFIDENTIAL1
SOC Implementation to AchieveHighest Performance
& Lowest Power
Mickie Liu
Manager Strategic AccountsAugust 2011
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
2/15
CONFIDENTIAL2
Agenda
Driving Forces (Performance and Power)
SOC requirements
ARM Physical IP Solution
Performance Optimized PackTM (POP)
Standard Cell Libraries and Memories
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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CONFIDENTIAL3
ARM Compute Subsystem
Convergence Driving SoC Requirements
Interconnect &memory controllers
VideoGraphicsprocessor
Tools support forCoreSight
Coherency and virtualizationSecure systemson TrustZone
MobiCore
Comprehensiverange of videostandards onNEON and Mali-VE
Software stackoptimized forCortex + Mali 1.1 & 2.01.1
JSR237
Foundation IP & POPs
http://cms-pro.cms.local/CMS/RadEditor.NET/[ioID]51DD2016F3574D80B3B2EAA6E58E4A4Ehttp://www.arm.com/community/partners/display_company/rw/company/pls-development-tools/http://www.arm.com/community/partners/display_company/rw/company/mentor-graphics-corporation/http://www.arm.com/community/partners/display_company/rw/company/kyoto-microcomputer-co-ltd/http://www.arm.com/community/partners/display_company/rw/company/abatron/http://www.arm.com/community/partners/display_company/rw/company/yokogawa-digital-computer-corporation/8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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CONFIDENTIAL4
SOC Requirements
Millions of gates in todaysSOC designs
Not all blocks require thesame performance
Mix libraries on the same SOC
Save power and cost andmaximize performance
High Density libraries forperformance uncriticalapplications
High Performance libraries forperformance critical
applications Create different standard cell
regions during designplanning
Low-performance block Scratch pad, look
up table, timer,
graphics Dense library for low cost
High-performanceblock Processor, L1, L2 Best possible
performance
Low Power BlockSpecializedmultimediafunctions switchedon or off
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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CONFIDENTIAL5
ARM Physical IP covers the whole range
Performance
Area/Power
+
+
High Density/Low Power
High Density (7T,9T) libraries Multi Channel libraries
High Density memory compiler Low Power memory compiler
Process: Generic & Low Power
High Performance
Strain optimized libraries High Performance (12T) libraries Multi Channel libraries High Speed Memory compiler
Process: Generic & Low Power
Ultra High Performance
Processor Optimize Package
Cache Compiler
Process: Generic & Low Power
250nm 28nm
-
-
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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CONFIDENTIAL6
Processor Optimization Pack (POP)
0.8
0.9
1
1.1
1.2
1.3
1.4
Company A Company B Company C PanasonicCortex-A9
POP Enabled
Cortex-A9 GHz Results in Production
Typical silicon results
Core-OptimizedPhysical IP
ARM CertifiedBenchmarking
ImplementationKnowledge
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
7/15CONFIDENTIAL7
Example of POP Performance Boost
Vendor ProductBitcell
(sq um)Pre-shrunk
area*Address
Setup Time*AccessTime*
ARM1024x32 sizedmemory usedfor L1 cache of
Cortex-A9
RF1-HD(Std Product)
0.299 1 1 1
RF1-HS(Std Product)
0.374 1.21 0.8 0.72
RA1-HS(Std Product)
0.374 1.67 0.67 0.61
Fast CacheInstance (POP)
0.374 1.29 0.47 0.5
* normalized
Almost 50% fasterperformance
Knowing the critical path of Cortex-A9 => Fine tuned memory design!!
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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Cortex-A9 MP Dual Core TSMC 40LP >1.0GHz
867MHz (125C)860MHz (-40C)
LVt andMulti Channel
POP Physical IPand ARMImplementationKnowledge
1014MHz (125C)1067MHz (-40C)
LVt , Multi
Channel & OD
POP Physical IPand ARMImplementationKnowledge
1.4GHzTypical Silicon
0.5
GHz
1.0
0.675GHz
Mixed Vt
Implemented
using genericPhysical IP
SS, 0.99V, 125C SS, 0.99V SS, 1.08V TT, 1.2V, 25C
mWat Fmax
500
1000
888mW
(TT)
623m
W(
TT)
1240mW(TT)
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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Library Performance Library Selection
Optimal Libraryfor each section
of the curve
Intersection points depend on
Primary factors Design and constraints Technology
Node (90, 65, 40) Process option (G, LP..) Vt (RVT, HVt)
Secondary factors Synthesis and P&R tools Experience
SC9/10
SC12
SC7/8
(65nm)
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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SC12 with Strain Optimized Layout Cells
Strained silicon
Atoms are further apart,
reducing atomic forces
Improves mobility,
resulting in betterchip performance
How to strain silicon ? Put over another
material (SiGe) withlarger lattice
Atoms will line up,stretching the silicon
SC12 min-L librarywith strain optimized cells provides10% more performance for 40G!
Different layout techniques can beused to optimize the
performance advantage(s) ofstrained silicon
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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Addressing Leakage
For Max Performance design
POP gives you implementationflexibility to use as much LVt C40as needed.
POP utilizes an ARM developed
methodology to carry out leakagereduction
Does not disruptrouting/placement
Simply driven by in-placeoptimization cell replacement
0.01
0.10
1.00
10.00
0.40 0.60 0.80 1.00 1.20 1.40 1.60
Rela
tiveLeakageFF,
125C,
1.1
0V
Relative Performance SS -40C 0.99V
Performance vs Leakage
for ARM multi-channel libraries
at TSMC CLN40LP
c50
c50
c50
c40
c40RVT
LVT
HVT
Vnom = 1.1V
V1.3 PDK
SPICE TN40CLSP004_1_1_2
Extraction Based Data
LVTC50,100%
LVT,C4040%LVT
C50,60%
LVT,C40
100%
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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Memory Selection and Performance
25-36% Difference in Area 30-40% Difference in Performance
4k 512k
RelativePerformance
4k 512k
RelativeArea
H I G H S P E E D H I G H D E N I S T Y
Memory Architecture tradeoff
Memory Instance Size Memory Instance Size
High Speed
High Density
High Speed
High Density
8/2/2019 2011 ARM Physical IP Seminar Taiwan Mickie Liu
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Memory Power Management Modes
CoreDec
SA/IO
LevelShifters
CTRL
CoreDec
SA/IO
LevelShifters
CTRL
CoreDec
SA/IO
LevelShifte
rs
CTRL
Headers for Memory Array
Footers for Periphery
Precharge ON/OFF
CoreDec
SA/IO
LevelShifte
rs
CTRL
Headers for Memory Array
Footers for Periphery
Precharge ON/OFF
CoreDec
SA/IO
LevelShifters
CTRL
Headers for Memory Array
Footers for Periphery
Precharge ON/OFF
Retention (external PG) Power down (external PG)
Retention 1 (with PG) Retention 2 (with PG) Power down (with PG)
Power OFF
External power gate,designed by user
Internal power gatein memory
Source Bias for
Memory Array
Low Voltage inmemory array
(Data Retained)
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Summary
ARM understands the driving forces and SoC requirements
Performance continues to be important Power continues to gain in importance
ARM Physical IP provides the solution
IP covers the range of needs across a spectrum ofpower/performance optimization points
Processor Optimized Pack (POP)
Includes all the necessary IP to maximize ARM Core Performance
Libraries and Memories architected for specific applications
High Performance and Multi-Channel libraries give wide range ofperformance and power
Memories are architected for High Speed and/or High Density withmany low power features