2010-4DM4-Lab4-ALU

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4DM4 Lab. #4, Posted Monday, Nov 10, 2008

ECE 4DM4 - Computer Architecture

Lab # 4 A Pipelined ALU Unit

Posted: Monday, Nov. 15, 2010Starts: Wednesday, Nov. 17, 2010

Ends: Friday, Nov. 26, 2010

Instr_In: Instruction supplied to ALU_unit from ID_Unit

Instr_Out Instruction supplied from ALU_unit to Load/Store Unit

A_op: 32 bit A_operand for the ALU (from ID_Unit)B_op: 32 bit B_operand for the ALU (from ID_Unit)

C_addr: 5 bit identify of the destination register for the C_ operand

C_op: 32 bit C_operand to be written back to the ID_unit

C_write: 1 bit control signal: 1-> write the C_op to the register file in the ID_unit.

ALU-Unit - Behavioral Description Overview:

The ALU_Unit accepts two operands (the A_op and B_op) from the ID_Unit per clockcycle, and performs the required ALU operations on those operands to produce the

C_operand. In a 5-stage pipeline, The C_Operand would then go to the MEM and WB

stages, where it is written back to the ID unit. The ALU operation to be performed is

specified in the Opcode on the instruction supplied on the Instr_In port.

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The ALU_unit will process instructions which are valid ALU instructions. If the

ALU_Unit receives an instruction which is not an ALU instruction, ie a NO-OP, it simply

passes it through the pipeline without doing anything.

ALU UNIT Behavioural Rules:

A rising clock edge denotes a new clock cycle, call it "clock cycle t".

(1) At the beginning of clock cycle t, if Valid_Instr=1, then the instruction on the Instr_In

port is valid, and the ALU_unit will process this instruction, its A operand and B

operand.

(2) Before the next rising clock edge, the C_operand computed in the current clock cycleis asserted onto the C_operand port for the duration of the current clock cycle, and the

C_write signal is asserted. This allows the ID state to capture these values at the next

rising edge, and allows the C operand to be written back to the registers in the ID stage,

one clock cycle after they are computed. In our lab, the ALU unit is performing theWrite-Back.

Comments:

- There are special situations called "data hazards" which can exist. You can assume

that data hazards are handled by the compiler.

Laboratory # 4 - ALU Unit Writeup:

(1) Implement the ALU Unit in well-documented behavioral VHDL. The VHDL should

be synthesizable to a high-end ALTERA FPLD. Provide a hardware circuit diagram

indicating the hardware your VHDL is expected to synthesize to. The circuit diagram

should contain basic logic blocks, such as adders, registers, multiplexers,

comparators, etc. In particular, illustrate the "inferred registers", which are

synthesized using DFFs. Label the expected width (in bits) of these blocks.

Remember, a hardware diagram is like a blueprint of your circuit.

(2) Describe your expected resource usage (IO pins, DFFs, LABs, LEs, EABs), using

your knowledge on synthesis from lab. 1. Examine the compiler report file. Compare

the compiler's resource usage with your expected resource usage, and comment on

any discrepancies. In particular, compare the DFFs expected and the DFFs used.

(3) Design the ALU unit to be as fast as possible, and to be reasonably hardware

efficient. Discuss any design features that make your ALU unit hardware efficient

and fast.

(4) Estimate the maximum clock rate of your circuit by identifying the critical path in

your hardware diagram, and using your knowledge on synthesis and delay for basic

operations from lab. #1. Discuss the compilers reported maximum clock rate, i.e.,

does it match your expectations ?

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(5) Using the waveform editor, validate the ALU unit's behaviour through the followingtests.

DEMOS: You need to demonstrate the correct operation to your lab to a TA, and have

them record the demonstration and its grade. You do not need to capture images to

include in a lab report.

Tests to Demonstrate to your TA:

(T1) The ALU unit receives the appropriate data from the ID_Unit : Set the instruction

for the current clock cycle to be ADD R3,R2,R1. Set the A_op and B_op inputs to

be +9 and -9 respectively. Verify that the C_op is 0, the C_addr is 3, and the C_write

is asserted before the next rising edge.

(T2) Modify and Repeat Test T1, for the other ALU instructions that you haveimplemented. In your report, it should be clear which instructions you have

implemented, and which instructions you have validated through a test.The TA should record which instructions have been demonstrated successfully.

(6) For the ALU lab report, answer parts (1)-(4), state which instructions were

successfully demonstrated to the TA and state the TA's name, and include your

documented VHDL code for the ALU Unit. If some aspect of your unit does not

work, write a brief description to explain what needs to be done. If you cannot get the

complete ID unit working, try for a subset.

Good Luck with your design.

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Starting VHDL code for the ALU Unit-----------------------------------------------------------------------

-- Filename: ALU_Unit.vhd

-- Title: ALU Unit for 4DM4 Microprocessor

-- Authors: Honglin & Ted

-- Date: Nov, 2007-- Description: See Specs, 4DM4, Lab. #4;

-- This handout is a hint which you can modify & complete. This is NOT optimized.

-----------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; -- IEEE standard definitions for allowable logic signals, etc.

LIBRARY lpm;

USE lpm.lpm_components.ALL; -- use ALTERA's built-in components, etc.

LIBRARY ieee;USE ieee.std_logic_signed.ALL; -- definitions for signed arithmetic

-- define some OP-Codes

package constants is

CONSTANT ADD : STD_LOGIC_VECTOR(7 downto 0) := "11000000";--C0

end constants;

-----------------------------------------------------------------------

-- main Entity declaration for IF_Unit

-- not all I/O ports are here, so you wil have to add some

-----------------------------------------------------------------------

ENTITY ALU_unit IS

PORT(

clock, pause : IN STD_LOGIC;

c_write, valid_instr : OUT STD_LOGIC;

instr_in, A_op, B_op : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

instr_out, C_op : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

C_write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)

);

PROCESS(clock)

variable A_op_temp : signed(30 downto 0);

variable B_op_temp : signed(30 downto 0);

-- more variables

-- more code

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CASE op_code(7 downto 0) IS

WHEN ADD => c_op_temp

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Lab. 5 (Optional) : Putting Stages 1 - 3 Together

Sample VHDL Code for the 4DM4 CPU

----------------------------------------------------------------------------------------------------

-- Entity: CPU_ENTITY for 4DM4 COMPUTER ARCHITECTURE-- Designers: the 4DM4 class

-- Note: this code may need revision.

-- In Lab. 5 which is optional, we will likely ask that all the stages that you created be

-- connected together and demonstrated to the professor and the TA(s);

-- this code gives you a starting point

-- you may add an external memory module to this too

----------------------------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;USE ieee.std_logic_unsigned.ALL;

LIBRARY STD; -- for debugging statements

USE STD.TEXTIO.ALL;

ENTITY cpu IS

PORT (


done : IN STD_LOGIC;

instr_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

addr : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

read : OUT STD_LOGIC

);

END ENTITY cpu;

ARCHITECTURE cpu_structural OF cpu IS

COMPONENT if_unit

PORT (


load_bta, done : IN STD_LOGIC;

addr, instr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

read, valid_instr : OUT STD_LOGIC;

instr_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

offset : IN STD_LOGIC_VECTOR(15 DOWNTO 0)

);END COMPONENT;

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COMPONENT id_unit

PORT (


c_write : IN STD_LOGIC;

instr_in, c_op : IN STD_LOGIC_VECTOR(31 downto 0);

c_addr : IN STD_LOGIC_VECTOR(4 downto 0);instr_out, op_a, op_b : OUT STD_LOGIC_VECTOR(31 downto 0);

offset : OUT STD_LOGIC_VECTOR(15 downto 0);

load_bta, valid_instr : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT alu_unit

PORT(


instr_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

op_a, op_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);instr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

c_op : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

c_addr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

c_write : OUT STD_LOGIC;

);

END COMPONENT;

-- define the wires (internal signals) to connect the 3 pipeline stages

SIGNAL if_id_instr, id_alu_instr, alu_ls_instr : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL op_a, op_b, c_op : STD_LOGIC_VECTOR(31 DOWNTO 0);SIGNAL c_addr : STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL c_write, load_bta : STD_LOGIC;

SIGNAL cond_code : STD_LOGIC_VECTOR (2 DOWNTO 0);

SIGNAL offset : STD_LOGIC_VECTOR (15 DOWNTO 0);

BEGIN

-- instantiate the 3 components, and interconnect them using PORT MAPs

-- here we use an "explicit association" rather than "implicit association"

PORT MAP

-- the mapping between a global signal and a components I/O ports is explicit,

-- so that the order does not matter

-- CHECK ALL THESE CONNECTIONS THEY ARE ILLUSTRATIVE ONLY

if_inst: if_unit PORT MAP (

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clock=>clock, pause=>pause,

read=>read, addr=>addr, instr=>instr_in, done=>done,

instr_out=>if_id_instr,

offset=>offset, load_bta=>load_bta);

id_inst: id_unit PORT MAP (clock=>clock, pause=>pause,

instr_in=>if_id_instr, c_write=>c_write,

c_op=>c_op, op_a=>op_a, op_b=>op_b,

c_addr=>c_addr, instr_out=>id_alu_instr,

offset=>offset, load_bta=>load_bta);

alu_inst: alu_unit PORT MAP (

clock=>clock, pause=>pause,

instr_in=>id_alu_instr,

op_a=>op_a, op_b =>op_b,

instr_out=>alu_ls_instr, c_op=>c_op,c_addr=>c_addr, c_write=>c_write);

END ARCHITECTURE cpu_structural;

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2010-4DM4-Lab4-ALU