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ON-CHIP SPECTRUM/VECTOR ANALYZER FOR BUILT-INTESTING OF ANALOG INTEGRATED CIRCUITS

A Thesisby

MARCIA GISELA MENDEZ RIVERA

Submitted to the Office ofGraduate Studies ofTexas A&M Universityin partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

December 2002

Major Subject. Electrical Engineering

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ON-CHIP SPECTRUM/VECTOR ANALYZER FOR BUILT-INTESTING OF ANALOG INTEGRATED CIRCUITS

A Thesisby

MARCIA GISELA MENDEZ RIVERA

Submitted to Texas A&M Universityin partial fulfillment of the requirementfor the degree of

MASTER OF SCIENCE

Approved as t ty and content by:

Jose lva-Martinez(Chair ofCommittee) E anchez-Sinencioember)

Aydin Karsilayan(Member)

Frede ck Stricter(Member)

Eva Sevick-Muraca(Member)

anan Sin(Head ofDepartment)

December 2002Major Subject: Electrical Engineering

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ABSTRACT

On-Chip Spectrum/Vector Analyzer for Built-In Testing of Analog Integrated Circuits.(December 2002)Marcia Gisela Mendez Rivera, B.E. University of Guanajuato, Guanajuato, Mexico;

M.S. Instituto Nacional de Astrofisica, Optics y Electronica, Puebla, MexicoChair of Committee: Dr. Jose Silva-Martinez

The number of functions that can be integrated on a single chip has increased during thelast years, making the functional testing of circuits a challenging task. Even though thedigital testing has reached certain maturity and well-defined techniques have beendeveloped, we cannot use the same techniques for analog and mixed-signal circuits dueto the different nature of digital and analog circuits. In the case of analog circuits, thenumber ofpossible values is unlimited and there is not a specific value that tells us if thecircuit is working properly. The complexity and sensitivity of the time and voltagenature in analog circuits makes the testing task even more difficult. Even more, theanalog circuits have to be tested under different conditions; e.g. sweeping frequency andamplitude. Due to the fact that there are not specific and efficient techniques for testinganalog circuits, every analog circuit requires a particular design in order to be tested. Asa result of this, the test cost is the dominant issue in many products and the investmentmade in this stage is not recovered.

This work deals with some of the fundamental problems faced in analog testing. Newtechniques to characterize and test analog circuits using an external digital tester ratherthan an analog tester have been developed. The architecture used is a built-in self-testcircuit. The test is made in an automatic way, obtaining information that tells us if thecircuit works or not based on certain error margin. In our case, the parameters that

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concern us are transfer function (magnitude and phase response) and harmonic distortioncomponents.

The techniques proposed to measure the frequency response of the DUT rely on thecapability of the circuit to generate a low distortion and accurate sinusoidal signal to beused as stimuli. The switched-capacitor based circuit techniques used ensure thesynchronization between the blocks involved. The use of the same digital signal forcontrolling these blocks assures that the tracking error could be within 0. '/o if switched-capacitor techniques are used.

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To my beloved family:My husband Ari, my daughter Aimee,

my parents Luts Alfonso and Lydia and my brother Luis Alfonso

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ACKNOWLEDGMENTS

I would like to thank my advisor Dr. Jose Silva-Martinez for his support, guidance, andpatience beyond the advisor-student relationship during this research work and for hisinvaluable friendship during all these years. The advice and time he always shared withme are a very important part of my education. I also would like to thank Dr. Sanchez-Sinencio for his support during the time I spent in the AMSC group, as well as expressmy gratitude to all the members of my committee, Dr. Karsilayan, Dr. Stricter and Dr.Sevick, for their support and help to complete this work.

I would like to thank in a very special way to the family Silva-Rivas whose supportplayed a very important role in the culmination of this work, especially Mayo, whoseIriendship and support were primordial and priceless.

I also want to thank to all of my friends and colleagues in the AMSC group that helpedin one way or another during this work. The interaction I had with all of them was reallyimportant during my studies here at Texas A&M.

Finally I would like to dedicate this work to the most important persons in my life: myhusband Ari, my daughter Aimee, my parents Luis Alfonso and Lydia and my brotherLuis Alfonso, whose love and support were the foundations to make my dreams cametrue. This works belongs to all ofyou.

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vn

TABLE OF CONTENTS

ABSTRACT. PagenlDEDICATION.ACKNOWLEDGMENTS.TABLE OF CONTENTS.

V1

V11

LIST OF FIGURES.LIST OF TABLES.CHAPTER

1X

X11

I INTRODUCTION.A. Introduction.B. Motivation.C. Basics on Testing .D. Organization.

II ON-CHIP SPECTRUM AND NETWORKANALYZER PRINCIPLES.

1467

A. Introduction.B. Basic Principles.C. Proposed Solution.D. Specifications.III BASIC BUILDING BLOCKS.

910151924

A. Introduction.B. Sinewave GeneratorC. Bandpass FilterD. Voltage Gain Amplifier (VGA) . .E. Operational Amplifier (Opamp) . .F. Analog-to-Digital Converter.

242429373941

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vnt

CHAPTERIV SIMULATION AND EXPERIMENTAL RESULTS . .

Page45

A. Introduction.B. Sinewave Generator .C. Bandpass FilterD. Voltage Gain Amplifier.V CONCLUSIONS

45465055

REFERENCES.APPENDIX.

6164

VITA. 75

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LIST OF FIGURES

FIGURETest at each stage of the manufacturing process. . . Page1.21.3

1.41.51.62.12.22.32.4

Test economics in the manufacturing steps. . .Production cost. Manufacturing cost includes the design, high-levelsimulations, actual device-level design, layout and fabrication forproduction.Digital vs. analog functionalityTesting in circuits. Block diagram.Parameters to be measured in analog circuits . .Relationship between time and frequency domains. . .Frequency domain representation of a filter bank . .Block diagram of a superheterodyne spechnm analyzer. . .Typical swept-tuned spectrum analyzer.

10

1313

2.5 Spectrum analyzer measurement for different values of14ir and ST. 142.62.72.8

On-chip spectrum/vector analyzer basic block diagram. .On-chip spectrum/vector analyzer block diagram. . .Center-to-sampling f'requency relationship. (a)f, = 8 f, (b)f, = /6.

1618

223.13.23.3

Variable gain amplifier used to generate the sinewave. . .Logic control for the sinewave generator.-Output sequence for the logic.

2526

3.43.5

Simulated control signals and output of the sinewave generator. . . . . 27Quality factor effects in the selection of the harmonic distortion

3.63.7

component. (a) High Q (b) Low Q.Effect of the accuracy of the center frequency on fundamental,second and third harmonic measurements.Switched-capacitor bandpass filter.

30

3132

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FIGURE Page3.8 Block diagram for the switched-capacitor bandpass filter. . 333.9 Bandpass filter with additional sampling frequency in Cti. (fj' = '/4 .

fi and js '= '/~. fj). . 353.103.113.123.133.143.153.163.174.14.24.3

Switcap simulation for the filter.Simulated time response for the bandpass filter. .Variable gain amplifier.Opamp schematicBlock diagram of the algorithmic A/D converter. . .Flow graph for the algorithmic approach.(a) Schematic of the multiplier by two. (b) Phases. . .Multiplier by two: circuit configuration for each phase. . .(a) Cadence layout of the chip. (b) Microphotograph . .Simulated output of the sinewave generator . .Measured output signal of the sinewave generator . .

3637384041424444454647

4.44.5

Sinusoidal signal spectrum at 1 kHz and +50 mV reference voltage . 48Spectral noise density for the output of the sinewave generator withV,~+100 mV and 1 kHz center frequency. . .4.6

4.74.84.94.104.114.124.13

4.14A. 1

Measured transfer function for the bandpass filter. . .Error in the center frequency for the bandpass filter. . .Gain for the bandpass filter.Quality factor for the bandpass filter.Intermodulation measurement for the bandpass filter. . .Noise of the bandpass filter.VGA output for different gains.Error in the VGA measurements. The input signal amplitude is +100mV.Noise in the VGA.Switched-capacitor bandpass filter.

51515252535456

565767

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FIGUREA.2 Block diagram for the switched-capacitor bandpass filter. .B. Opamp schematic

Page6769

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LIST OF TABLES

TABLE2.1 PageTarget specifications for the on-chip network/spectrum analyzer. . 233.13.23.33.43.53.64.1

4.24.34.4B.

Capacitor values for the sinewave generator. . .Capacitor values for the SC bandpass filter. . .New capacitor values for the SC bandpass filter. . .Final capacitor values for the SC bandpass filter. . .Capacitor values for the VGA.Sizes for the opamp transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulated and experimental results for the harmonic components ofthe sinewave generator for V,=50 mV.Sinewave generator measurements summary . .Bandpass filter measurement summaryMeasurement summarySizes for the opamp transistors.

29

35353841

4650555772

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CHAPTER I

INTRODUCTIONA. Introduction

The process of making integrated circuits consists of several steps. First, the idea andspecifications must be translated into a design that is simulated and optimized until itworks within the specs. Once the design is finished, the layout is made: in this step, post-layout simulations help to determine if the original design corresponds to the schematicthat has been developed. When the chip is fabricated, it is tested to verify that the mainspecifications are within certain boundaries. Finally, provided that the circuit worksproperly, it is sent to major production. Again, testing is necessary to ensure properperformance of each fabncated circuit.

Testing is present in several steps of the production process. Fig I. shows the idealprocess of placing a product on the market [1,2]. If in any of these steps a failure exist,optimization or modifications of the original design must be made. Some of thesefailures can occur at the layout level, on the wafer or in packaged parts. There are manyissues that can make the circuit to work improperly: bad design or layout, chemical orenvironmental agents and even careless handling can affect the final performance of thechip. The distribution of the test throughout the manufacturing process is more costeffective because only non-defective components are permitted to move to the next levelof assembly.

This thesis follows the style and format of the IEEEJournal ofSolid-State Circuits.

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Wafer DieProcess Test Pastose Bum-ia

Substrate

Test

IninalAssembly

BoardTest FmalAssembly

SystemFmalTest

Discard

To FteldProcess Test

Repair

Diagnosisand Repatr

Diagnosisand Repair

Fig. 1. Test at each stage of the manufacturing process.

Since testing is encountered many times in the process of Integrated Circuits (IC)fabrication, a large amount of money is invested in this stage and ls usually notrecovered. Fig. 1.2 shows the cost associated to each stage of the process of making anintegrated circuit. It can be seen that it takes ten times the effort through each successivemanufactunng step to detect, locate and repair a faulty component. Therefore, the testingat early stages helps to reduce the testing cost of the next stage.

1000Cost Per Component

10010

0.1Test'O

ActtvttyA pM

Fig. 1.2. Test economics in the manufacturing steps.

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B. MotivationModem integrated circuits are becoming more complex, which does not assure optimalperformance and the access to internal nodes is difficult due to both the limited numberof pins available and buffers required, making the testing a challenging task. Severaltechniques that involve built-in self-testing and allow diagnosing failures have beendeveloped. However, the growth in complexity and number of functions that can beintegrated on a single-chip have increased rapidly in the last years, making the testing adifficult task [3].Even tough the majority of these systems are mainly digital, the analogsection is still an important part on such systems.Albeit the digital testing has reached certain maturity and well-defined techniques have

been developed, we can not use the same techniques for analog and mixed-signal circuitsdue to the different nature of digital and analog circuits. In digital circuits, theinformation is binary and only two possible values are required; the main issue is,however, to test both robustness and speed. In the case of analog circuits, the number ofpossible values is unlimited and there is not a specific value that tells us if the circuit isworking properly, so a boundary must be set; a graphic comparison is shown in Fig. 1.4.Testing in analog circuits faces many problems that digital testing has overcome. Thecomplexity and sensitivity of the time and voltage nature in analog circuits makes thetesting task even more difficult. Even more, the analog circuits have to be tested underdifferent conditions; e.g., sweeping frequency and amplitude. There are not specific andefficient techniques for testing analog circuits: every analog circuit requires a particulardesign in order to be tested.

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Bad GoodDigital Function

BadGood

BadAnalog Function

Fig. 1.4. Digital vs. analog functionality.

In the case of mixed-signal circuits, the digital part should be tested separately from theanalog part. Mixed signal testing is not only made difficult by the long testing times ofanalog components which must be tested on expensive automated test equipment withmixed signal capabilities, but also the access to analog nodes is usually limited torelatively few inputs and outputs since it is not possible to bnng all the analog inputs andoutputs out to the pins.

There are several factors that have contributed to make the mixed-signal testing morecomplex, such as the access to the analog components and the close interaction betweenboth digital and analog parts. Other issues to consider are the reduction of the test timeand the area used by the testing circuit. They should not represent a large area overheadfor the whole system. Also, the presence of the testing circuit must affect as less aspossible the measurements obtained.

Mixed-signal testing techniques can be divided into two parts: DC BIST and AC BIST[4].In the first one, we are only concerned for the DC behavior of the Device Under Test(DUT): i.e. operation point. In the AC BIST we try to measure the frequency response ofthe system. Traditionally, the AC characterization of a linear system is done on the

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frequency domain: a sinusoidal signal is applied to the input of the DUT and thefrequency of this signal is swept. The output is converted to the digital format andanalyzed. It may seem quite simple and straightforward but this process is expensive andtime consuming. Therefore, the need for a solution to this problem is evident.

C. Basics on Testing

Fig. 1.5 shows the block diagram of how the testing is performed in analog circuits.There are two blocks: the device under test (DUT) and the circuit performing the test.Using the switches, normal operation or testing mode can be chosen. The area of the testcircuit should be smaller than the DUT. The goal is to test the DUT in an automatic waywithout changing its original configuration.

Input DUT Output

L ectorAnalyzerFig. 1.5. Testing in circuits. Block diagram.Fig. 1.6 shows, some of the many parameters that can be measured in analog circuits:frequency response, amplitude, phase, noise, harmonic distortion, etc. Depending on theapplication of the DUT, some of these parameters are going to be more important thanothers and the circuit should allow us to test the most critical parameters, all of theseusing an input signal and measuring an output. In our case, some of the parameters ofconcern are:

~ Transfer function (Iiequency response).

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~ Harmonic distortion.~ Noise.

Input OutputDUT

VectorAnalyzer

Amphtude BIV Analysis

Fig. 1.6. Parameters to be measured in analog circuits.

The main goal of this research is to develop new techniques to integrate the testingcircuit on the same chip and characterize and test analog circuits using an external digitaltester rather that an analog tester in order to reduce test time and cost [5]. Thearchitecture to be used is a built-in test circuit. The test should be made in an automaticway, obtaining information that tells us if the circuit works or not based on certain errormargin. The tester is designed in such a way that allows us to test the most importantparameters, such as transfer function (magnitude and phase response) and harmonicdistortion components. This work deals with some of the many features than can bemeasured in analog systems, and based on them, decide if the circuit works within therequired specifications.

D. Organization

The thesis is organized as follows: Chapter II describes the main principle of theproposed technique as well as some previous proposals. The third chapter deals with thedesign issues of the main building blocks involved in the proposed solution. The next

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chapter shows simulation and experimental results of the designed blocks and thecomplete system. Finally, Chapter V lists the summary and conclusions of the thesis.

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CHAPTER IION-CHIP SPECTRUM AND NETWORK ANALYZER PRINCIPLESA. Introduction

Spectrum and network analyzers are found in many laboratories for the characterizationof analog systems. The network and spectrum analyzers in use today are the result ofover half a century of continuous development. The best commercially availablespectrum analyzers today have a dynamic range greater than 100 dB (corresponding to10 orders of magnitude in power) and over seven orders of magnitude in frequency [6].With this equipment, it is possible to analyze the transfer function and the distortioncomponents of the circuit under test. The use of the spectrum analyzers for productiontesting is prohibited due to large testing time and high costs. In general, thecharactenzation or testing of an analog circuit involves the extraction of the gain andphase frequency response as well as the harmonic distortion.

Usually such measurements are performed in a large tester and take a considerableamount of time. Besides, the reconfiguration needed in the device under test adds extraparasitic to the circuit that can affect its response. The best way to correct this problem isto embed the testing circuitry on the same chip in order to reduce the interaction of thesystem with external conditions that can alter its functionality . Several approaches tothis problem have been reported [7-11],but the synchronization between the stimuligenerated and the circuits that perform the measurements is not assured. In tlus work it isdemonstrated that the use of switched-capacitor techniques and a master clock providesa self-synchrouized circuit, making the measurements reliable and precise.

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10

B. Basic PrinciplesThe traditional way of observing an electrical signal is using an oscilloscope, where twoparameters are displayed: amplitude and time. When using frequency-domain displays,we observe the same information, but using frequency instead of time domain. Thespectrum analyzer takes the analog signal (in the time domain) and converts it into thefrequency domain. The resulting spectrum measurement shows the energy of thedifferent frequency components along the frequency axis. Fig. 2.1 shows thisrelationship [12];here, we can see how a signal with two frequency components that arenot distinguishable in the time domain can be easily analyzed in the frequency domain.

Ampbtude

eeetIi

AmplitudeAmphtude

Time prequeueyFig. 2.1 Relationship between time and frequency domains.

Many signals that are not distinguishable in the time domain (such as noise andharmonic components) are clearly defined in the frequency domain. Using spectral

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analysis, it is possible to observe all the &equency components in a single frequencysweep. For a sinusoidal signal, amplitude and frequency can be measured using anoscilloscope, but for more complex signals, this task is not possible because such signalsgenerally contain more frequency components with different amplitudes and phases.This is why spectrum analyzers are useful: they allow measuring and comparing thefrequency and amplitude of individual components of a time-dependant signal.There are several ways of measuring the spectrum of a signal. One technique is the useof filter banks [13], where the time domain signal f(t) is mapped into the frequencydomain f(roj by applying the input signal into a bank of bandpass filters, each onecentered at a different frequency, as shown in Fig. 2.2. The outputs of these filters arethen passed through Root Mean Square (RMS) quantifiers to calculate the energy at thedifferent frequencies of the input signal. This approach is effective when the filters coverall the frequency range of interest. However, its ability to resolve fiequency componentsthat are close to each other is highly dependent on the bandwidth of each filter.Therefore, in order to obtain a good resolution, each filter must achieve a very smallbandwidth zion, which leads to a large number n of filters given by:

Spectrum bandwidthn = (2.1)

FrequencyFig. 2.2. Frequency domain representation of a filter bank.

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We can see that even for small frequency ranges, the number of required filters canbecome very large, which makes this option not a good candidate for on-chip testing,where silicon area must be optimized. Another problem is the aliasing that can begenerated from the overlapping filters as well as frequencies that are not covered in thenon-overlapping frequencies.

Another approach of spectrum analysis makes use of tunable filters. This technique usesa filter centered at a fixed frequency and translates the frequency of the incoming signalto the filter frequency. For this purpose, a mixer and a local oscillator (LO) are used.The &equency of the LO is chosen in such way that the difference between thefrequency of the input signal and the one of the LO are located at a specific intermediatefrequency (IF); this signal is filtered by an adjustable bandwidth bandpass filter. Bysweeping the frequency of the LO, the mixer's output, which include all the informationof the input signal, is swept through the filter. This process is knows as heterodynepnneiple.

Fig. 2.3 shows a superheterodyne spectrum analyzer. The low-pass filter limits the&equency range of the input signal to avoid alias components. Then, the filtered signal ismixed with the signal coming from the LO. The envelope of the IF signal is detected andis used to control the y-axis [6].The LO frequency is swept in order to downconvert thefrequency of the input signal; the VCO is con&oiled by a ramp generator, which alsocontrols the x-axis. In commercial single range spectrum analyzers, the IF is chosenabove its highest &equency of operation. The frequency resolution of the spectrumanalyzer is determined by the bandwidth of the IF filter. Since narrow IF bandwidths aredifficult to achieve in the Gigahertz range, most of the spectrum analyzers use several IFstages to mix down the input signal to an IF where the narrowest filtering takes place.Fig. 2.4 shows the typical swept-tuned spectrum analyzer where all these IF stages areincluded [12].The swept-tuned spectrum analyzer uses one up-conversion and multipledown-conversions (IF stages) in order to reject image frequencies. All the filters are

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fixed-tuned so better resolutions can be achieved; also, the bandwidth of the final IFfilter can be changed to control selectivity. The local oscillator sweeps across the desiredrange of frequencies (which is translated into a visual swept between the start and stopfrequencies of the spectrum being studied). The detector is used after the last IF stage torecover the incoming signal, where the detected signal is converted into a dc value,which represents the amplitude, and is sent to the circuitry that drives the display.

InputmixerX '" EnvelopeDetector Verticaldeflection

Lo

Honzontaldeflection

vco Voltage ramp

Fig. 2.3. Block diagram of a superheterodyne spectrum analyzer.

I"MaterInput

2 LOIF d)

3 LO~if xed I I~Oet le

Leman Ftiterflntaae ReieetteelI"L 0

IVanaale

I' lP Piller

3 opC ael

2 IF alter 3 IF Fdler(Rural te

Bandwtdih F It I

V dee Falter

Fig. 2.4. Typical swept-tuned spectrum analyzer.

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14

There are some important specifications that every spectrum analyzer should satisfy.First, resolution bandwidth, which is the ability to resolve signals of different&equencies, is determined by the IF bandpass filter bandwidth. Second, the optimumsweeping time for a given resolution bandwidth and the frequency span, are related asfollows [6]:

ST=k.Rzu (2.2)

where ST is the sweeping time, k is a constant that depends on the filter shape (for aGaussian filter is about 2.5), sPan is the &equency sPan and Rsrr is the resolutionbandwidth. Usually, Rsrr and ST are adjusted accordingly to the &equency span so areasonable resolution can be obtained; if a higher resolution is desired, then longersweep times will be needed. If low level signals are going to be measured, then it isnecessary to use narrow Rsrr, which implies longer measurement times. Fig. 2.5 showssome typical values for these parameters.

R=10 Hz, ST=0 03 sec R s=3 kHz, ST=0 i secR s=l kHzST=0 3 sec R s=0.3 kHz, ST=3.3 sec

Frequency

Fig. 2.5. Spectrum analyzer measurement for different values of Rsrr and ST.From the previous description it can be seen that the measurement of the signal isperformed in the time domain; therefore, it is only an approximation of the contents ofthe actual frequency of the signal. Since the spectrum analyzer only measures the power

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at a certain frequency, the phase of a given frequency component is lost; as a result, themeasurement obtained is not enough for reconstructing the time domain representationof the signal. The detection and measurement of magnitude and phase are requiredbecause these quantities provide information about the transfer function of the system.The magnitude and phase extraction can be implemented using peak detectors and phasedetectors but they usually require calibration and are prone to errors over frequency,power level and temperature variations. Calibrated RF/IF vector analyzers that uselogarithmic amplifiers have been reported [7]; these measurements are fully ratiometricsince the result is given by the ratio V,, V, .Another proposed solution is the use offilter banks that are multiplexed accordingly to the frequency being analyzed [8-11],butthe silicon area required is quite large, which makes them not very good candidates forbuilt-in testing.

From the previous discussion, the advantage of integrating frequency, magnitude andphase characterization in one technique results in a considerable saving on testing timebecause there will be no need to use two different tests in order to measure the spectrumand the transfer function of the DUT.

C. Proposed Solution

The architecture to be used is a built-in on-chip spectrum analyzer. The parameters ofconcern are transfer function, (magnitude and phase response) and harmonic distortioncomponents. For this purpose, the use of an on-chip spectrum/vector analyzer isproposed. Fig. 2.6 shows the basic block diagram of the scheme. The source generatesthe stimuli that is applied to the DUT and its output is sensed by the detector. Havingboth the input and output signals, we can compare and analyze them to decide if thecircuit is within the required specifications.

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DeviceUnderTest

Source

On-Chip Spectrum/VectorAnalyzerSignal

Processor DetectorV /

DigitalControl

xz'Output

External

Control

Fig. 2.6. On-chip spectrum/vector analyzer basic block diagram.

The techniques proposed to measure the frequency response of the DUT rely on thecapability of the circuit to generate a low distortion and accurate sinusoidal signal to beused as stimuh. Once this tone has passed through the DUT, it has to be measured andcompared with the stimuli in order to obtain the DUT transfer function.

The process descnbed above is repeated for different frequencies to obtain the full DUTcharactenzation. In order to perform the harmomc distortion testing, a single tone at afixed frequency is applied to the DUT. Then the center frequency of the high-Q filter ischanged to frequencies that are integer multiples of the frequency applied to the DUTand their respective amplitudes are measured. A vanable gain amplifier (VGA) is neededfor the optimization of the system dynamic range. Usually a very selective bandpassfilter is used in the detector in order to minimize the in-band noise and spurious tones.Therefore the frequency of the stimuli and the filter's center frequency have to be fullysynchronized in order to avoid unwanted attenuations in the measured tones. Theswitched-capacitor based techniques used ensure the synchronization between the blocksmentioned above. It is shown in this thesis that if both signal generator and bandpassfilter are controlled by the same digital signal, the tracking error of these parameters lies

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within 0.5'lo since switched-capacitor techniques are used. The resolution of theproposed on-chip spectrum-vector analyzer will be limited to 8 bits, which is easilyachievable using switched-capacitors techniques.

A conceptual schematic diagram of the proposed technique to characterize analogcircuits is shown in Fig. 2.7. It consists of a digital I'requency synthesizer, a switched-capacitor sinewave generator, two VGAs, a switched-capacitor bandpass filter and ananalog-to-digital converter. The system operates as follows: the frequency synthesizergenerates the master clock used as the sinusoidal generator sampling frequency as wellas the non-overlapping clock phases for the switched-capacitor blocks. The sinewavegenerator, based on switched-capacitor techniques, delivers a sinusoidal signal with afrequency of I/16 of the master clock frequency. The amplitude of the signal comingfrom the sinusoidal generator is adjustable to provide the proper level to the stimuli. Theoutput of the DUT is amplified/attenuated by the second VGA to accommodate it to theproper input range of both bandpass filter and ADC. The narrowband switched-capacitorfilter is a key building block of the spectrum-vector analyzer, its function is twofold:one, it can be centered at the center frequency f, to obtain the DUT transfer function;second, to select the proper frequency component (f2p, 3f) or harmonic distortioncharacterization. Finally, the ADC delivers the signal to a digital tester to be processed.The main advantage of this system is its inherent synchronization. The sinewavegenerator is based on switched-capacitor circuits, with an oscillating frequency equal tof, //6. The center frequency of the switched-capacitor filter, f0, can be precisely definedby both clock frequency and capacitor ratios as follows:

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where f, is the sampling frequency, Cr is the integrating capacitor and Cz is the switchingcapacitor. Capacitive ratios can be as precise as 0.1 rm Hence, adjusting the capacitorratios and the clock frequency, the bandpass filter's center &equency can be preciselydefined. Even more, given that the stimuli frequency and the filter center &equency aretracked to each other (since both are generated from the master clock), the system is self-synchroiuzed; when the stimuli &equency is changed by the frequency synthesizer, thefilter center &equency follows these adjustments.

Filter clocks

referenceclk Frequency

Synthesizer SmevraveGenerator

f,fsr Z'fo3 sf

Signal

VGA SystemUnder Test VGA

SC Bandpass FdterA/D

Converter

DSP, PC,Drgnal Tester

Fig. 2.7. On-chip spectrum/vector analyzer block diagram.

From the previous description, it can be noted that the blocks that conform the systemand their main properties are:

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~ Digital Frequency Synthesizer: Should be flexible and simple. Since the numberof frequencies to be generated is limited at 10, very simple digital circuitry can beused.

~ Sinewave Generator. A low distortion switched-capacitor oscillator (THD &50dB) is desired for this block. The digital circuitry used to control the switchesshould be as simple as possible.

~ Switched-Capacitor Bandpass Filter: A biquadratic implementation is used; itshould be precise, with low noise, low power and high g (50). The capacitor spreadneeds to be minimized to reduce silicon area.

~ Voltage Gain Amplifier: This is a programmable gain amplifier with anattenuation/gain range from -20 to 20 dB in 4 dB steps.

~ AnaloglDigital Converter: 8 bits resolution. Must be simple and cheap.

The particular specifications for these blocks will be discussed in the next section and inChapter III.

D. Specifications

In this section we will discuss the main design issues and the specifications for eachbuilihng block.

The first limitation to be considered is the distortion allowed in the sinewave generatorand bandpass filter. Since we are using switched-capacitor circuits, the limitation inresolution comes Irom the maximum capacitor mismatch, which could be around 0.1'/0.This error corresponds to a resolution of 10 bits. A tradeoff between accuracy, system

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robustness and implementation complexity takes us to limit the maximum resolution ofthe system to 8 bits. This value ensures a proper functionality of the test circuit underincreased capacitor mismatch conditions and also comes in hand with a limitedimplementation complexity.

A resolution of 8 bits corresponds to an error of 0.4 '/o (-48 dB), From the previous valuewe can set the distortion specification for both the bandpass filter and the sinewavegenerator. The third harmonic distortion is set to be I LSB below the resolution of thesystem, such that it is transparent to the ADC, yielding a value of 0.2 '/o (-54dB).

The distortion of the sinewave generator mainly depends on the number of steps used togenerate the sinusoidal waveform. If a small number of steps is chosen, the harmonicdistortion could be very high. Since the introduced harmonics are due to the samplingand hold nature of the signal, it is necessary to choose a number of steps that provides asmall number of harmonic components along with a small silicon area. If 8 points areused, the signal obtained can resemble a sinewave, but the number of harmonics can behigh. If we use 32 points, the signal will be purer, but the digital control logic increases(as well as the required silicon area) and there is not a significant improvement in theharmonic components compared with the one obtained using 16 steps. Therefore, thebest option is to use 16 points, which provides a reduced digital logic and therefore asmall area and a proper number ofharmonic components.

The quality of the harmonic distortion measurement is highly dependent on the quahtyfactor g of the BP filter. The higher the g, the more accurate the measurement of theharmonic distortion is. However a practical limit must be set for the quality factor of thefilter. The following approach sets a quantitative value for Q. For HD3 ~-54 dB, theattenuation Irom the center frequency fp to the third harmonic 3fp, yields to:

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~H(s) H(s)~, 4dB or iH(s) ' &0.005 (2.4)

The transfer function of a biquadratic bandpass filter is given by:

No SH(s) = NsS + S+NoQ

(2.5)

The transfer function of the filter is evaluated at frequencies, fo and 3fo and a Q thatsatisfies the following relation is calculated:

, &0.00564 Q'9

(2.6)

The required quality factor to provide an attenuation of -46 dB according to the previousequation is 75, which is extremely high for this application. Note that a high Q istranslated into a large capacitive spread or a higher order filter. Since one limitation forthis application is the use of a small silicon area, this value could be unacceptable. If a Qof 50 is assumed, the obtained attenuation is 0.00749 (around 2.5 dB). Even thoughthis attenuation is smaller than the original target, it provides a reasonable tradeoffbetween complexity and performance.

Another issue to consider is the center to sampling Irequency ratio fg lf, . This ratio can becalculated according to the number of harmonic components to be measured. Since thefilter transfer function repeats at f, /2 as a consequence of using switching techniques,and at least the third frequency component has to be measurable without any effect of

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the aliasing (see fig. 2.8). Using a ratio of p lf, = I/32 along with high Q, we can ensureno effect on the first 4 harmonic components.

/I

I/ 1/

p 2fp 3fp 4fp 3fo

fp= sf

6f 7fo fo fo 10fo

// 'I

I 1/I f, =16fo

2fp 3fp 4fp ifo 6fp fp o 1 fo o 12fo 13f 14f 15f 1 f(b)

Fig. 2.8. Center-to-sampling frequency relationship. (a)f, = 8 f, (b)f, = J6 f,Also, the frequency range where the proposed on-chip spectrum analyzer can operate hasto be evaluated. In order to avoid the hard constrain that a high frequency design impliesand since we want to probe the proposed principles only, this particular implementationis set in the frequency range from 1 kHz to 10 kHz, Therefore a Gain-Bandwidth product(GBW) of 1 MHz for the operanonal transconductance amplifiers (opamps) is proposed.Finally, we have to set the number of frequency steps generated in order to obtain ameasurement that allows deciding if the DUT is working within the specifications. Sincethe main ob)ective is just to measure the most important frequencies of the transferfunction of the DUT, we set up to 10 different &equencies: &om 1 kHz to 10 kHz in 1kHz steps which can be achievable using a simple digital &equency synthesizer.

The most important system specifications are given in table 2.1.

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Table 2.1.Target specifications for the On-Chip network/spectrum analyzer.

Specs

Harmonic Distortion(Sinewave Generator)

On-ChipNetwork Spectrum

Analyzer&-54 dB

Harmonic(Randpass Filter)

Distortion &-42 83()uality Factor Q(Randpass Filter)Center to SamplingFrequency Redo (fJfjFrequency RangeFrequency Resolution

&50

161 kHz-10 kHz

1-10kHz in 1 kHz steps

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CHAPTER IIIBASIC BUILDING BLOCKS

A. Introduction

The blocks to be used in this project were defined on the previous chapter. All of themuse switched-capacitor techniques in order to assure the self-synchronization of thesystem. In this chapter, the main design issues are thscussed.

B. Sinewave GeneratorThe purpose of this block is to generate the stimuli to be applied to the system under test.Several approaches for generating sinewave signals have been reported [14-16]. n manyapplications, sinusoidal signals can be generated using digital circuitry and a Digital toAnalog Converter (DAC). The signal to be generated is sampled in several points andthe obtained values are stored in a Read-Only Memory (ROM) and translated into ananalog signal to be applied to the Device Under Test (DUT). Even though the signalsobtained using this technique have very low distortion and are very accurate when theDAC and the ROM (or PEA) are added up, the resulting area is quite large. Since wedesire a small area, a simpler but efficient approach has to be used.

Fig. 3.1 shows the schematic diagram of the sinewave generator proposed in this work. Itconsists of a programmable gain amplifier whose preset gain stages correspond to thevalues of an ideal sampled and held sinewave. The amplifier has 4 different gain stages,which generate a sinusoidal output with 16 steps per period. The switch PZ sets the zeroof the sinusoidal waveform. The switches PAI to through PDl are closed sequentiallywith each clock cycle to generate the first quarter-period of the sinusoidal waveform. .

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Once the maximum values is obtained, the switches close in the opposite direction (fromPDI to PA1) in order to generate the second quart-period. In the second zero crossing,PI,switches from V, to Vpr so the lower half of the signal is generated. Theadvantage of this implementation against direct digital synthesizers lies in the simplicityof the logic, resulting in a very compact implementation.

PDI CIPD2

J PC2PBI

PV,~

-P

j B2PBI

g PA2 Voot

Fig. 3.1. Variable gain amplifier used to generate the sinewave.

An important issue on the design of the sinusoidal generator is the control logic for theswitches. Particular attention needs to be taken in generating non-overlapping phases foreach control signal to avoid errors in the generation of the sinewave. Fig. 3.2 shows thelogic used to control the switches of the sinusoidal generator. It is composed of a 5-bitbi-directional shift register with clear and preset. The control signals generated by theshift register are multiplied by the non-overlapping phases f& and f~ that control theswitches of the bandpass filter. In order to obtain a full cycle, 16 clock cycles arerequired. Fig. 3.3 shows the switching sequence obtained using this logic. Fig. 3.4 showsthe simulated results for both the control signals and the sinusoidal output.

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4

0Ik 0,

QP

0Ik Q.Ik

DIk Q,

P

D0 00 0Ik2

Ik

f, A 8 8 f, C I D f. Z f A, C 8 f, 0

PAI, PBI, PCI PDI PZI PA' PD PIZ PI2,

P 11 PBI PCI PDI PZI PA PDI ICI Pl 'Fig. 3.2. Logic control for the sinewave generator.

time 0 I 4 I 5 6 8 9 le I I 12 '13 '14 15PZ

PDPC

PBIPAI

Fig. 3.3. Output sequence for the logic.

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Sinewave Generator Responses

2.6 Pz88

-2.2,888.82,888.8288.8

2.8

88.8

pet

Pat

, Pet

PA1

: trout588m8 8

-588 588u 1. m 1 em 28mtime ( s 1 2 em 2 em

Fig. 3.4 Simulated control signals and output of the sinewave generator.

This implementation has several advantages. As stated above, the logic is very simpleand provides a compact implementation. The sinusoidal signal is generated using adigital clock, which makes its frequency very precise and controllable and sinceswitched-capacitor techniques are used, the synchronization with the bandpass filter isensured. Since this circuit uses just one operational amplifier, a very compact structureresults.

One of the most important characteristics of the circuit is that it should have a very lowharmonic distortion to be able to measure properly the DUT. The main limitations of thisblock are due to the finite parameters of the operational amplifier and clock feed-through

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effects. The maximum operation frequency is given by the maximum frequency at whichthe opamp can work. A rule of thumb for switched capacitor circuits is that themaximum frequency is limited by the gain-bandwidth product according to:

f, =BW(Hz)2n10 (3.1)Since the sinewave is generated using 16 points, the output trequency vs. clockfrequency is ratio 1/16. This ratio provides a good trade-off between implementationcomplexity and harmonic distortion. The maximum resolution that is achieved whenswitched-capacitor techniques are used is 8 bits; therefore, a HD3 less than -46 dB isenough.

From Fig. 2.7, we can see that the amplitude of the sinusoidal generator output isadjusted by a VGA to provide a proper level of the stimuli to be applied to the deviceunder test (DUT). From Fig. 3.1, it can be noted that the amphtude of the sinusoidalsignal is determmed by the reference voltage + V,A therefore, the use of the VGA shownin Fig. 2.7 can be avoided and the amplitude of the sinusoidal signal is controlled withthe magnitude of the reference voltage. The values of the capacitors used in the sinewavegenerator are calculated according to:

C,= Sin(90')C, C,' = Sm(67.5')C,= Sm(45')C, ' = Sin(22.5')C,

The minimum capacitor C4 is set to 2 pF. Table 3.1 shows the final values of thecapacitors

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Table 3.1. Capacitor values for the sinewave generator.Cr 5.22 F Cr 4.83 pFC9 3.7 F C4 2 FCs 5 22 F C(ops 20 97

C. Bandpass FilterAnother critical building block of this system is the bandpass filter. As stated in ChapterII, a high quality factor is required in order to perform the harmonic distortionmeasurement fmm the DUT. Due to the important role played by the filter in the system,special care must be taken in its design.

The harmonic distortion measurement will set the specifications for the quality factor ofthe filter. First, the quality factor should be high enough to select the frequencycomponent to be measured and attenuate other components. This is graphically depictedon Fig. 3.5. Consider a bandpass filter with a high quality factor (Q). When measuringthe fundamental component, all harmonic components should be attenuated and the onlycomponent amplified is fp, but when an harmonic distortion measurement at 2 fp is made,the amplitude of the fundamental should be attenuated in such way that its magnitude ismuch smaller than the one at 2 f0 it should be attenuated at least -46 dB. The sameapplies for the measurement of 3fp, where the component at 2fp should be attenuatedmeanwhile the one at 3fp should be passed. Lets consider now a bandpass filter with awider bandwidth (low g) like the one shown in Fig. 3.5(b). We can see that when ameasurement of the second harmonic is performed, the amplitude of the fundamental isconsiderably large, sometimes even larger than the second harmonic when the filter isnot precisely centered. As we can see, the effect of Q is more critical for the second andthird harmonic distortion characterization.

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2f 3fo Frequency

2f 3fFrequencyFrequency

e 2"o 3& Frequency

o

L

o o Frequency

2t;, 3j, Frequency

o o Frequency

2 o 3 o Frequency

Fig. 3.5. Quality factor effects in the selection of the harmonic distortion component. (a)High g (b) Low Q.A second issue to consider is the precision of the filter's center &equency. A smalldeviation of the center frequency can lead to incorrect measurements as shown in Fig.

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3.6. Consider, for instance, the measurement of the fundamental; it can be noted that ifthe center frequency of this filter deviates from the desired frequency, this component isattenuated while the second harmonic is less attenuated than we expected. This effect iseven more severe when high Q filters are used. Both magnitude and harmonic distortionmeasurements are sensitive to these errors.

f; t,+af2(, 3fo Frequency

fo 2$ 3 f, Frequencyf.= if+sf

o o o Frequency

f,= 3f+sf

o 2fo o Frequency

Fig. 3.6. Effect of the accuracy of the center frequency on fundamental, second and thirdharmonic measurements.

From the previous discussion, the need of implementing a bandpass filter with a highquality factor, accurate center &equency synchronized with the incoming signal is amust. The first problem implies the use of a large capacitor ratio to achieve a high g; theneed of a small area requires the use of an alternative technique to reduce the capacitivespread. The second problem can be solved using a very precise approximation: in thiscase, a predistorted bilinear transformation is the best choice.

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Since the system is intended for on-chip testing, the silicon area required by the filtershould be minimized, preventing the use of a high order filter. A second order switched-capacitor filter using the bilinear approximation is employed. Even though the bilinearapproximation yields a more complex implementation than the forward or the backwardapproximations, it is preferred because it provides better accuracy and move attenuationof higher frequencies due to the zero located at f/2.The specifications to be met are the following:

~ f, lf, =1/32~ Q =50

Fig. 3.7 shows the bandpass filter implementafion, and Fig. 3.8 shows its correspondingblock diagram.

C~lC,

C

OUi

Fig. 3.7. Switched-capacitor bandpass filter.

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C, z'C, 1 '

CzCi 1-z '

C, 1Ci 1

V

C, 1C, 1 '

C,C,

Fig. 3.8. Block diagram for the switched-capacitor bandpass filter.The bilinear bandpass transfer function is given by:

-2H( )=A z'+a ='+b (3 3)and the transfer function of the block diagram shown in Fig. 3.8 is:

2

H(z)2 z 11

(3.4)

By comparing both the bilinear and filter transfer functions (equations 3.3 and 3.4), wecan find the required values for the capacitors. These values are summarized on table 3.2for a unity peak gain reahzation. The minimum capacitor is set to 0.2 pF. A detaileddesign of this filter can be found in appendix A.

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Table 3.2. Capacitor values for the SC bandpass filter.Cs 02 F Cr 5116 FCs 10.04 F Cs 51.16 FCg 10.04 F Cs 1.02 FC 0.2 F Croiag 123 82 F

From table 3.2 it can be seen that the capacitor spread is very large (1:250).Notice thatthe smallest capacitors are Cg and Cs, those that connol the quality factor and the peakgain of the filter. For high g, the capacitance spread becomes exnemely large. The largecapacitive spread implies many problems in the design of the filter. First, the largespread means a large silicon area and increased power consumption. Second, themismatch between the capacitors is also increased.

A method that allows to reduce the capacitive spread while maintaining the high g of thefilter is needed [17].The associated resistance of the switched-capacitor Co is given by:

1A CQ (3 5)

where f, is the sampling fiequency and Cti is the capacitor that emulates the resistor. Ifwe decrease f, by a factor n, then the eqmvalent resistance increases by the same factorn as follows:

1 nf/ C f Co (3.6)Since the obtained equivalent resistance is n times larger than the original R,~, and thetime constant (R, C&) of the integrator must be maintained, then the integratingcapacitor C& should be scaled down by the same factor n, effectively reducing the

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capacitance spread by a factor n. Using this technique, an effective reduction in thecapacitive spread can be obtained without sacrificing the filter's performance.

Table 3.3 shows the new values of the capacitors for n =4. It can be noted that thesevalues are much smaller than the original ones, leading to a capacitive spread of I:64.Furthermore, if the minimum capacitance is reduced to 0.1 pF, the absolute value of allcapacitors is also reduced. The final capacitor values are given on table 3.4.

Table 3.3.New capacitor values for the SC bandpass filter.Cs 0.2 pF Cz 12.78 FC2 2.5 F Cs 12.78 FCq 2.5 F Cs 1.02pFC 0.2 F Croppy( 31. 8 F

Table 3.4. Final capacitor values for the SC bandpass filter.Co 0.1 pF Ci 6.3 FCs 1. 5 pF Cs 6.3 FCv 1. 5 pF Cs 0.51 pFC 0.1 F Cr, ~ 15.99 pF

Figure 3.8 shows the implementation of the described technique.

1' CQ 1'

72Vin

COC1

C3

Voulcs

Fig. 3.9. Bandpass filter with additional samplingIrequencyin Cg. (fi' = 'l4. fi andfz'='l~ fz).

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Fig. 3.9 shows the modified schematic. The filter was simulated in Switcap. Fig. 3.10shows a comparison of the bandpass filter when the capacitive spread reductiontechnique is used. Since the effective Q is increased by factor 4, the peak gain increasesby the same factor, as can be seen on Fig. 3.10, since the input capacitance Ct) was notadjusted. For unity gain filters, both CF) and Cs must be scaled down properly. Fig. 3.11shows the simulated output of the filter for a 5 mV input signal at 1 Khz.

ste it ta

10

estusqes st)ter

's, t" qtt 0 1~ nng tqoo sana)ang sequent)caUnng one sang)ltng gequency

-10

-10

-30

5(q) No) 100) 3000Fmqqqrtto Fn)

Fig. 3.10. Switcap simulation for the filter.

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58m

Bandpass FilterTransient Response

28m18m-48m8m

78m48m1 8m

8m-58m 32m 38mtime ( s ) 48m 42m 44m

Fig. 3.11.Simulated time response for the bandpass filter.

D. Voltage Gain Amplifier (VGA)Another important block is the variable gain amplifier. The VGA accommodates theamplitude of the signal coming from the bandpass filter to cover the complete dynamicrange of the ADC and to avoid a reduction in resolution due to a small input signal. Forthis application, amplification factors in 4 dB steps ar p p . 'g,ro osed. Fi . 3.12 shows the

u Cchematic of the VGA. The VGA is a capacitive amplifier with capacitors Cq throughsetting the desired gain and conuolled by switches D through H. It is important for theVGA to have an offset compensation scheme in order to avoid the introduction of errorsdue to the finite gain of the amplifier and dc offsets. The offset compensation schemeworks as follows: during phase 2, the input capacitors Cq and C7 sample the offsetvoltage while C6 holds the output; during phase I, the polarity of C7 is reversed and the

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measured stored offset voltage is subtracted from the input voltage plus the offsetvoltage [18].The capacitor values are given in table 3.5.

p C6

o C3

1Vin o C1

J c7vout

Ct

Fig. 3.12. Variable gain amplifier.Table 3.5. Capacitor values for the VGA.

C6

0.34 pF0.2 F05 F1.241 F0.2 F

CrCgCyCt~&

0.34 pF0315 F0792 F034 F4.268 F

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E. Operational AmpiiTier (Opamp)This section deals with the design of the opamp. The specifications to be met by theopamp are based on the features required by the filter because this is the block with morestringent constrains.

In order to determine the minimum gain of the opamp, consider the follovnng:

IP A (3 7)

where s is the maximum accuracy error permissible, P is the feedback factor equal to0.5 and A is the opamp dc gain. For an error of I'/w we have that the minimum dc gainshould be 200.

The gain-bandwidth product GBW is determined by the maximum sampling frequencyas follows:

GBW &10 f,Then, for a 32 kHz sampling frequency, the minimum GWB should be 320 kHz.

(3.8)

The load capacitor is estimated adding all the capacitors that will be connected at theoutput of the opamp in each clock cycle, which will be at most 10 pF.Form the previous discussion, we can set the design specifications for the opamp:

~ A, & 200 (46 dB).~ GBW & I MHz.~ Ct = 10pF.

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Fig. 3.13 shows the schematic of the opamp. It consists of a differential pair (Mq-Mz) andthree current mirrors (Mq-Ms) with a cascode output stage (M6c-Msq). The designprocedure is described in appendix B.The final transistor sizes are given in table 3.6.

Voo

M, M4 M4 M4

IbM4c

V

Msc

M, 4

M4

~ssFigure 3.13.Opamp schematic.

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Table 3.6. Sizes for the opamp transistors.Trdrrtsistor

Mn Ms 5,528'(pm) L(~)

13.2 1.3.86 4.8 1.2

MsrMsrsMa Mdc 3.86 4.8 1.Mn Mg, MacMn Mitt

1.3162.63

1.623.3

1.21.2

F. Analog-to-Digital ConverterEven though this block is not being implemented on this chip and an external ADC willbe used, it is important to discuss some issues about its design. An implementation thatis fast enough, compact and provides enough resolution is presented.

For this purpose, an algorithmic ADC can be used [19-20].A block diagram of theconverter is shown in Fig. 3.14. This structure works in a similar way as the successive-approximation converter, but in this case, the remaining voltage is doubled instead ofbeing halved, and the reference voltage is unchanged. This provides a quick conversiontime and a moderate circuit complexity.

Vm0 Trackaod Hold V,V,

ComparatorSenalOutput

X Va ~vm /2

Fig. 3.14. Block diagram of the algorithmic A/D converter.

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The conversion is made as follows: first, the input signal is sampled by a track and holdcircuit and then passed to a comparator. If the comparator input signal, V, is larger thanthe reference voltage V,, the corresponding bit is set to 1, otherwise, it is set to 0.Depending on the value assigned to this bit, a voltage V,s, 2 is added (if the bit is 0) orsubtracted (if the bit is I) to V,. This process is repeated until the desired number of bitsis obtained. As we can see, this converter requires small area because it reuses the samecircuitry to perform the conversion. The whole process is summanzed in Fig. 3.15,where the flow graph for the algorithmic approach is presented.

Qs~.

V&=v, otVot )[Btt=1

i V=2(V-V ,2) V=2(V+V j2)I=i+i

No i&N

Vo. QStop

Fig. 3.15. Flow graph for the algorithmic approach.

One of the most cntical blocks in this architecture is the multiplier by two. The errorintroduced by this block should be minimized in order to reduce errors in the final resultof the conversion. As we know, the ratio of the input and output capacitors will give us

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the gain, but because of the nature of the fabrication process, a mismatch in their sizescan be generated. Therefore, we need to find a way to reduce the error introduced by thispossible mismatch.

A common source of error is the offset generated by the opamp due to its finite gain andtransistor mismatches. The use of techniques using switched capacitors help us to reducethis error.

The architecture used in the multiplier by two is shown in Fig. 3.16(a) [21]. t consists ofan opamp, two capacitors and seven switches. The circuit works as follows: This circuitrequires seven different phases, which are shown in Fig. 3.16(b). In the first period, theinput voltage is sampled in Ci as well as the input offset voltage; in the second one, thecharged stored in Ci is transferred to Cz. In the third period, the input is sampled againand Cz is floating, so it holds the charge transferred in the previous stage. Finally, in thefourth penod, the charges from Ci and Cz are combined in Ci and are present at theoutput. As we can see, the final value of the multiplication does not depend on thecapacitor matching, but in the number of integrations made. Fig. 3.17 shows the circuitconfiguration for each phase.In the next chapter, simulation and experimental results for each block and the completesystem vtdll be discussed.

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bv. ~ JCI

V

(a) (b)2 I 3

Fig. 3.16. (a) Schematic of the multiplier by two. (b) Phases.

a CbVinn J

aX

Vout

a CVfn n

Vout

Phase 1

a CI&Vtn n

Vout

a CbVinW J

Vout

Phase 3 Phase 4Fig. 3.17. Multipher by two: circuit configuratton for each phase.

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B. Sinewave GeneratorAs stated in the previous chapter, the purpose of this block is to generate the stimuli tobe applied to the system under test. Figure 4.2 shows the simulated results for thesinewave generator wtth a 500 mV reference voltage. Since the amplitude of the outputwaveform is proportional to V,, it can be adjusted to provide the proper amplitude.Table 4.1 shows the simulated and measured results for the spectrum at fa 2f0, and 3f0for a reference voltage of+ 50 mV and an output frequency of 1 kHz.

688m8.M

MmFig. 4.2. Simulated output of the sinewave generator.

Table 4.1. Simulated and experimental results for the harmonic components of thesinewave generator for Vf=50 mV.

2 p3Simulated-74.61 dBc-64.02 dBc-90.29 dBc-59.08 dBc

3feasured- 66.31 dBc-51.09 dBc-70.92 dBc-53.24 dBc

Figure 4.3 shows the transient response of the sinewave generator. This plot shows thesignal for three different reference voltages: +200 mV, +100 mV and +50 mV. Theoscillating frequency is 1 kHz

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%+V/8v.

ir I ttII

1

3I

I-W 4'

I

It *M-+- + I "I""4-,II

'I

titf4--k-

I II i

tIf

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Betet 88 &)2 Taaet NBSB NtttRCE 8: Cht BeeetrunA Bffstt

08tr- 1,088 d8

.10d8

/dt's

-100dBJt 8'tg 'tt 0 Ht Btedt 10 kdt

ete: IPHS-82 faetex 6$83P. N1 000, Ht -89 888 88tt/Nt

-180dde/BB

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The rms value for the 200 mV~ input signal is given by:Vp 200m VV,(rms) = = 141. 2m V,, (4.1)

From Fig. 4.5, the noise power measured (in dBm) in the bandwidth of interest is givenby:P = 59.26+10 log(BW) (4.2)

where BW is the filter bandwidth at 1 kHz, which is 6 Hz. Then:P = 59.26+10 log(6) = 9.26+ 7.78 = 1. 7 dBm

The rms power is given by:(4 3)

(P51. 7dBm =10 log[ J m P, = 7.55n W,ll gJ (4 4)normalizing to a 50 D resistor:

V, =JP, 0=~7, 55 10' (50i=614"10' (4.5)The dynamic range is given by:

DB =20 log, " * =47.247dB141. 2m V,6.14x10 'V, (4.6)Table 4.2 shows a summary of these measurements.

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Table 4.2 Sinewave generator measurements summary.Spec Value

D3 51 dB (Fig. 4.4)cise 47 dBc at

kHz (Fig. 4.5)ynamic range 7.25 dBaximum input

eltage00 mVp

C. Bandpass FilterAs discussed before, the most critial block of the system is the bandpass filter. A veryprecise center frequency and high quahty factor are required to provide a reliablecharacterization of the device under test. Some of this specs were measured and arediscussed on this section.

Fig. 4.6 shows the filter transfer function. The sampling frequency is 32 kHZ (1 kHzcenter trequency) and the sampling f'requency for C0 is 8 kHz (see Fig. 3.9). Themeasured quality factor is around 380.

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4tH 8P~Z'f&Z Tice. fZ".N PNRACK Sg.F~m keepensakit" 1 003.$$ R Hg

4t '

Af)V

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Fig. 4.8 shows the filter peak gain measured from 1 kHz to 9 kHz. It can be seen that itfollows an almost constant value up to 8 kHz; after this value, the error increases due tothe limited GBW of the opamp. Ifa higher frequency operation is desired, then the GBWof the opamp should be increased. In Fig. 4.9 the quality factor of the filter from I kHzto 9 kHz is shown. The value moves between 380 and 420, but this is mainly due tomeasurement errors. A behavior similar to the one achieved in Fig. 4.8 is expected.

39 5

38 5

38nl'or 375

u- 3736 5

35 51000 2000 3000 4000 500D 60DO TDOD 800D 9000Center frnquencyfo fHz)

Fig. 4.8. Gain for the bandpass filter.560540520500

ty 490rr 460

4408420

400380

4

3601000 2000 3000 4000 5000 6000 TDOO 8000 900DCenterfrequencyfo)Ht)

Fig. 4.9 Quality factor for the bandpass filter.

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Iate: 08-38HZ, Vice'. 84 % PN

-t55. @N' 'C&ater '

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YRRCK' R' CHR Irttt4 HzrkzrIHrHRHHHz

IC118/div

',I IHIHHMtrHz Czniart I HHz

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(4.11)

The signal to noise ratio is given by:SNR =20 log ', =84.17dBIII 322x10-'V (4.12)

Table 4.3 shows a summary of these results.Table 4.3 Bandpass filter measurements summary.

Spec Value

cise1'

-75 dB (Fig. 4.10)13.228 ltVrmsFig. 4.1I)84 dB

uxituutu iuputaltagerequeucy rauge

302.6 Vp1 kHz kHz

D. Voltage Gain Amplifier (VGA)

The VGA is used aAer the signal has been filtered by the bandpass filter. In this case,gain steps of 4 dB each are used. Fig. 4.12 shows the response of the VGA for 5different gains: 0, 8 12, 16 and 20 dB when a sinusoidal signal of 1 kHz and +80 mVamplitude is applied. Fig. 4.13 shows the error between the ideal and the measuredvalues. It can be noted that the obtained results have a gain error below 0.25 dB.

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t I

Yw-~-*" -s.f +wT

jI

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RACE Rg $2 PS8-RS888/HX

8 AS 8 Hx -137 817 de Hz

ORHQR I

18 !CIR/III Y .

818PI IC . HR

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CHAPTER V

CONCLUSIONSIntegrated circuits are becoming more complex as the featured size decreases. This trendallows us to implement more functions on a single chip, making them more prone to fail.Usually, each analog circuit requires a "custom made" testing circuit. Then, the need offinding a umversal test technique for analog circuits is a must.

This work deals with some of the many problems that analog testing engineers find veryoften. Some of the goals to achieve are to use an external digital tester instead of theanalog or mixed-signal tester to reduce the test nme as well as facilitate the test programgeneration. An important issue to consider is the silicon area used for the testing circuit,since it should not represent a large area overhead for the whole circuit. Also, the testingcircuit should not interfere with the DUT performance when it is working in normalmode.

With these purposes in mind, an on-chip spectrum/vector analyzer for built-in testing ofanalog ICs has been proposed. The idea behind this work is based on the most populartest techniques: spectrum and network analyzers. Using this approach there is not needto reconfigure the DUT. Since one of the most critical issues to solve is synchronization,the use of switched capacitor techniques is a must, where a high accuracy and robustnesscan be achieved and the synchronization between all the blocks is ensured.

In order to probe the main ideas of this work, several blocks were designed: a sinewavegenerator, a high-g bandpass filter and a voltage gam amplifier (VGA). An analog-to-digital converter can be added, but it is not included in this system. All of these blocksuse switched-capacitor techniques to ensure synchronization.

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The required features for the sinewave generator included a dynamic range larger than45 dB, center frequency and amplitude programmabihty as well as synchronization withall the other blocks. The sinusoidal signal is obtained by using 16 samples of an idealsinewave and since its amplitude is set by a reference voltage and can provide the properdynamic range for the DUT, the input VGA was removed. The proposed architecturerequires a very simple digital logic to control the step sizes of the sinusoidal signal andsince it requires one operational amplifier only, a very compact implementation results.

The bandpass filter was the block with more constrains. Since a high quality factor and avery precise center frequency are a must, special care has to be taken in its design. Thefirst issue was solving using a predistorted bilinear transformation; The high qualityfactor yield to a very high capacitive spread, but this can be reduced by using a differentsampling frequency (fin) for the capacitor that controls the Q of the filter: in order tokeep the same time constant, the equivalent resistance is increased, reducing thecapacitor spread by the same factor (n).

The voltage gain amplifier is used to provide a proper dynamic range to the ADC, aswell as to avoid a reduction in resolution due to small input signals. For this purpose, avariable gain amplifier with six gain steps of 4 dB each (from zero to 20 dB) is used. Thestructure used is offset and gain compensated in order to reduce the introduction oferrors due to the dc offset and finite gain of the opamp. The gain is set externallyaccording to the desired level.

The complete system was fabricated through the MOSIS service, using the AMI 0.5 )imCMOS process. The silicon required for the on-chip spectrum/vector analyzer was750pmx550tim. Experimental results has been presented and summarized in Chapter III.

In summary, a compact on-chip spectrum/vector analyzer using SC techniques has beenproposed, where the signal generation is made using the digital clock and a frequency

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synthesizer. Magnitude and phase characterization and harmonic distortion of the DUTcan be measured. Since switched-capacitor techniques are being used, fullsynchronization of the system is achieved and the precision obtained can be as low as

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REFERENCES

[I] G.W. Roberts, "Metrics, Techniques and New Developments in Mixed-SignalTesting", Tutorial presented at the International Test Conference 1999, IEEEComputer Society, Atlantic City, N.J. September 26-October I, 1999.

[2] G.W. Roberts, "Metric and Techniques of Mixed-Signal Testing: AnInnoduction", presented in the Analog and Mixed-Signal Testing Short Course,Texas A&M University, College Station, November 13-17,2000.

[3]A. Rueda, "Analog and Mixed-Signal Testing", presented in the Analog andMixed-Signa! Testing Short Course, Texas A&M University, College Station,Tx. November 13-17,2000.

[4] B. Provost, "Design Methodologyfor Mixed-Signal AC BIST and ADC Self-Cahbration" Ph.D. Dissertation, Texas A&M University, May 2002.

[5] B. Dufort, G.W. Roberts, "On-Chip Analog Signal Generator for Mixed-SignalBuilt-in-Self Test", Proceedings of the IEEE 1998, Custom Integrated CircuitsConference, Santa Clara, California, USA. , 1998.

[6] J. M. Byrd, F. Caspers, "Spectrum and Network Analyzers", Joint US-CERV-Japan-Russia Particle Accelerators School on Beam Measurement, Mountreux,Switzerland, 11-20May 1998.

[7] J. Cowles and B. Gilbert, "A Cahbrated RF/IF Monolithic Vector Analyzer",2001 IEEE MTT-S Microwave Symposium Digest, Vol. 3, Phoenix, Arizona, pp.2163-2161,2001.

[8] L. T. Lin, FL Tseng, D. Cox, S. S. Viglione, D. P. Conrad and R. G. Runge, "AMonolithic Audio Spectrum Analyzer", IEEE Journal of Solid State Circuits,Vol. SC-18, No. I, pp.40-45, February 1983.

[9) Y. Kuraishi, K. Nakayama, Z. Miyadera and T. Okamura, "A Single-Ship 20-Channel Speech Specmim Analyzer Using a Multiplexed Switched-CapacitorFilter Bank", IEEE Journal of Solid State Circuits, Vol. SC-19, No. 6, pp. 964-970, December 1984.

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[10]J. S. Chang, Y.C. Tong, "A Micropower-Compatible Time Multiplexed SCSpeech Spectrum Analyzer Design", IEEE Journal of Solid State Circuits, Vol.28, No. I, pp. 40-48, January 1993.

[11]R.Courteau, T. K. Bose, "A High-Precision RF Vector Analyzer Based onSynchronous Sampling", IEEE Transactions on Instrumentation andMeasurement, Vol. 43, No. 2, pp. 306-310,April 1994.

[12] HP 3588A Getting Started Guide, Hewlett-Packard Company, Everett, WA. ,March 1990.

[13]L. Chan, A Continuous Short Time Founer Transform Spectruni Analyzer: AProject Report, Texas A&M University, Department of Electrical Engineering,October 1995.

[14]G. Boarin, G. Chiappano, F. Maloberti, S. Napolitano, M. Porta, "VLSIImplementation of the Metering Signal Generator for Switching System AnalogTerminations", IEEE, Personal collection of M. G. Mendez Rivers, 1990.

[15]J. Silva-Martinez, E. Sanchez-Sinencio, "Excess Phase-Jitter CancellationMethod for SC Relaxation Oscillators", IEEE Transactions on Circuits andSystems, Vol. CAS-34, No. 6, pp. 695-700, June 1987.

[16]H.C. Patangia, B. Zenone, "A Programmable Switched-Capacitor SinewaveGenerator", Proceedings of the 37th Midwest Symposium on Circuits andSystems, IEEE, Vol, 1, pp. 165-168, 1994.

[17]J. L. Ausin, J. F. Duque-Carrillo, G. Torelli, E, Sanchez-Sinencio, F. Malobern."Penodical Nonuniform Individually Sampled Switched-Capacitor Circuits",ISCAS 2000-IEEE International Symposium on Circuits and Systems, Geneva,Switzerland, pp. 449-452, May 2000.

[18]S. Nagaraj, "A Parasitic-Insensitive Area-Efficient Approach to Realizing Verylarge Time Constants in Switched-Capacitor Circuits", IEEE Transactions onCircuits and Systems, Vol. 36, No. 9,pp. 1210-1216,September 1989.

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[19]P.W. Li, M. J. Chin, P. R. Gray and R. Castello, "A Ratio IndependentAlgorithmic Analog-to-Digital Conversion Technique", IEEE Journal of SohdState Circuits, Vol. 19, pp. 828-836, December 1984.

[20]R. H. McCharles, V.A. Saletore, W. C. Black Jr. and D. A. Hodges, "AnAlgorithmic Analog-to-Digital Converter", IEEE International Solid StateCircuits Conference, Philadelphia, February 1975.

[21]A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley& Sons Inc. ,New York, NY, 1997.

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APPENDIX

A. Bandpass Filter DesignIn Chapter III we discussed the filter architecture to be used. A second order bandpassfilter using swtiched-capacitors and a bilinear approximation is proposed. Thespecifications to be met are the following:

~ f, =1kHz~ f, = 32 kHz m (T, = 31.25x10-6 s.)~ g =50~ HD3 ( 42 dB

The charactenstic transfer function of a bandpass filter is given by:

where ra, is given by

I')s + +co (A. 1)

ra. =2 rr f, =2 rr (1000)=628318x10' rad(sec (A.2)In order to simplify the calculations, we will use the previous equation in the followingform:

H(s) = s'+a s+b (A.3)

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where a and b are given by:

628318 10'a == ' = 125.6637061 rad / secg 50b = m, =(6.28318x10') = 39.478x10'rad/sec

(A.4)

In the other side, we know that the bandwidth of the filter can be found with thefollowing equation:

N ai, 6.28318x10'(7= ' mBW= = = 125.6637 rad /sec = 20HzBW Q 50 (A.5)As we know, a very precise aproximation is needed in order to obtain the desired centerfrequency; hence the bilineal transformation is used. The transfer function in the z-domain for this case, is obtained using the following equation:

2 I 'S=T I+z' (A.6)After some algebraic manipulation, we end up with the following result:

-2H(z) =2 a T. b.T' a T+4 z '+ 2 b T z '+ b T'+2 a T+4 (A7)Now, we will apply the prewarping for the bilinear transformation as follows

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For the central frequency of 1 kHz and a sampling frequency of32 KHz:

2 ( 6.28318x10' 31.25x10 'CrP , tan31. 5 x10 2m = 6.30345 x10'rad/sec =1. 032252 Hz

(A.9)

And the new values of the constants a and b are:a = 126.0689963b = 39.73347x106

Substituting the values of a and b in the z-domain transfer function and aAer somealgebra, we obtain:

H(c) = 6.419x10 '. z ' .8596 ' +1. 1284 (A.10)The previous transfer function is compared with the block diagram of the switched-capacitors implementation in order to obtain the capacitor values required. Theimplementation of the circuit and the block diagram is given in figure A. l and A.2respectively.

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c C 2 C 2V,,C

Fig. A. l. Switched-capacitor bandpass filter.

C z'C, i-z-'

CzC, i='

V,C, 1C, iz' C, iC, i-z-'

C,C,

Fig. A.2. Block diagram for the switched-capacitor bandpass filter.

The transfer function of the block diagram is:

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C, 1-z' C, C, 1-z'

" (-'):::((-'- ) (A. 1 1)And after some algebra:

C4 C5 r Co C4 C5 ) CoH(z) C, C3 Ci Ci C3 C,z'+ ' " z'+ 1+ (A. 12)

or

(Co 'Ci f ] Co 'C~H(z)

4(A.13)

By comparing both the block diagram and the filter transfer functions, we can easily findthe required values for the capacitors. The obtained values summarized on table 3.1 arecalculated form the following relationships:

C, C,C4 C,

C, =C,and C, =C4 (A. 14)

The final results are given in Chapter III section B.

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B. Operational Amplifier (Opamp)The operational amplifier is a common element is all the block of the system proposed inthis work. The specs to comply are:

~ 3=200 (46 dB).~ GBW=I MHz.~ Cr = 10 pF.

Figure Bl shows the schematic of the opamp. It consists of a differential pair and threecurrent mirrors with cascode stage output. The design procedure is carried out next.

M4 M4 M4

IbM4c

Msc

Mio

M, M4

Figure B. . Opamp schematic.

The parameters for the AMI 0.5 pm process are:

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~ V,=0.79VVip =0,93 V

~ K=114.6x10 A/V~ K~ = 38x10 A/V

First, we need to know what is the minimum required bias current so the opamp worksproperly.

1'4' Visas ' CLt, (B.1)

where Vqu is fixed to 50 mV because we are using a cascode structure and we need toensure there is enough room to keep all the transistors in the saturation region. t, is thetime require to ensure a proper charging and discharging of Cz. After some calculations,we find that the minimum current required is around 0.720 iiA . Hence, we can fix thiscurrent to a higher value in order to get more gain. A bias current of 8 liA can be used.

The g required for the differential pair in order to charge the capacitive load in 4.r isgiven by:

16*C,gmci = (B. )

With this equation, we can easily find the sizes of transistors M& and Mi. Using:

L, 2 K ID (B. )

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For transistors Ms and Mq, we fix Vq,and calculate the transconductance using:

2 Is"34 Vdsof3, 4and the sizes of transistors M3 and M~. Using:

(B4)

L, 2 K ID (B.S)For a mirronng current of 1 in Ms and M6.

(B.6)

The cascode transistors Mi c and M6i- have the same sizes as M5 and M6.

The gain of the opamp is related to the minimum length of transistor M6 which is givenby:

1x10 ' 3 ID6 g~i Vs (B.7)

Even though the Early Voltage V,~ does not have an exact value, it gives a goodapproach to a good value for this transistor length.

For M5 and Mrs

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Finally, for transistors M9 and Mns we fix Vd,,and calculate the transconductance using:2. IDgmz4 = Vaoa4 (B.9)

and the sizes of transistors M9 and Mns Using:

L, 2 K. o (B.10)The final transistor sizes are given on table B.

Table B. . Sizes for the opamp transistors.TransistorMn MtM3, M4

5.523.86

8'(Ian)13.24.8

L(tom)1.21.2

Ms, MiGMa Msc 3.86 4.8 1.Mz Mg, MscMy, Mts

1.3162.63

1.623.3

1.21.2

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C. Abbreviations and AcronymsError

ADC:Ave

Analog-to-Digital ConverterDC gain

BIST: Built-in self testingCr.r Load capacitanceclkr ClockDAC: Digital-to Analog ConverterDFTr Desig for testabilityDUT: Device under testfor Center frequency

Sampling frequency

GBP't Gain-Bandwidth productHD3:IC:IF:LO:LSB:

Third harmonic distortionIntegrated circuitIntermediate frequencyLocal oscillatorLeast significant bit

Opampt Operational amplifierProgrammable Logic ArrayQuality factor

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R88'r Resolution bandwidthRFr Radio frequencyROM: Read-Only MemorySTr Sweeping timeTHDr Total harmonic distortionVCOr Voltage controlled oscillatorVGA: Voltage gain amplifierV.e'er Reference voltage

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VITA

Marcia Gisela Mendez Rivers was born in Irapuato, Guanajuato Mexico in 1972. Shereceived the B.E. degree in electronics Irom the Universidad de Guanajuato, Mexico andthe M.S. degree in Electronics in the Instituto Nacional de Astrofisica, Optics yElectronics (INAOE) in 1996 and 1998 respectively. She received the M.S. degree inelectrical engineering from Texas A&M University in the Analog and Mixed SignalCenter in 2002. She is working towards her Ph.D. degree in Electronics in the InstitutoNacional de Astrofisica, Optics y Electronics. During her studies at INAOE she workedon clock recovery circuits. Her current interests are analog testing and switched-capacitors systems. Her permanent address is Otono 772, Las Reynas, Irapuato,Guanajuato, Mexico, 33660.