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AS-Chap. 5 - 1
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Chapter 5
Digital Electronics
AS-Chap. 5 - 2
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Fast (< 100 GHz)
Low-power (aJ / gate)
Requires cooling
Not yet established technology
Requires new periphery (power supply, packaging, ...)
5.1 Superconductivity and Digital Electronics
Potential Advantages and Disadvantages
AS-Chap. 5 - 3
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The Cryotron (1956)
IcontrIgate Icontr
Igate
0 1
(a) (b)
5.1.1 Historical Development
Operating principle: superconducting-normal transition in wireControl line has higher critical magnetic fieldControl line switches enough current to control another gate LogicMemory: trap flux ±𝛷 in loop, read/write via sc-normal transitionInferior to semiconductor devices (low switching speed 𝜏𝐿𝑅 ≃ 10 ns)
AS-Chap. 5 - 4
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The Josephson Switch (1966, Matisoo, IBM)
Icontr
Igate
0 1
Icontr
Igate
0 1
5.1.1 Historical Development
Sub-ns switching times Clock speeds up to 1GHzControl Flux quantum as natural bitStrong shielding and controlled trapping of residual flux requiredUnderdamped Pb junctions Large 𝐼c-spread, vulnerable to thermal cycling
IBM stops efforts in 1983
Increase 𝜏𝐿𝑅 by switching JJ or SQUID instead of sc wire Josephson cryotron
AS-Chap. 5 - 5
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Rapid Single Flux Quantum (RSFQ) Logic (1985, Likharev, Nakajima)
5.1.1 Historical Development
Operating principle: Non-latching logic with overdamped Nb-JJSlightly above 𝐼c ps current pulsesPhase difference evolves by 2𝜋 during pulseUse resulting voltage pulses for logic circuits
1978 First RSFQ gate (T-flip-flop) proposed
Fast (record so far: 770GHz clock speed)Intrinsic memoryLow power consumtionReproducible fabrication possible
Fabrication still demandingNo transistor-like superconducting devices with high gain
High fan-out difficult Small parameter spread required
AS-Chap. 5 - 6
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5.1.1 Historical Development
Rapid Single Flux Quantum (RSFQ) Logic (1985, Likharev, Nakajima)
AS-Chap. 5 - 7
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10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-12
10-11
10-10
10-9
10-8
10-7
ga
te d
ela
y (
s)
power dissipation / gate (W)
5.1.2 Advantages of Josephson Switching Devices
Fast
(For 106 switching elements)
Low power
AS-Chap. 5 - 8
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Matched superconducting striplines for onchip wiring (fast, low dissipation)
Junction technology available (Nb based)
5.1.2 Advantages of Josephson Switching Devices
𝑍 ≃ 10 Ω close to JJ resistance for width 𝑊 ≃ 1 μmLittle dispersion up to 1 THz Transfer of ps pulses OKDense layout with little crosstalk possible
AS-Chap. 5 - 9
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𝐼c
𝐼
𝑉2Δ/𝑒
𝐼gate
IgateIcontrIL
Ic LsRJ(V) C RL
5.2 The voltage state Josephson logic
Underdamped JJ as switching gates Zero and finite voltage state as 0 an 1 Natural emulation of semiconductior logic
Initially: 𝐼gate < 𝐼c
𝐼contr + 𝐼gate > 𝐼c Switching
Load 𝑅L ≪ 𝑅sg All current transferred to load after switching
AS-Chap. 5 - 10
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Characteristic Times (linearized LCR circuit)
5.2.1 Operation Principle and Switching Times
Switching time limited by 𝜏𝑅𝐶
Geometric mean
Underdamped junction for switching logic
AS-Chap. 5 - 14
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5.2.2 Power Dissipation
Nb junction for RSFQ (already high damping)
Compare tosemiconductingdevices & HTSL
AS-Chap. 5 - 15
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Voltage state logic Underdamped JJ
1. Latching nature requires to switch off bias current
Global clock system at GHz frequecies required
2. Ac power source required
JJ biased with ac current source Shapiro steps JJ may switch back to step voltage instead of zero
Bipolar operation JJ may switch through to negative voltage branch „Punchthrough“ Intrinsic feature of Josephson physics Limits clock speed to a few GHz
No speed gain over semiconductor technology!
5.2.3 Global Clock, Punchthrough
AS-Chap. 5 - 16
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5.2.4 Josephson Logic Gates
General requirements
IgateIcontrIL
Ic LsRJ(V) C RL
High fan-out Single gate should trigger multiple consequtive gates
Large parameter margins Stable operation
Small size Very large scale integration
Short gate times High clock frequency Requires fast switching
Low power dissipation High integration density
Input-output isolation Directional logic Difficult in switching gates Not satisfied by simple circuit shown before!
AS-Chap. 5 - 25
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5.2.4 Josephson Logic Gates
Speed not due to gate type, but due to junction technology(typical gate speed for Nb technology)
Performance (see lecture notes for details)
AS-Chap. 5 - 26
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General typesNDRO: Non-Destructive Read-OutDRO: Destructive Read-Out
Speed requirementsOrder of CPU speed
Natural physical quantitypersistent currents / magnetic flux in sc.loops„0“: no flux in the loop„1“: finite flux in the loop (usually 𝛷0)
AccessRead/write JJ-based gates
5.2.5 Memory Cells
General definitions and requirements
AS-Chap. 5 - 27
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NDRO memory Igate
Iwrite Iwrite
L/2 L/2
readIc3
Ic Ic
5.2.5 Memory Cells
Dc-SQUID geometry
WRITE operationFinite bias 𝐼gate No flux coupled into loop at 𝐼write = 0 Increase 𝐼write such that induced shielding current 𝐼sh > 𝐼cTurn off Iwrite Flux remaines trapped for 𝛽𝐿 > 1
READ operationJJ3 biased slightly below 𝐼c3„0“ state No circulating current No switching of JJ3
„1“ state Circulating current suppresses 𝐼c3 Switching of JJ3
Does not alter cell state
AS-Chap. 5 - 29
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5.2.5 Memory Cells
Still inadequate for most applications (too big)1996 an 8.5 × 11.5 μm2 chip (1 Mb/cm2) demonstrated(Compare: 2016 Samsung 3D NAND flash185 Gb/cm2)
Performance
AS-Chap. 5 - 34
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5.2.6 Microprocessors
Performance
AS-Chap. 5 - 35
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5.2.6 Problems of Underdamped Junction Logic
Underdamped junction logic gates and memory Josephson microprocessors werebuilt
Problems preventing their practical use
Pb technology too unreliable Solved with Nb technology
Latching logicAc power supply and global timing requiredSpeed < 1GHz due to punchthroughSwitching back to zero voltage state slow (~1ns)
No transistor-like amplifying 3-terminal device
AS-Chap. 5 - 36
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Specific properties of RSFQ logic
5.3 RSFQ Logic
Acronym for rapid single flux quantum logic
Clock frequencies above 100 GHz Fast!
Nonlatching logic
Overdamped Josephson junctions
Low power consumption 𝑃diss𝜏 ≃ 10−18J
bit
AS-Chap. 5 - 37
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Ic
I
VIcRL
Igate
Igate + Icontr
V
t 00
0
10
IgateIcontr IL
Ic Ls RL
Ic
I
V2D/e
Igate
Igate + Icontr
0
1
0
5.3 RSFQ Logic
Switching vs. RSFQ logic
Latching„0“ „1“ fast„1“ „0“ slow
Not competitivewith semiconductor-based logic
Nonlatching„0“ no SFQ emitted„1“ SFQ emitted
Significantly fasterthan semiconductor-based logic
SFQ pulses can be naturally generated, reproduced, amplified, memorized andprocessed with overdamped Josephson junctions!
AS-Chap. 5 - 38
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Ic
I
VIcRL
Igate
Igate + Icontr
V
t 00
0
10
5.3 RSFQ Logic
Dynamic SFQ circuits
Static SFQ circuits
Information passed as dc flux/supercurrent Limited integration, requires rf power supply/clock Practical limitations!
Information passed ballistically between devicesInterconnectsMicostrip (passive) or Josephson transmission lines (active)
AS-Chap. 5 - 39
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Time averaged voltage2𝜋
Total current must be constant (neglecting the fluctuation source)
and
𝐼 > 𝐼c Part of the current as 𝐼N or 𝐼D Finite junction voltage 𝑉 > 0 Time varying 𝐼s 𝐼N + 𝐼D varies in time Time varying voltage Sinusoidal or non-sinusoidal oscillations of 𝐼s
Oscillation frequency 𝑓 =ℎ 𝑉
𝛷0
T: oscillation period
5.3 RSFQ Logic
Repetiton: Voltage state of overdamped JJ
RSFQ pulse
AS-Chap. 5 - 40
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-1.0
-0.5
0.0
0.5
1.0
I s (t)
/ I
c
0 10 20 30 40 500.0
0.5
1.0
1.5
2.0
V(t
) /
I cR
t / c
5.3.1 Basic Components of RSFQ Circuits
Generation of RSFQ pulses – single JJ
Igate
Icontr IL
Ic Ls
R=(1/RN+1/RL)
-1
Bias overdamped JJ sightly above 𝐼c Pulse duration Φ0/2IcR ≈1 ps for IcR ≈ IcRN ≈ 1mV Nb JJ intrinsically underdamped Shunt resitance Pulses longer & less high Single pulse with few-ps control pulse Demanding
No control pulse RSFQ pulse train Natural clock
AS-Chap. 5 - 41
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5.3.1 Basic Components of RSFQ Circuits
Generation of RSFQ pulses – rf SQUID
Icontr
0 tpulse reset
I1
I2
Vout
0 t
Ism
0 Icontr
``0” ``1”Igate
I1I2
SFQout
Vout
Igate
L
J1
J2
rampin
Icontr
Replace overdamped JJ by rf SQUID with 3 ≲ 𝛽𝐿,rf ≲ 10 Hysteretic behavior 0 → 1-transition at 𝐼contr = 𝐼1 1 → 0-transition at 𝐼contr = 𝐼2
RSFQ pulse again generated with dc current pulsePulse can be longer at cost of decreased amplitudePulse train can be generated with external RF clock
AS-Chap. 5 - 42
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5.3.1 Basic Components of RSFQ Circuits
Dc-to-SFQ converter
L2
SFQout
J2
J1
dcin
Igate
Vout
L1
L3J3
Advanced version of rf SQUID type RSFQ pulse generator Igate > Ihigh J3 enters voltage state
RSFQ pulse & 3-JJ interferometerswitched into different flux state
Reset: Igate < Ilow
Sequential 2𝜋 phase jumps in J1 and J2
Accompanied by RSFQ pulse generationacross J1 and J2
Circuit also requires only a dc input signal
𝐼gate not too far from 𝐼c RSFQ pulse triggered by short control pulse Generation circuits can bring area of slightly damped RFSQ pulse back to 𝛷0
(„reproduction“) Moderate voltage gain
Pulse reproduction and amplification
AS-Chap. 5 - 43
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Josephson transmission line (JTL)
Igate,1
J1 J2 J3
Igate,2 Igate,3
L1 L2 L3A B
5.3.1 Basic Components of RSFQ Circuits
Reciprocal device
Exactly 1 fluxon localized at sinlge junction 𝐿𝑛 ≃ 𝛷0/𝐼c
SFQ pulse incident at A Trigger consecutive 2𝜋 phase jumps in junctions Fluxon propagates towards B
5 ps-pulse & 1 cm line length No noticable attenuation
Amplification 𝐼c,𝑛 should grow & 𝐼c,𝑛 decrease accordingly in propagation direction
AS-Chap. 5 - 44
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Buffer stage
Pulse splitter
J1
L1A
J2
L2
J3
L3
B
C
Igate,1
Igate,2
Igate,3
J2
Igate
BJ1
L2A
L1
5.3.1 Basic Components of RSFQ Circuits
Reciprocal device Symmetric with repsect to
all three ports
Evident generalization of JTL
Reproduction capability used
Provides isolation
J1 and J2 dc-biased below their critical currents 𝐼c1 < 𝐼c2
SFQ pulse incident on port A 2𝜋 phase shift at J2
SFQ pulse output at B
SFQ pulse incident on port B 2𝜋 phase shift at J1
No output at port A
AS-Chap. 5 - 45
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J1 J2
Igate
L
FLS
LR
JS
JR
S
R
LF
0 1
Icirc
Ism
IS
``0” ``1”
Igate
IR
SFQ Memory cell: RS flip-flop register (DRO register)
5.3.1 Basic Components of RSFQ Circuits
Dc SQUID with 𝛽𝐿 ≃ 3 and two JJ-buffered input lines
Information stored as quantized flux trapped inside the loop
Proper parameters and bias Incoming SFQ pulse at port S (set) triggers flux trapping („0 → 1“-transition) Incoming SFQ pulse at port R triggers reset („1 → 0“-transition) JR and JS protect input from setting(resetting) a 1(0) state During reset, a readout pulse is emitted at port F
Operating principle similar to latching (flipflop) logic
High-density RAM possible, but not implemented yet (effort, resources)
AS-Chap. 5 - 46
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S1
S2
S3
Sn
Sout
V(t)
t
S1
S2
Sout
``0”
``1”
T
T
´
5.3.2 Information in RSFQ Logic
Concept of elementary cells or timed gates (Likharev)
Each cell Two or more stable flux states & signal RSFQ pulses S1, S2, …
Clock generates additional timing line T Sets cell to initial state „1“ at the beginning of every clock period Possibly generates output pulse Sout at the end of every clock period
Logical „0“ and „1“ Absence and presence of RSFQ pulse during time 𝜏 in line Si
AS-Chap. 5 - 47
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RSFQ OR gate
J1 J2
Igate,2 L
CLS
LR
JS
JRTL3
0 1
Icirc
A
B
Igate,1JA
JB
5.3.3 Basic Logic Gates
Confluence buffer connected to RS flip-Flop
Initial clock pulse resets the memory to 0
One SFQ pulse enters either A or B memory cell switches to in state 1
Pulses in A and B First pulse switches memory to 1, second pulse does nothing
Clock pulse at the end Resets memory and generates output pulse if in state 1
AS-Chap. 5 - 48
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J1 J2
Igate,A L
LS
LR
JS
JRT
0 1
Icirc
J1 J2
Igate,B L
LS
LR
JS
JRTL3
0 1
Icirc
B
AL3
JA
JB
JC
C
Igate,C
RSFQ AND gate
5.3.3 Basic Logic Gates
Initial clock pulse resets the memories to 0
If two SFQ pulse enters A or B at different timesMemory cells for storage
Next clock trigger Reset memories and release stored pulses simultanelously
Jc switches only if two pulses add Only then SFQ pulse released at port C
Two RS flip-flops at theinputs of a confluencebuffer
AS-Chap. 5 - 49
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J1 J2
Igate
L
OUT
LS
LR
JS
JR
IN
T
0 1
Icirc
J3
RSFQ NOT gate
5.3.3 Basic Logic Gates
Initial clock pulse resets the memory to 0
If no pulse (state 0) enters at port IN J2 carries virtually no current Next trigger T pulse switches J3 Output of SFQ pulse (state 1)
If a pulse (state 1) enters at port IN Stored in memory, increiasing current through J2 Next trigger pulse T switches J2 and not J3 No output of SFQ pulse (state 0)
AS-Chap. 5 - 50
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0 1
Icirc
Igate
0 1
Icirc
Igate
0 1
Icirc
Igate
0 1
Icirc
Igate
T
OUTIN
RSFQ shift register
5.3.3 Basic Logic Gates
Upper array acts as JTL transmittion trigger/reset pulses from port IN
First in first out (FIFO) memory
AS-Chap. 5 - 51
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SimulationMaximum delay ≃ 6𝜋𝜏𝑅𝐿
Overdamped Josephson junctions < 1
5.3.5 Maximum Speed of RSFQ Logic
3 μm technology 2𝜋𝜏𝑅𝐿 ≃ 3 ps Clock speed ≃ 100 GHz
Submicron technology Clock speed ≃ 500 GHz
AS-Chap. 5 - 52
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But: power dissipation mainly determined by dissipation in biasiresistors
𝑃diss ≃ 1μW
gate
5.3.6 Power Dissipation
AS-Chap. 5 - 53
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Applications of RSFQ logic
5.3.7 Prospects of RSFQ
Cryogenic electronics for control and readoutof superconducting quantum circuits forquantum information
many ??
AS-Chap. 5 - 54
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5.3.7 Prospects of RSFQ
AS-Chap. 5 - 55
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Pseudo random bit generator, operated up to 17 GHz
5.3.7 Prospects of RSFQ
AS-Chap. 5 - 57
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PetaFLOPS Scale Computing: Speed and Power Scales (Year 2006)
Semiconductors (CMOS)
Performance: > 100K chips @<10 GFLOPS each
Power: >150 W per chip total >15 MW
Footprint: >30x30 m2
Latency >3 ms
Superconductors (RSFQ)
Performance: 4K processors @ 256 GFLOPS each
Power: 0.05 W per PE nodetotal 250 W @ 5 K(100 kW @ 300 K)
Footprint: 1x1 m2
Latency 20 ns
K. K. Likharev, SUNY Stony Brook
5.3.7 Prospects of RSFQ
AS-Chap. 5 - 58
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K. K. Likharev, SUNY Stony Brook
5.3.8 Fabrication Technology
AS-Chap. 5 - 59
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1 THz
HTS RSFQ (??)
100 GHz 30M JJ
3M JJ 0.4 mm
300K JJ 0.8 mm
10K JJ 1.5 mm
3.5 mm
10 GHz 0.05 mm
0.07 mm
0.10 mm
0.12 mm
0.14 mm
0.20 mm
1 GHz
"no known solutions"
optical lithography
100 MHz
1995 1998 2001 2004 2007 2010
Year
RSFQ ROADMAP(VLSI circuit clock frequency)
RSFQ (Stony Brook Forecast)
CMOS (SIA Forecast 1997)
LTS RSFQ
5.3.9 RSFQ Roadmap
________________________
Stony Brook____________________________________________
AS-Chap. 5 - 60
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𝑥 𝑡
0
𝑥 𝑡𝑘
𝑡0
123
4
5
6
𝑇 𝑡𝑘
𝑦 m
Fundamental task
𝑛-bit ADC allows for 𝑘 = 2𝑛 discrete values Real signals are noisy (Electronic noise, white quantization noise)
Effective bit number 𝑛eff < 𝑛 Equivalently expressed in terms of least significant bit LSB ≡ 𝑛 − 𝑛eff Other equivalent measures: Signal-to noise- ratio (SNR), dynamic range
Superconductor Flux quantization Accuracy of 𝛷0/2
Convert analog signal 𝑥 𝑡 into an integer-valued signal 𝑦m 𝑡𝑘 = 𝑦m 𝑘𝑇 with k discrete points
5.4 Analog-to-Digital Converters
AS-Chap. 5 - 61
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𝑥min
𝑥max
𝑥
0
2𝑛 − 1
𝑦
Analog-to digital conversion process
0 1 2 3 4 5 6 70
1
2
3
4
5
6
7
analog input
dig
ital
ou
tpu
t, e
rro
r
Input signal
Output signal
Quantization error
Mapping of the inputsignal onto the availablerange of digits
5.4.1 Foundations of ADCs
AS-Chap. 5 - 62
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Claude Elwood Shannon Harry Nyquist
5.4.1 Foundations of ADCs
AS-Chap. 5 - 63
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Shannon-Nyquist theoremMust sample at twice the maximum signal frequency
Two fundamental types of ADCs
Sample with Nyquist frequency and many bits (Nyquist sampling) Sample with too high rate & only one bit & digital postprocessing (Oversampling)
Separate signal and samplig frequency!
5.4.1 Foundations of ADCs
AS-Chap. 5 - 64
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outSref
Sin
JQL
Icirc
SinVout
Isens
JQ
L
Icirc
SinVout
JS
LSin
Vout
JQ
RL
RB
Compares analog input signal to reference 0 if smaller, 1 if larger
Semiconductor
High-gain amplifier with clipped output
Superconductor
Use flux quantization Compare to max. supercurrent Input < 𝐼c No output pulse Input > 𝐼c SFQ pulse
Other Configurations (see lecture notes)
Quasi-one-junction comparator(sense 𝐼circ instead of SFQ pulses)
Voltage-to-frequency quantizer(pulse rate ∝ signal amplitude)
5.4.2 The Comparator
AS-Chap. 5 - 65
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Igate
𝑳/𝟐
Icirc
OUT-
JQ2JQ1
OUT+
𝑳/𝟐
Ism
0 Iin
-Igate
+ - + - +- + - +
Incremental quantizer
Dc SQUID configuration
Double slit (periodic) characteristic Count threshold passage in + and – direction (flux quanta enering or leaving
the loop) with separate counters OUT+ and OUT- Determine incremental change in + or - direction from counting rates Promises high linearity In practice limited by stray magnetic flux suppressing the critical currents
Sin
5.4.2 The Comparator
AS-Chap. 5 - 66
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offset
input Comparatorclock
offset
input Comparatorclock
offset
input Comparatorclock
offset
input Comparatorclock
offset
input Comparatorclock
R
R
R
R
R
R
2R
2R
2R
2R
2R
S/2
S/4
S/8
S/16
S/32
offset
clockanalogsignalS
D0 (MSB)
D1
D2
D3
D4 (LSB)
Flash ADC (Nyquist type)Fast, but small number of bits
5.4.4 Different Types of ADCs
AS-Chap. 5 - 67
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time
anal
og
sign
alVCO
f = V/F0
gate
counter
Gat
e co
ntr
ol
analoginput
digitaloutput
VC
O
ou
tpu
tga
teco
ntr
ol
pu
lse
s to
co
un
ter
time
time
time
pass
block
Tt
Counting Converters Based on voltage-to-frequency conversionQuantization and sampling separatedSampling performed by counting SFQ pulses
Single JJ
SFQ pulse rate ∝ Signal amplitude
5.4.4 Different Types of ADCs
AS-Chap. 5 - 68
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5.5 Prospects of Superconducting ADCs
