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©2000 Addison Wesley A basic ARM memory system ROM D[7:0] ROM D[7:0] ROM D[7:0] ROM D[7:0] SRAM D[7:0] SRAM D[7:0] SRAM D[7:0] SRAM control D[7:0] D[31:0] D[31:24] D[23:16] D[15:8] D[7:0] A[n+2:2] A[n+2:2] A[n+2:2] A[n+2:2] A[m+2:2] A[m+2:2] A[m+2:2] A[m+2:2] RAMoe RAMwe3 RAMwe2 RAMwe1 RAMwe0 ROM0e ARM D[31:0] A[31:0]

©2000 Addison Wesley A basic ARM memory system. ©2000 Addison Wesley Simple ARM memory system control logic

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©2000 Addison Wesley

A basic ARM memory system

ROM

D[7:0]

ROM

D[7:0]

ROM

D[7:0]

ROM

D[7:0]

SRAM

D[7:0]

SRAM

D[7:0]

SRAM

D[7:0]

SRAM

control

D[7:0]

D[31:0] D[31:24] D[23:16] D[15:8] D[7:0]

A[n+2:2] A[n+2:2] A[n+2:2] A[n+2:2]

A[m+2:2] A[m+2:2] A[m+2:2] A[m+2:2]

RAMoe

RAMwe3 RAMwe2 RAMwe1 RAMwe0

ROM0e

ARM

D[31:0]

A[31:0]

©2000 Addison Wesley

Simple ARM memory system control logic

RAMwe0

RAMwe1

RAMwe2

RAMwe3

mclk

A[0] A[1]mas[0] mas[1]

RAMoe

ROMoe

A[31]

r/w

©2000 Addison Wesley

ROM wait control state transition diagram

ROM RAM

resetfast

ROM2 ROM3ROM1

©2000 Addison Wesley

ROM wait state generator circuit

ROMoeA[31]

r/w

D Q

wait

reset

D Q

mclk

ROM3

ROM

D Qen

D Qen

wait1

wait2

©2000 Addison Wesley

The timing diagram for the ROM wait state logic

mclk

A[31:0]

wait

wait1

wait2

ROM0e

fast ROM1 ROM2 ROM3

©2000 Addison Wesley

State transition diagram with a wait state for address decoding

ROMseq

reset

RAMRAM

mreq seq

ROM2 ROM3ROM1

decode

©2000 Addison Wesley

DRAM memory organization

ras

cas

A[n:0]

dataout

array ofmemory

cells

mux

©2000 Addison Wesley

ARM address register structure

incrementer

from/to PC in register bank

from ALU

exceptionvector

address to memory seq signal(address + 4)

address mux

©2000 Addison Wesley

DRAM timing illustration

mclk

A[31:0]

seq

wait

ras

cas

A A+4 A+8

S cycle S cycleN cycle

D[31:0]

©2000 Addison Wesley

DRAM timing after an internal cycle

mclk

A[31:0]

seq

mreq

ras

cas

A A+4

S cycle S cycleI or C cycle

©2000 Addison Wesley

A typical AMBA-based system

externalbus

interface

ARMcore/CPU

on-chipRAM

bridge

APB

AHB or ASB

test i/f ctrl

DMAcontroller

parallel i/f

timer

UART

©2000 Addison Wesley

AHB multiplexed bus scheme

decoder

address

wri

teda

ta

readdata

master3

master2

master1

arbiter

slave3

slave2

slave1

©2000 Addison Wesley

Rapid Silicon Prototyping principle

reference chip final chip design

Rapid Silicon Prototyping system

FPGAs

unused

resynthesis

©2000 Addison Wesley

JTAG boundary scan organization

core

logic

TAPcontroller

device ID reg

bypass reg

instruction reg

in

out

I/O

enable

in enable

TDI

TMS

TCK

TRST

TDO

©2000 Addison Wesley

Test Access Port (TAP) controller state transition

diagram

test logic reset

TMS = 1

TMS = 0

TMS = 0

capture DR capture IR

exit2 DR exit2 IR

update DR update IR

TMS = 0 TMS = 0

TMS = 0 TMS = 0

TMS = 1 TMS = 1

TMS = 0 TMS = 0

TMS = 1 TMS = 1

TMS = 1 TMS = 1

TMS = 0

shift DR

TMS = 0

shift IR

TMS = 0

pause DR

TMS = 0

pause IR

TMS = 1TMS = 1

TMS = 1TMS = 1

TMS = 1 TMS = 1

TMS = 0TMS = 0

TMS = 1 TMS = 0 TMS = 1 TMS = 0

TMS = 1run test/idle select IR scan

exit1 IRexit1 DR

select DR scan

©2000 Addison Wesley

A possible JTAG extension for macrocell testing

ARM macrocellDRAM control

custom logicvideo macrocellTAP

PCB test scan path

ARM test path

©2000 Addison Wesley

EmbeddedICE signal comparison logic

ARMsignal

value mask

othersignals

match

©2000 Addison Wesley

EmbeddedICE register mapping

Addres s Wi dth Funct i o n00000 3 Debug control00001 5 Debug status00100 6 Debug comms control register00101 32 Debug comms data register01000 32 Watchpoint 0 address value01001 32 Watchpoint 0 address mask01010 32 Watchpoint 0 data value01011 32 Watchpoint 0 data mask01100 9 Watchpoint 0 control value01101 8 Watchpoint 0 control mask10000 32 Watchpoint 1 address value10001 32 Watchpoint 1 address mask10010 32 Watchpoint 1 data value10011 32 Watchpoint 1 data mask10100 9 Watchpoint 1 control value10101 8 Watchpoint 1 control mask

©2000 Addison Wesley

EmbeddedICE register read and write structure

r/w address

decode

mask

compare

TDI TDO

update DR

breakpoint

value

03104

data

©2000 Addison Wesley

Real-timed debug system organization

EmbeddedICE

Trace por tanalyzer

ARMcore

Embeddedtrace

macrocell

EmbeddedICEJTAG TAPJTAGport

Traceport

hostsystem

System on chip

data

address

control

controller

©2000 Addison Wesley

Piccolo organization

ARM7TDMI

AMBA i/fAMBA i/f

deco

de

an

d co

ntr

ol

mult

I cache

registerbank

ALU

inputbuffer

outputbuffer

AMBA

©2000 Addison Wesley

ARM v5TE PSR format

N Z C V unused mode

31 28 27 26 8 7 6 5 4 0

I F TQ

©2000 Addison Wesley

Architecture v5TE multiply instruction binary encoding

cond 0 0 0 1 0 Rm

31 28 27 23 2221 20 19 16 15 12 11 8 7 4 3 0

1 y x 0RsRn/RdLoRd/RdHimul 0

©2000 Addison Wesley

Architecture v5TE add/subtract instruction binary encoding

cond 0 0 0 1 0 Rm

31 28 27 23 2221 20 19 16 15 12 11 8 7 4 3 0

0 1 0 10 0 0 0RdRnop 0