1

Out-panel Overview

• Crate-based (VME 9U) architecture.• 4 crates for entire MUID system:

– North Horizontal, North Vertical, South Horizontal, South Vertical

• 1 Front End Module (FEM) per crate communicates with PHENIX Online:– Serial Control

– Timing & Control

– Data Collector Modules (DCM)

2

Out-panel Overview - cont.

• 20 96-channel Readout Cards (ROCs) perform analog processing and communicate with LVL1.

• 20 Transition Cards (TCs) (1 per ROC) allow input signals to enter from backplane.

• Passthrough backplanes on P1 and P2 connect each TC to its ROC.

• Modified VME backplane for ROC/FEM communication, geographical addressing and power distribution.

3

FEM Crate

ROC

ROC

:::

20 ReadOut Cards(ROCs)

Serial Dataand Control

lines onbackplane

GLink to DCM (20 MHz)GLink from T&C (40 MHz)

Arcnet line

6 sets of 16 twisted-pairsfrom Iarocci tube panels

16

16 :

6 sets of 16 twisted-pairsfrom Iarocci tube panels

16

16 :

GLink to LVL1 (60 MHz)

GLink to LVL1 (60 MHz)

ControllerCard

4

Front of FEM Crate

ROC

CONTROL

ROC

ROC

5

FEM Crate Profile

DataFromPanels

Power Supply

P1

P2

P3

Transition cards

Electronics cards

Analog Data

Custom Digital Backplane

Fans

Digital Lemos

Analog Lemos

DCM Glink

T&C Glink

Arcnet

Trigger Glinks

6

/HALT

BCLK

FEM Block Diagram

Arc Addr/DataMode CLK

Xfer Mode (2)MP_dat (2)

5

GLinkTo DCM

GLinkXMITFIFO

ArcnetSubsystem

LVL1acceptBCLK

4xBCLKENDAT0

UserBit[2:0]ModeBits[7:0]Mode Enable

GLinkRCV

GLinkFrom T&C

P3 Backplane

FPGA

ARCnetserial line

Mode Bits (20)

LVL1_Acpt

Resets (4)Align bit

ROC Data

FEM Addr

16

5

/ALE

/ROC_DV/RD

GeographicAddress (6)

Data (16)

WR Clk & EN (2)

RD Clk & EN (2)

DataFormatter

Strobe, /CAV, /Dav

Data (16)

Mode Control

Address & RD Cntrl (7)

Front Panel

Serial Data (6) AddressDecode

PLD

CommandLines (7)

FPGA Program (6)

Tx Reset,Locked,

ED

Rx Reset,Stat0

Arcbus (10)

FPGA Program (6)

Data FormatterDiagnostic

FPGA

7

FEMs

• State machine for ROC/FEM communication:– Builds event header/trailer words.

– Cycles through ROCs, copying data into DCM FIFO:• 96 data bits per ROC

• Plus 16 bit beam clock counter to identify I/O errors

– FPGA implementation, simulated.

• State machine for T&C communication (mode control):– FPGA implementation, simulated.

8

FEMs - cont.• Self-tester to allow complete FEM testing in the

absence of full crate of ROCs.– FPGA implementation, schematics finished, simulated.

• Address decoder (identical for FEM and all ROCs) uses geographical address to direct serial control and data traffic on digital backplane.– CPLD implementation, simulated.

• ORCAD schematics in progress.• Stealing (working!) schematics from PC for ARCnet,

T&C and DCM links.

9

ROC Block Diagram

TriggerGLink

(60 MHz)

P2

P1{

{P3

analog data

{analog data

Backplane

16

1616

1616

1616

1616

1616

BCLK Board Resets (4)

/RD

LVL1_AcptAlign bit

sdin,rdback,slatch,sclk,

sdout,sreset

TTL GLinkCircuit

Mode CLK Xfer Mode (2)

MP_dat (2)/ALE

FEM Device Addr (5)Arcnet Addr/Data (5)

AddressDecode

PLD

Greset

EDLocked

Align bit

Trigger Data

6X BCLK

Geographic Address (6)

20

6

Receiver&

Threshold

Delay &Latch

FPGAs (6)and

Clockdelay

chips (12)

16

96

DataStoreFIFOs

(3)

TriggerFormatFPGA

Data 16

LVL1_Acpt

/DVData (16)

BCLK

FiveEventFIFOFPGA

96

SerialString &Pulser

6

28/HALT

FPGA Prog.

/RD/RD_EN

/DV

/RD_EN

5

AnalogMuxes (7)

Analog SpyOutput

Digital SpyOutput

96

Pulserlines

16

16

16

16

16

96

32

32

32

FIFO cntrl

6

10

ROCs

• 96-channel implementation:– Multiple of input cable size (6x16=96).

– Fits into single optical G-link connection to LVL1 (with 6*BMCLK multiplexing).

– Minimum #channels that simultaneously allows:• Horizontal/Vertical ROC segregation

• Standard (21-slot) VME crates

• Only 4 DCMs

11

ROCs - cont.

• Analog processing chain.• Supplemental diagnostics.• Serial control.• All FPGAs schematics in hand and simulated.• ORCAD schematics in progress.

12

ROCs: Analog Processing Chain - Receiver, Discriminator

• Differential Receiver– Prototype panel used amplification of 1 w/ Thresh = 40mV and

50/50 isobutane/CO2.

– Amplification of 3 chosen:• Optimize filtering and minimize “popcorn”

• As a hedge against possibility of smaller operating gas gain (lower isobutane concentration)

• Discriminator– Leading edge seen to be sufficient on prototype.

– Range: 12.5 - 500 mV (256 steps).

– Selectability every 4 channels.

13

ROCs: Analog Processing Chain - Variable Delay

• Pipeline nature of PHENIX DAQ leads to requirement that all signals arrive within one beam clock cycle (106 ns).

14

ROCs: Analog Processing Chain - Variable Delay - cont.

• Maximum gate width reduced to 90 ns by set/hold requirements.

• Further reduced to 80 ns by convolution with transmission time down length of LST.

• Failure to match T0 leads to 1% efficiency loss every 3 ns. Inefficiency vs. gate width for different

isobutane/CO2 ratios. Measurement is for a 2-pack at one longitudinal location.

15

ROCs: Analog Processing Chain - Variable Delay - cont.

Skew Source Granularity(# Channels)

Max t(ns)

ROC/FEM bus drivers 96 5

Flight time to different gaps 16 8

Different internal cable lengths 1 5

Different flight time to LSTs on a cable 1 5

Trace lengths 1 2

Insertion time 1 10

16

• Specification– 50ns dynamic range total (25ns w/i input cable)

– 4ns resolution

– 1ns precision

• Staged implementation– CPLD portion simulated

– Full circuit to be tested on 8-channel prototype

ROCs: Analog Processing Chain - Variable Delay - cont.

17

ROCs: Analog Processing Chain - Outputs

• LVL1 trigger:– 96-bit struck LST pattern.

– 6*BMCLK MUX (schematic from H. Skank) into optical G-link connection (1 per ROC on front panel).

• DCM:– Bit pattern from every beam crossing is strobed into 64-deep FIFO

to cover LVL1 latency.

– Data from events from valid LVL1 is strobed into 5-event-deep FIFO.

– Data from 5-event FIFO on each ROC is sent to DCM event FIFO on FEM.

18

ROCs - Supplemental Diagnostics

• Pulser– Selectable every four channels.

– Allows diagnostics w/o being connected to a detector.

• Spy MUXes– Analog MUX samples immediately after the receiver.

– Digital MUX samples immediately after the variable delay.

– Both allow looks at signals, one channel at a time.

– Both are channel-selectable via serial control.

– Both outputs drive 50 to front-panel LEMO connectors.

• Output Mask– Allows elimination of known bad channels.

– Allows arbitrary bit patterns, e.g., to test trigger algorithms.

19

ROCs - Serial Control

• Signal routing via address decoder CPLD identical to that described for the FEM.– Pulser select– MUX selects– Output mask select– Threshold DACs– Variable delay settings– FPGA programming

20

8-Channel ROC Prototype

• Will test analog processing chain through variable delay.

• Will test “final” layout of analog portion of board.

• NIM resident, currently being stuffed.

• Will be tested on full-scale prototype.