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Page 1: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented
Page 2: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

2 SoC • 2013 • www.altera.com/industrial

Helping You DifferentiateFrom factory and process automation to energy infrastructure and surveillance systems, your industrial products help improve our world. Your products have to be safe, reliable, adaptable, and built to last. At the same time, business success requires you act quickly in order to differentiate in a highly competitive market while driving down total cost.

With innovative programmable solutions from Altera at the heart of your industrial designs, you’re equipped to tackle the key challenges:

•Adaptingquicklyandcost-effectivelytoevolvingendmarketsandstandards

•Meetingdiverseandescalatingperformancerequirementsacrossproductlineswhilesimultaneously reducing system material and development costs

•Designingsystemsthatmeetrequirementsforsafety,quality,andreliabilityoververylongsystem deployment lifetimes

Meeting Challenges with Altera FPGAs and SoCs

Today’s FPGAs and SoCs from Altera offer unprecedented integration capabilities alongside inherent hardware and software flexibility and performance advantages. This silicon convergencedeliversapplication-classARM®Cortex™-A9processors,state-of-the-arttransceivers,andmemorycontrollersintegratedwithhigh-performanceprogrammablelogic fabric.

Theseplatformsenablethecost-effectiverealizationofcompleteindustrialapplicationssuchasdrives,solarinverters,programmablelogiccontrollers(PLCs),orcamera-basedsurveillance systems in a single device. Increased performance and integration of discrete devicescanreducebothmaterialanddevelopmentcosts.Standardizationonasingleplatform across product lines and adjacent applications can significantly reduce schedule and obsolescence risks. Productivity with advanced software and system development tools provide optimal partitioning and design reuse to reduce time to market and preserve development methodology investments.

Page 3: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

SoC • 2013 • www.altera.com/industrial 3

Industrial Automation – Motor ControlDeliveringadifferentiateddriveproductthatcanmeetevolvingneedsinahighlycompetitivemarketpresents you with several distinct challenges:

•IncreasingDSP-intensivecontrolalgorithmperformanceforenhancedsystemefficiencyandreliabilitywhile reducing overall material and development costs

•DesignflexibilitytomeetdiverseandevolvingrequirementsforIndustrialEthernet,powerelectronics,and sensor feedback

•Integratedfunctionalsafetycapabilitywithhighreliabilityandlong-termdeviceavailability

Toaccelerateyourtimetomarketandincreaseproductivity,ourMotorControlDevelopmentFrameworkletsyoueasilycreateintegrated,high-performancedrive-on-a-chipsystemswithourCyclone®VFPGAsand SoCs. The Framework comprises tools, software libraries, intellectual property (IP) cores, reference designs,anddevelopmentboards.OurmotorcontrolIPincludespulse-widthmodulation(PWM),analog-to-digital(ADC),anddigitalencoderinterfaces.Italsohasintegrated,customizablefield-orientedcontrol(FOC)drive-on-a-chipreferencedesignstosupportsingleandmultiaxishardwaresystems.

Benefits of Altera FPGAs in Motor Control Applications

•Meetthefullrangeofsystemperformancerequirementsbyusinghardwarecoprocessorstoaccelerateyour motor control algorithm

•Flexiblysupportvariedpowerelectronics,positionfeedbackencoders,andnewandupcomingIndustrialEthernetandlegacyfieldbuscommunicationinterfaces

•IncreaseproductivitywithsoftwaredesignflowstargetingintegratedARMCortex-A9andNios®IIprocessorsandmodel-baseddesignforDSPcoprocessors

•ReducetimetomarketanddevelopmentcostsoffunctionalsafetycompliancewithIEC61508-qualifieddesign tools, IP, and products

•LowertotalcostofownershipthroughintegratedSoCplatforms,providingopportunitiestodifferentiateon a single architecture with long device lifetimes that significantly reduce obsolescence risks

Drive-on-a-Chip for FPGA-Based Motor Control

IndustrialEthernet

ADC I/F

PositionEncoder I/F

FPGA/CPLDSafety DeviceSafety IP

Motor ControlAlgorithm

PHY

PHY

IGBTControl I/F Power

StageΣΔ A/DConverters

PLC/DCS with Safety

Cyclone® V FPGA

Encoder(s)

Multiple Motors

ARM®/Nios IIProcessor

Page 4: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

4 SoC • 2013 • www.altera.com/industrial

Industrial Automation - PLCs PLCarchitecturerequiressupportformultiplespecializedperipherals,backplanes,andothercustominterfaces, typically integrated using an FPGA. You have the option to develop your system using an Altera SoC with an integrated processor or an FPGA companion chip for your discrete processor.

Integrated Altera SoC Solution

You can reduce system power, cost, and board space by integrating your processor, FPGA, and other required functionality, such as peripherals, into our Altera SoC.

•RunthePLCapplicationsoftware,Ethernetmasterprotocolstack,andmotioncontrolsoftware ontheSoC’sdual-coreARMCortex-A9processor

•Implementmostperipherals,includingUSB,CAN,Ethernet,timersandUARTs,requiredbythe PLC system processor using the SoC’s hard processor system

•ImplementspecializedperipheralssuchasmultiportEthernetswitches,2D/3Dgraphicsengine, andTCP/IPoffloadusingtheFPGAfabric

SoCs Implemented as PLC-on-a-Chip

FPGA

HPSHPS I/O

HPSUSB OTG

(x2)(1)

64 KBRAM

DMA

Shared Multiport DDRSDRAM Controller(2)

DDR Memory Controller,x32 with ECC | 400 MHz

Most of theCommon Peripherals

JTAGDebug/Trace(1)

QSPI FlashController

NAND Flash(1) (2)

SD/SDIO/MMC(1)

I2C(x4)

CAN(x2)

GPIO

SPI(x2)

Timers(x11)

HPS toFPGA

FPGA toHPS

FPGAConfiguration

UART(x2)

Ethernet(x2)(1)

ARM Cortex-A9NEON/FPUL1 Cache

L2 Cache

ARM Cortex-A9NEON/FPUL1 Cache

Hard PCIe*

Hard MemoryController*

3.125-Gbps and5-Gbps Transceivers*

*Optional Configuration (1) Integrated DMA (2) Integrated ECC

Multiport Ethernet SwitchTCP/IP Offload

Motion Control SoftwareIndustrial Ethernet Protocol Stack (Master)

PLC Run-Time Application SoftwareRTOS – VxWorks, Linux RT, QNX Ethernet MACs

Page 5: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

SoC • 2013 • www.altera.com/industrial 5

FPGAs as a Companion Chip

Ifyourelyonadiscreteprocessor,youcanuseour28nmCycloneFPGAasacompanionchiptocost-effectivelyimplementIndustrialEthernetorfieldbusprotocols,custominterfaces, and peripherals for your PLC application processor, includingtheIntelATOMprocessor.

•Integratecontrolandgluelogicplusrelatedbridgingandcommunication devices using our FPGA’s high levels of integratedhardIPsuchasDDRmemorycontrollersand PCIExpress®(PCIe®)endpoint

•SimplifyPCIelinkbandwidthsharingbetweenmultipleperipherals using standard operating system (OS) software drivers with our FPGA’s unique PCIe endpoint multifunction hard IP

Benefits of Altera FPGAs and Altera SoCs for PLC Applications

•BuildasinglehardwareplatformforusewithdifferenttypesofPLCs

•Integratealltheprocessingunits,peripherals,andcustominterfacesinasingledevice,effectivelybuildingaPLC-on-a-chip

•Customizeacompletelyprogrammablecompanionchiptoyourfavoriteapplicationprocessor

•Acceleratetimetomarketbysupportingthelatestgenerationofinterfacestandardsinprogrammablelogic

•MinimizePCBspinsandfuture-proofyoursystemwithin-fieldupgradestotheFPGA

x86 Processor

PCle

FPGA

Visualization

Motion Control

Safety

Application Specific

GPIO Fieldbus

FPGAs as Companion Chips for Application Processor

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6 SoC • 2013 • www.altera.com/industrial

Industrial Ethernet WiththeneedtosupportmultiplevariantsofIndustrialEthernetprotocols,designingindustrialsystemscanbefarfrom simple. These protocols have to be implemented as a deeply embedded function to meet shrinking system cost, form factor, and power budgets. As you integrate the digital drive functions onto a single piece of silicon, the communicationprotocolisbecomingasmallfunctionimplementedaspartoftheentire“drive-on-chip”design.

To obtain IP protocols, you need to negotiate with differentvendors,payup-frontlicensingfees,andworry about tracking sales.

ByusingourFPGAswithanintegratedIndustrialEthernetfunctionandoursimplifiedlicensingstructure, you can support most of your required protocols and redirect your resources for a more cost-effectivedesign.

TomakeiteasierforyoutoimplementdifferentslaveIndustrialEthernetprotocolswiththesamehardware, weteamedwithSoftingIndustrialAutomationGmbH,theworldleaderinIndustrialEthernetIPprotocols. ThecombinationofourFPGAandasecurityCPLDprovidesaneasyandinexpensivewayforyoutodevelopIndustrialEthernetandfieldbusconnectivityplatformswith:

•Nolicensenegotiation

•Noup-frontlicensingcosts

•Noper-unitroyaltyreporting

Moving from Modules to Devices to an Integrated Chip Function

Easy-to-Use Two-Chip Solution with “No-Hassle” Licensing

SecurityCPLD

Slave ProtocolsProfinet RT/IRTEthernet POWERLINKModBus/TCPEthernet/IPProfibus DPEtherCAT

TheprotocolIPandreferencedesignsarehardwaretestedonboththeAlteraIndustrialNetworkingKit(INK)featuringtheCycloneIVFPGAorSofting’sFPGARTEMCIIIkit.

Benefits of Altera FPGAs in Industrial Ethernet Applications

•UpdateyoursystemtoworkwithanyofthetopIndustrialEthernetandfieldbusprotocolswithoutchangingthe hardware design

•Useourpre-tested,license-freeIPtospeedyourtimetomarket

Page 7: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

SoC • 2013 • www.altera.com/industrial 7

Save Time with Functional Safety Certification for Tools, IP, and DevicesFunctional safety is increasingly a central requirement for industrial systems in the machinery, transportation, and process automation sectors. Government directives to reduce the risk of operator injuries and the demand forimprovedoperationalefficienciesaredrivingtheneedformorecomprehensivefunctionalsafetyfeatures.Safety imposes an increase in overall complexity with considerations such as:

•On-scheduleandin-budgetproductcertificationmeetingtheappropriateSafetyIntegrityLevel(SIL) asdefinedbyIEC61508andderivativeindustry-specificstandards

•Flexibilitytodesignfortoday’sdiverserequirementswhilemeetingevolvingrequirementsoverthe product line lifetime

•Costandriskreductionthroughintegrationofsafeandnon-safefunctionalityintofewerdiscretedevices

Tosimplifyandspeedupyourcertificationprocess,weworkedwithTÜVRheinland,anindependentthird-partyassessorspecializinginfunctionalsafetytestingandcertification,togainapprovalfortheuse of our products in safety applications. This makes us the first and only FPGA supplier whose FPGA devices, IP,developmenttools,andestablishedFPGAdesignflowarecertifiedforIEC61508functionalsafetyto SILLevel3.Altera’sTÜV-qualifiedsafetypackagestypicallysaveourcustomers18to24man-monthsin certifying their safety applications.

SafeRequirementSpecification

Qualification of Used Devices

and Tools

Development Without “TÜV-Qualified Safety Package”

Implementationof Safe

Functionality Development ofApplication-Specific

Hardware and/or Software

Implementation ofSafe Diagnostic

FunctionsCertification

by TÜV

Development ofApplication-Specific

Hardware and/or Software

SafeRequirementSpecification

Certificationby TÜV

Development With “TÜV-Qualified Safety Package”

Functional Safety Data Package Components – IEC 61508Qualified Tools Qualified IP Qualified Devices

Quartus® II software v11.0 SP1 Nios II embedded processor Cyclone and Cyclone II, Cyclone III FPGAs

Analysis and elaboration CRC compiler Cyclone III 60 nm FPGAs

Altera simulation libraries DDRx high-performance and next-generation controller supporting both Altmemphy and Uniphy

Cyclone IV except EP4CGX50 and EP4CGX75 FPGAs

Synthesis and place and route 8B/10B encoder/decoder Arria® GX FPGAs

TimeQuest-timing analyzer SOPC Builder IP within Quartus II software Stratix® III FPGAs

Signal Tap II logic analyzer Diagnostic IP: • CRC checker • SEU checker • Clock checker

Stratix II and Stratix II GX FPGAs

NIOS II debugger Stratix and Stratix GX FPGAs

In-System memory editor MAX® II and MAX II Z CPLDs

PowerPlay power analyzer MAX 3000A, MAX 7000AE/B/S CPLDs

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8 SoC • 2013 • www.altera.com/industrial

Smart Energy – Substation AutomationReliabletransmissionanddistributionsubstationautomationequipmentiskeytokeepingtheelectricity flowing. You may face some tough challenges when designing your substation equipment:

•MeetingawiderangeoffunctionsforIntelligentElectronicsDevices(IEDs),aswellasmonitoring,control, or safety systems

•Supportingmission-criticalsystemsinrealtimethatplacedemandsonreliability,upgradability,and interoperability

•ImplementingIEC61850overEthernetwithIEC62439-3ParallelRedundancyProtocol(PRP) andHigh-AvailabilitySeamlessRedundancy(HSR)

•Sustaininglongproductlifecycles

With a single Altera FPGA, you can develop a scalable platform that delivers the performance, flexibility,andcostsavingsyourdesignneeds.Forexample,thereal-timeswitchrequirementsinaredundantnetworkareidealforFPGAs.Ourlow-costCycloneVFPGAsandCycloneVSoCsmeettheperformancerequirementsofGbpsEthernettrafficwithPRP/HSRredundancyandevolvingstandards.OurPRP/HSRsolutionincludesnolicensenegotiations,up-frontlicensingcosts,orper-unitroyaltyreporting.

Benefits of Altera FPGAs in Smart Grid Applications

•LeverageFPGAflexibilitytoevolveyourdesignforchangingI/Ointerfacesandprotocolstandards

•Improvedperformancetoprocess10/100/1000MbpsswitchtrafficwithHSRorPRPinrealtime

•IntegrateHSR/PRPEthernetswitchwithIEDsystemfunctionsonaCycloneVSoCtoreducecost,lower power, and increase system reliability with fewer components

•FocusonnewproductdevelopmentinsteadofworryingaboutlifecyclemanagementwithourlongFPGA life cycles

PHY

Interlink ormaintenanceport

HSR/PRP ports

PHY

PHY MAC

MAC

MAC

STA MMD

Registers

On-ChipOff-Chip Host System

FRSMAC CPU

MII/GMII

MDIO

10/10

0/100

0 Mbp

sEt

hern

et Me

dium

10/10

0/100

0 Mbp

sEt

hern

et Me

dium

10/10

0/100

0 Mbp

sEt

hern

et Me

dium

MII/GMII

MII/GMII

MII/GMII

MDIO

Example: Cyclone V SoC-Based IEDs with 4-Port PRP/HSR Switch

Page 9: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

SoC • 2013 • www.altera.com/industrial 9

Smart Energy – Solar InvertersProducingreliable,moreefficient,andlesscostlysolarorphotovoltaic(PV)systemsisanimportantstepinmaking solar energy more competitive. This poses challenges in designing the solar inverter architecture to meet demands for:

•Reliabilityandusabilitywithlongservicelifetosupplydistributed,renewableenergysourceswithcentralpower generation to meet growing power needs

•Increasedefficiencyandlowerunitcostsusingadvancedcontrolalgorithmsandpowertopologieslikethree-levelinsulatedgatebipolartransistor(IGBT)andwidebandgapSiC-FETs

•Localgridcodecompliancewhichincludespowerqualitymonitoringandcontrol

OurFPGAsenablecostandefficiencythroughsiliconconvergenceontheFPGAplatformtomeetreal-timeperformance,featurerequirements,andpricepointsforhigh-volumeinverterapplications.

Benefits of Altera FPGAs in Solar Inverter Applications

•UsetheFPGAasacoprocessortooffloadtheDSPfunction,addI/Ofunctions,orintegrateDSPand communications on the SoC

•SwitchelectricalcurrentmoreefficientlyusingDSPcontrolloopandmultilevelIGBTcontrolontheFPGA

•Increase switching frequency and further reduce inductive component costs with the FPGA and wideband gap materials

•IncreaseproductivitywithsoftwaredesignflowstargetingintegratedARMCortex-A9andNiosIIprocessors andmodel-baseddesignforDSPcoprocessors

•FocusonnewproductdevelopmentinsteadofworryingaboutlifecyclemanagementwithourlongFPGA life cycles

PV Inverter with Cyclone V as Coprocessor or All-in-One SoC

DC-ACControl

DC-DCControl

Drivers Drivers

DC-DCConverter

DC-ACInverter

GridProtectionInterface

Grid

ACDCDC

Current &VoltageSensors

Control Block

SoC

Current &VoltageSensors

Current &VoltageSensors

CommunicationHPS

(e.g. ARMCortex A9)

MPPT Control

Inverter

Page 10: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

10 SoC • 2013 • www.altera.com/industrial

Video SurveillanceGovernment, municipalities, financial institutions, and businesses are driving new uses for video surveillance technologies beyond crime prevention or security into applications such as asset management, risk mitigation, and safety.

DevelopingadifferentiatedIPcamerathatincludesthelatestfeaturesandcapabilitiespresentsseveralchallenges:

•Increasingimagesensorresolutionfromstandarddefinitiontohighdefinitionwithwidedynamicrange(WDR)capabilities

•Differentiatingyourproductswithreliablevideoanalyticsthatcanrunrealtimeonhigh-definition(HD)images with low power requirements

•Flexibilitytoscaleyoursolutionacrossmultipleproductlines,addingnewfeaturesandadaptingtochanginginterface and output standards

Our FPGAs can help you easily adapt your camera design to account for changing image sensors and market requirementswhileaddingadvancedanalytics.UnlikeanASSP-basedapproach,designingwithanFPGAlets you differentiate your products in hardware and software, allowing you to release new features and stay ahead of your competitors. We provide a wide variety of devices, tools, and IP directly and through a network of partners to help you quickly and easily bring your product to market.

Benefits of Altera FPGAs in Video Surveillance

•OptimizedcontrolofHDWDRimagesensors

•IntegratemultipleIPcamerafunctionsandmultichannelvideoanalyticsinasinglechip

•Onlytechnologyprovidingadvanced1080pvideoanalyticscapabilitiesinasinglechip

•ConnectusingourflexibleoptionstovariousEthernetinterfaces

•Addcustommotorcontrolalgorithmsforpan-tilt-zoom(PTZ)functionality

•Integratewithlow-powerandhigh-performanceFPGAsandSoCs

Single-Chip IP Camera Block Diagram

Sensor Controland

WDR Pipeline

CPU(Control)

EthernetPHY

10/100Ethernet

MAC

VideoAnalytics

DRAM

FPGA

Image Sensor

H.264Encoding

Page 11: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

SoC • 2013 • www.altera.com/industrial 11

Accelerate Your Design FlowOptimizingindustrialdesignsrequiresversatilesoftwareandhardwaredevelopmenttoolsandapracticaldesignflowthatenablesanintegratedsystemtomeettheperformanceneedsofanapplication.Usingourintegratedtoolflowallowsdesignerstoreducedevelopmenttime,whilemeetingoptimizationrequirementsacrossthevariousstages and levels of system design.

Optimize Designs with an Integrated, Flexible Design Flow

ModelSystem

(Optional)

DevelopAlgorithm

in Software

Accelerate Algorithmin Hardware

Simulink/MATLAB

IntegrateSystem Hardware

CompileDesign

Integrate withApplication Software

OptimizedSystem

ARM orNios II

Processor

Quartus IISoftware

ARM or Nios IIProcessor

Software Tools

SoC

Algorithmin “C”

AlgorithmUsing

DSP Builder

Qsys SystemIntegration

Tool

Standard Software Development Tools for High Productivity

DevelopsoftwaretargetingintegratedARMandNiosIIprocessorsonAltera’sSoCandFPGAsusingtheARMDevelopmentStudio5(DS-5™)Altera®EditionToolkitandotherstandardEclipse-basedsoftwaredevelopmentanddebugtools.

DSP Builder

DesigncustomcoprocessorsforCPUoffloadandaccelerationintheFPGAusinghardwaredescriptionlanguage(HDL)orourmodel-baseddesignflowthatsimplifiesyourdesigneffort.OurDSPBuilderdevelopmenttoolshortensyourdesigncycle,enablingalgorithmdevelopmentandpartitioninginMathWorks’MATLAB/SimulinkenvironmentandautomaticgenerationofoptimizedHDL.

Intellectual Property

Together with our partners, we offer a broad IP portfolio in areas such as IndustrialEthernet,motorcontrol,andfunctionalsafetyinadditiontooptimizedstandardcommunication,memorycontroller,andDSPfunctions.

Quartus II Software Development Tool

The Qsys system integration tool, part of the Quartus II software development tool,letsyouintegratecoprocessors,interfaceIP,andon-chipARMandNiosIIprocessors.Itallowsforsystem-levelspecificationofdesigntopology,peripheraladdressing and interrupts, and AXI interconnect generation to meet required throughput, latency, and area constraints.

TheQuartusIItoolistheprogrammablelogicindustry’snumber-onesoftware inperformanceandproductivityforCPLDandFPGAdesignsynthesis,place and route, and static timing analysis.

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12 SoC • 2013 • www.altera.com/industrial

High Quality and Reliability for the Long TermManyindustrialsystemsneedtoreliablyperformdemandingfunctionsinextremelyharshenvironments,oftenforextendedperiodsoftime—insomecasesfor15yearsormore.Alterahasdecadesofexperienceapplyingthehighest quality standards, which means you get better solutions and peace of mind for your designs. As an ISO 9001certifiedcompanysince1994,wehaveshippedhundredsofmillionsofprogrammablelogicdevicesintoindustrial systems. We also require all our suppliers to comply with stringent manufacturing and test standards to ensure reliability and quality throughout your system.

Wehaveazero-defectphilosophywithrigorousproceduresateachphaseofdevelopmenttoensurethehighestqualityandlowestdefectivepartspermillion(DPPM).Ourwaferfabs,package,assembly,test,andprogrammingfacilitiesareTS-16949certifiedforaqualitymanagementsystemprovidingforcontinualimprovement, emphasizingdefectprevention,andreducingvariationandwasteinthesupplychain.

Wetakebusinesscontinuityplanning(BCP)seriously and employ several initiatives to ensure you have a continuous supply of product:

•Useofsixfabsacrossfourlocations

•DualfabstrategybyFabmatch®methodology

•Multipleassemblysitesourcing

•Sub-materialsourcingcontrol

Ouraverageproductcycleis15yearswithmanyofourproductshavinglifetimesinexcessof20years,so you can design in our products with confidence.

Waferfab(s)

Packageassembly site(s)

Testsite(s)

Programmingsite(s)

ASE, AmkorTS-16949certificates

ASE, AmkorTS-16949certificates

TSMCTS-16949certificates

✔✔

ASE, AmkorTS-16949certificates

✔✔

Altera's TS-16949 Compliant Manufacturing Flow

Active5 - 10 years

ASSP5 - 7 years (typical)

Alignment to application life cycle dynamics

t = 0

MCU7 - 10 years (typical)

ASIC10 years (typical)

Altera PLD+15 years (typical)

Phase Out1 - 3 years

ObsoleteR&D2 - 4 years

Competing PLD8 - 10 years (typical)

Life Cycle Comparison

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SoC • 2013 • www.altera.com/industrial 13

Industrial-Grade ProductsOurindustrial-gradedevicesfeaturejunctiontemperaturerangesupportfrom-40˚Cto+100˚C(orhigheronselecteddevices).Ourindustrial-gradeportfoliospansfromCPLDstoFPGAsandalsoincludesSoCsandHardCopy®ASICoptions to serve all your industrial needs.

Introducing the Cyclone V SoCTheCycloneVSoCintegratesanARM-basedhardprocessorsystem(HPS)withourFPGAfabric.Theseuser- customizableSoCsincreasesystemperformance,lowerpowerconsumption,andreduceboardspacerequirements,all designed to help you lower your overall system cost.

CycloneVSoCkeyfeatures: • Single-ordual-coreARMCortex-A9processors • VerticalmigrationacrossFPGAlogicdensities (25K,40K,85K,and110Klogicelements) • 3Gbpsand5Gbpstransceiveroptions • DualCANcontrollers(hardIP) • DualEthernetMACswithIEEE1588(hardIP) • DualPCIeinterface(hardIP) • Fullsuiteofperipherals(hardIP) • Fullerrorcorrectioncode(ECC)support – safety ready • Horizontalmigrationacrossthefamily

Cyclone V SoC Industrial-Grade Device Package Options and Maximum User I/Os

FamilyProduct

Line

Logic Density

(K LEs)

PLL

FPGA/HPS

(count)

Package Type/ Pin Count

UBGA-484(U19)

UBGA-672(U23)

FBGA-896(F31)

Ball Spacing (mm)

0.8 0.8 1.0

Dimensions (mm)

19 x 19 23 x 23 31 x 31

FPGA I/Os / Processor I/Os / LVDS I/Os / Transceivers (XCVR count)

FPGAI/O

HPSI/O

LVDSTX

LVDSRX

XCVR FPGAI/O

HPSI/O

LVDSTX

LVDSRX

XCVR FPGAI/O

HPSI/O

LVDSTX

LVDSRX

XCVR

Cyclone V SE SoC

5CSE-A2 25 5 / 3 66 161 15 18 – 145 181 31 35 – – – – – –

5CSE-A4 40 5 / 3 66 161 15 18 – 145 181 31 35 – – – – – –

5CSE-A5 85 6 / 3 66 161 15 18 – 145 181 31 35 – 288 181 72 72 –

5CSE-A6 110 6 / 3 66 161 15 18 – 145 181 31 35 – 288 181 72 72 –

Cyclone V SX SoC

(3 Gbps)

5CSX-C2 25 5 / 3 – – – – – 145 181 31 35 6 – – – – –

5CSX-C4 40 5 / 3 – – – – – 145 181 31 35 6 – – – – –

5CSX-C5 85 6 / 3 – – – – – 145 181 31 35 6 288 181 72 72 9

5CSX-C6 110 6 / 3 – – – – – 145 181 31 35 6 288 181 72 72 9

Cyclone V ST SoC

(5 Gbps)

5CST-D5 85 6 / 3 – – – – – – – – – – 288 181 72 72 9

5CST-D6 110 6 / 3 – – – – – – – – – – 288 181 72 72 9

ARM Processor SystemSingle / Dual

Core ARM Cortex-A9MPCore Processor

HardMemory

Controller

HardPeripherals

(CAN, EMAC,...)

28 nm FPGA

HardMemory

Controller

HardPCIe Gen 1

2x

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14 SoC • 2013 • www.altera.com/industrial

Cyclone V Industrial-Grade Device Package Options and Maximum User I/Os

FamilyProduct

Line

Logic Density

(K LEs)

PLL

(count)

Package Type/ Pin Count

MBGA -301

(M11)

MBGA -383

(M13)

MBGA -484

(M15)

FBGA -256 (F17)

UBGA -324 (U15)

UBGA -484 (U19)

FBGA -484 (F23)

FBGA -672 (F27)

FBGA -896 (F31)

FBGA -1152 (F35)

Ball Spacing (mm)

0.5 0.5 0.5 1.0 0.8 0.8 1.0 1.0 1.0 1.0

Dimensions (mm)

11 x 11 13 x 13 15 x 15 17 x 17 15 x 15 19 x 19 23 x 23 27 x 27 31 x 31 35 x 35

I/Os / LVDS / Transceivers (count)

Cyclone V E

5CE-A2 25 4 – 208 / TBD – 128 / 32 176 / 44 224 / 56 224 / 56 – – –

5CE-A4 49 4 – 208 / TBD – 128 / 32 176 / 44 224 / 56 224 / 56 – – –

5CE-A5 77 6 – 208 / TBD – – – 224 / 56 240 / 60 – – –

5CE-A7 149.5 6 – – 240 / 60 – – 240 / 60 240 / 60 336 / 84 480 / 120 –

5CE-A9 301 6 – – – – – 240 / 122 224 / 56 336 / 84 480 / 120 –

Cyclone V GX

(3 Gbps)

5CGX-C3 31.5 4 – – – – 144 / 36 / 3 208 / 52 / 3 208 / 52 / 3 – – –

5CGX-C4 50 6 127 / TBD / 4 175 / TBD / 6 – – – 224 / 56 / 6 240 / 60 / 6 336 / 84 / 6 – –

5CGX-C5 77 6 127 / TBD / 4 175 / TBD / 6 – – – 224 / 56 / 6 240 / 60 / 6 336 / 84 / 6 – –

5CGX-C7 149.5 7 – – 240 / 60 / 3 – – 240 / 60 / 6 240 / 60 / 6 336 / 84 / 9 480 / 120 / 9 –

5CGX-C9 301 8 – – – – – 240 / 60 / 5 224 / 56 / 6 336 / 84 / 9 480 / 120 / 12 560 / 140 / 12

Cyclone V GT

(5 Gbps)

5CGT-D5 77 6 127 / TBD / 4 175 / TBD / 6 – – – 224 / 56 / 6 240 / 60 / 6 336 / 84 / 6 – –

5CGT-D7 149.5 7 – – 240 / 60 / 3 – – 240 / 60 / 6 240 / 60 / 6 336 / 84 / 9 480 / 120 / 9 –

5CGT-D9 301 8 – – – – – 240 / 60 / 5 224 / 56 / 6 336 / 84 / 9 480 / 120 / 12 560 / 140 / 12

Cyclone IV E Industrial-Grade Device Package Options and Maximum User I/Os

FamilyProduct

Line

Logic Density

(K LEs)

PLL

(count)

Package Type/ Pin Count

EQFP-144 (E144)

MBGA-164 (M164)

UBGA-256 (U256)

FBGA-256 (F256)

UBGA-484 (U484)

FBGA-324 (F324)

FBGA-484 (F484)

FBGA-780 (F780)

Ball Spacing (mm)

0.5 0.5 0.8 1.0 0.8 1.0 1.0 1.0

Dimensions (mm)

22 x 22 8 x 8 14 x 14 17 x 17 19 x 19 19 x 19 23 x 23 29 x 29

I/Os / LVDS I/Os (count)

Cyclone IV E

EP4CE6 6.3 2 91 / 21 – 179 / 66 179 / 66 – – – –

EP4CE10 10.3 2 91 / 21 – 179 / 66 179 / 66 – – – –

EP4CE15 15.4 4 81 / 18 89 / 21 165 / 53 165 / 53 – – 343 / 137 –

EP4CE22 22.3 4 79 / 17 – 153 / 52 153 / 52 – – – –

EP4CE30 28.8 4 – – – – – 195 / 61 328 / 124 532 / 224

EP4CE40 39.6 4 – – – – 328 / 124 195 / 61 328 / 124 532 / 224

EP4CE55 55.9 4 – – – – 324 / 132 – 324 / 132 374 / 160

EP4CE75 75.4 4 – – – – 292 / 110 – 292 / 110 426 / 178

EP4CE115 114.5 4 – – – – – – 280 / 103 528 / 230

True LVDS I/O count only. Does not inlcude eTX/eRX.

LVDS count includes dedicated and emulated LVDS pairs, see Handbook.

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SoC • 2013 • www.altera.com/industrial 15

MAX V Industrial-Grade Device Package Options and Maximum User I/Os

FamilyProduct

Line

Logic Density

(K LEs)

Package Type/ Pin Count

MBGA-64 (M64)

EQFP-64 (E64)

MBGA-68 (M68)

TQFP-100 (T100)

MBGA-100 (M100)

TQFP-144 (T144)

FBGA-256 (F256)

FBGA-324 (F324)

Ball Spacing (mm)

0.5 0.4 0.5 0.5 0.5 0.5 1.0 1.0

Dimensions (mm)

4.5 x 4.5 9 x 9 5 x 5 16 x 16 6 x 6 22 x 22 17 x 17 19 x 19

I/Os (count)

MAX V

5M40Z 40 30 54 – – – – – –

5M80Z 80 30 54 52 79 – – – –

5M160Z 160 – 54 52 79 79 – – –

5M240Z 240 – – 52 79 79 114 – –

5M570Z 570 – – – 74 74 114 159 –

5M1270Z 1270 – – – – – 114 211 271

5M2210Z 2210 – – – – – – 203 271

Cyclone IV GX Industrial-Grade Device Package Options and Maximum User I/Os

FamilyProduct

Line

Logic Density

(K LEs)

PLL

(count)

Package Type/ Pin Count

QFN-148(N148)

FBGA-169(F169)

FBGA-324(F324)

FBGA-484(F484)

FBGA-672(F672)

FBGA-896(F896)

Ball Spacing (mm)

0.5 1.0 1.0 1.0 1.0 1.0

Dimensions (mm)

11 x 11 14 x 14 19 x 19 23 x 23 27 x 27 31 x 31

I/Os / LVDS / Transceivers (count)

I/O LVDS XCVR I/O LVDS XCVR I/O LVDS XCVR I/O LVDS XCVR I/O LVDS XCVR I/O LVDS XCVR

Cyclone IV GX

(2.5/ 3 Gbps)

EP4CGX15 14.4 3 72 25 2 72 25 2 – – – – – – – – – – – –

EP4CGX22 21.3 4 – – – 72 25 2 150 64 4 – – – – – – – – –

EP4CGX30 29.4 4 / 6 – – – 72 25 2 150 64 4 290 130 4 – – – – – –

EP4CGX50 49.9 8 – – – – – – – – – 290 130 4 310 140 8 – – –

EP4CGX75 73.9 8 – – – – – – – – – 290 130 4 310 140 8 – – –

EP4CGX110 109.4 8 – – – – – – – – – 270 120 4 393 181 8 475 220 8

EP4CGX150 149.8 8 – – – – – – – – – 270 120 4 393 181 8 475 220 8

Page 16: 2 SoC - Intel · Our motor control IP includes pulse-width modulation (PWM), analog-to-digital (ADC), and digital encoder interfaces. It also has integrated, customizable field-oriented

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