2 MC Soln - Vidyalankarvidyalankar.org/file/diploma/prelim_paper_soln/SemV/ETRX/2_MC_Soln.pdfbegins with a start bit which is active low is then followed by a 8 data bits starting

1013/TY/Pre_Pap/Elec/MC_Soln 36

Vidyalankar T.Y. Diploma : Sem V

[EJ/EN/ET/EX/DE/IS/IC/IE/EV/MU] Microcontrollers

Prelim Question Paper Solution

(i) Pin functions

ADC interfaced with 8085 through 8255 Let the ADC 0808 be interfaced to 8085 microprocessor through 8255 PPI configured in Basic input/output (mode 0) let the input/output addresses be 80H 83H. Let the Port Assignments be

Port / Pin ADC Signal Details

PA7 to PA0 D07 to D00 Digital outputs of ADC to Port A

PB0 SC ADC control start conversion PB1 CLK ADC control clock PB2 OE ADC control output enable PC EOC ADC Stats End of Conversion

(ii) Comparison of Von Neumann Architecture and Hardward Architecture

Von Neumann Architecture Harvard Architecture i) Von Neumann Architecture

identifies single memory space, physically it is Divided into the program memory and Data memory logically the program and Data memory alocations may change dynamically

Harvard Architecture identifies two separate memory spaces, physically one for program memory and other for Data memory alocations are fixed.

VCC VRef+

Ain

VREF GND

8

SC

CLK

DE

EOC

A D C 0 8 0 8

1. (a)

1. (a) Vidyala

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ii) Single set of address and Data buses is used

Two separate set of address and Data bus are used.

iii) There is only one memory map that contains program as well as data.

There are two separate memory map one for program and one for data.

iv) user has flexibility in sizing, storing and allocating memory space for program and Data.

As program and Data are separate memory. There is no such flexibility.

v) It is difficult to implement the instruction pipeline on one Neumann processor.

Implementing instruction pipeline is very simple in Harvard processor.

(iii) Memory Organisation in 8051 A Typical Register Bank Internal Program Memory External Program Memory

8051 Memories

Internal Memory External Memory

Internal Data Memory (128 Byte RAM & Special

Function Registers).

Internal Program Memory (4 Kb ROM).

External Data Memory (Max 4 kB)

External Program Memory (Max 64 kB)

Reset

0000H

FFFFH

60 kB (Accessed both when EA 0 or 1)

1000H

0FFFH

EA 0

R7 R6 R5 R4 R3 R2 R1 R0

07H

06H

05H

04H

03H

02H 01H

00H

1. (a)

Internal 4 kB ROM

0FFFH

0000H

EA 1 Vidyala

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Internal Data Memory External Data Memory Internal Data Memory

The internal data memory contains internal RAM’s and SFR. The total size of internal data memory is 256 bytes of which 128 byte used by internal RAM and remaining 128 bytes are special function register space. The 128 RAM starts at memory location 00H and ends at FFH in this 128 byte 1st 32 bytes upto 1FH are assigned to registers banks. It contains 4 registers bands of 8 bytes each. Each register bank has 8 general purpose register named R0 to R7 i.e. registers R0 to R7 are same as memory locations in currently selected register bank. The register bank can be selected by RS0 and RS1 bit in PSW register. After reset bank 0 is selected by default. Memory location 20H to 2FH are assigned for bit addressable memory. These 16 byte location can also be accessed individual bit wise. Memory location From 30H to 3FH are available as general purpose RAM location to user. Memory space from 80H to FFH is reserved for special function register. It is of size 128 byte however only 21 SFR are actually defined for 8051 (No. of SFR may varied From model to model and make of 8051). The memory location where no SFR are defined are empty. External data memory A maximum of 64KB of external data memory can be implemented with 8051. The address range from 0000H to FFFFH. This memory is accessed only through indirect address.

Special function Register (SFR)

Space

Reg. Bank 3

Reg. Bank 2

Reg. Bank 1

Reg. Bank 0

80H

FFH

User Memory 30H

7FH

2FH Bit Addressable

Memory 20H

18H 17H 10H 0FH 08H 07H 00H

2FH

128

Byt

es 25

6 B

ytes

64 kB (Indirect

Accessed)

0000H

Reset

FFFFH

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Internal and External Program memory 8051 has 4KB ROM as internal program memory. 8051 can have 64KB of external program memory maximum. However the access to lower most 4KB is controlled by EA pin. When EA is enabled 4KB ROM is used and 8051 is RESET at 0000H. When EA is zero 8051 access, external ROM and RESET at 0000H in the external program memory. The upper 60KB (Address range 1000H to FFFFH) is always accessed in the external program memory both when EA 0 EA 1 .

(iv) Exchange Instructions

Syntax XCHA, Rn XCH A, add XCHA, @Ri XCHDA, @ Ri No of bytes 1 2 1 1 Operation

A Rn Contents of A & Rn are mutually exchanged.

A (add) Contents of A & memory location pointed by add, are exchanged.

A ((Ri)) Contents of A & memory location specified by Ri are exchanged.

A3 0 ((Ri))3 0 Contents of Bit 3 0 (lower Nibble) & A and memory location specified by Ri are exchanged.

Addressing Mode

Register Direct Indirect Indirect

Examples XCHA R5 XCHA 2AH XCHA @ R0 XCHDA @Ri

(i) Synchronous Serial Data Communication

In Synchronous Serial Data Communication, transmitter and receiver use identical and synchronous CLK the data is transferred as fixed no. of byte block the communication usually begins with the synchronization byte they are called as sync bytes. Its 1 byte is used for this purpose it is called monosync and if 2 byte are used is called bi-sync. After the Sync byte the continuous stream of the data of the given block size is followed. The transmission ends with termination usually CRC (Cyclic Redendency clock) is used for checking the integrity of data the communication is high speed and provides higher data transfer rates.

Asynchronous Serial Data Communication

In this technique the transmitter and receiver CLK are independent they Operate at same frequency but are not synchronous to each other the receiver identifies valid char reception by a trailing edge the transmission

T Data Block Sync

Byte 2 Sync

Byte 1

D0 D1 D2 D3 D4 D5 D6 D7

Start Bit

P

Stop bits

Parity bits

1. (a)

1. (b)

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begins with a start bit which is active low is then followed by a 8 data bits starting with D0 at the end of last Data bit. Optionally parity bit is also transmitted the communication ends with 1 or 2 stop bits stop bits are always active high asynchronous serial Data communication is relatively slower but proved better flexibility.

(ii) Internal Block Diagram of 8051 (8051 Architecture)

A 8051 Internal Block Diagram shows following functional Logic Control Unit : The control unit consist of timing and control logic which is

responsible for successfully executing instruction over 8051. It also provide timing synchronization for all the events and operation over 8051. For this timing the necessary clock is generated by clock generator which is required to be connected to the crystal oscillator over X1 and X2 pins.

The instruction register is used to store the instruction currently being executed. It keep the opcode of the instruction. The instruction decoder decode it and it interpret the instruction. ALU and associated : The execution area of 8051 consist of following component.

Port 1 Latch Port 3 Latch

P3.0 P3.0 P1.0 P1.7

DPTR

PC

Increment

Buffer

Mem. Addr Register 128

8 Static

SFR’s &

Timer/UART/Interrupt/ Memory Control

PSW

8bit ALU

TMP1 TMP2

A B SP

To All Blocks

Register /Decode

Timing &

Contro

Clock Generator

X2

X1

ALE

RST

EA

PSEN

GNB

VCC

+5V

4K 8 ROM Port 0

Latch Port 2 Latch

P0.0 P0.7 P2.0 P2.7

8 8

8 8

1. (b)

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ALU: It is an 8 bit full function Arithematic and logic unit it is capable of performing arithmetic instruction such as addition, subtraction, multiplication, division, increment, decrement etc. It is also capable of performing logical instruction such AND, OR ExOR and compliment. TNP 1 and TNP 2 This are 8 bit register providing 2 I/P to the ALU. They are not user accessable. Accumalor A : It is an 8 bit general purpose register. It provides one of the I/P to ALU and it is use to store the result of ALU. Register B : It is an 8 bit general purpose register however it is specifically used by multiplication and division. Programmed status word’s : It is a flag-register and it store the condition flag for the last ALU Operation. SP (Stack pointer) : In 8051 SP is an 8 bit register. It stores the memory location point A to the top of the stack.

Main 3 memories : 8051 has 2 internal memories. It has 4 K 8 internal ROM which is used as internal program memory. 128 8 static RAM is a general purpose internal data memory. It includes general purpose register and bit addressable memory. The upper portion of internal data memory consist of special function registers (SFR) They are used to control the functionality of ports, timers, interrupt, serial input/output (UART and External memory access) Main 4 ports : 8051 has 4 general purpose input/output ports. They are connected through their respective port, latches and buffer. Port 0 and port 2 latches also connect to memory address bus for generating external memory address. Port 3 latch is also connected to the control logic of Timer UART/interrupt/memory control for providing the alternate function. Port 1 does not have any alternate function and therefore is connected to only internal bus. 16 bit memory access registers : Memory access register is used to generate 16 bit memory address. When external memory is being accessed, it also generates 12 bit Address for the internal programmed memory (4KB ROM). The buffer is used for connecting the internal bus with 16 bit register. Incremental latch is used to increment either PC or DPIR contents. PC (Program Counter) : It is a 16-bit register. It is used for storing the mem address from where the next instruction would be executed with the execution of instruction. PC is continuously incremented. DPTR (Data Pointer) : It is a 16 bit register. It is used to store the memory address pointing to a data. The data pointer has two 8 bit sub register DPH and DPL. DPH stores upper 8 bits of the data counter and DPL stores lower 8 bits of the data counter. DPH and DPL can be used as general purpose register.

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Bit Addressable Memory

Internal RAM addresses from 20H 2FH are assigned as Bit addressable memory. There are total 16 location each one of which is of 8 bits. They provides a total of 128 bits that can be addressed at a bit level. The table shows the actual bit address map of bit addressable memory. Bit address are from 00H 7FH. Bit 0 of memory location 20H is accessed at bit address 00H and in this way the last location is bit 7 of memory location 2FH, having bit address 7FH. Therefore this portion of memory can also be access at individual bit level Therefore it is called as bit Addressable memory.

Types of Subroutines

i) Simple Subroutines : The calling program encounters the call instruction (A CALL or L CALL) it saves the contents of PC by pushing it on the top of the stack. Then the control is transfers to subroutine the subroutine execution ends with RET instruction. Then the PC contents are popped back from the stack. Therefore the original calling program execution resume from the next instruction onwards.

ii) Nested Subroutines :

The calling program encounters CALL instruction and transfers control to subroutine 1 which in turn calls subroutine 2 and further subroutine 2 CALL subroutine 3. When subroutine 3 ends execution the control returns to previous subroutine successively. Finally the control returns to calling program. This type of subroutine is called Nested subroutines. The depth of nesting is limited to availability of memory physically in the stack.

7FH 7EH 7DH 7CH 7BH 7AH 79H 78H 77H 76H 75H 74H 73H 72H 71H 70H

17H 16H 15H 14H 13H 12H 11H 10H 0FH 0EH 15H 14H 13H 12H 11H 10H 07H 06H 05H 04H 03H 02H 01H 00H

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

2FH 2EH

23H

22H

21H

Internal RAM Byte Address

Bit Address

2. (a)

2. (b)

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Recursive and Re-entrant subroutines : (a) Recursive subroutine :

It is the subroutine which keeps on calling itself. Recursive subroutines must be handled carefully as they may end up into an enless loop loosing the program control.

(b) Re-entrant subroutines :

In case of reenterunt subroutine two or more subroutines keep on calling one another they may enter into deadlock if allowed to CALL infinitely. The care must be taken to insert equal number of PUSH and POP instruction in any subroutine to avoid integrity problem and failure of stack.

Program to find the largest of ‘n’ numbers Number are stored in memory from 30 to 3FH. Find the largest of these numbers and store it in 40H location.

START : MOV A, #F00H MOV 40H, A MOV R0, ,#30H MOV R7, #10H BACK : MOV A, 40H CLR C SUBB A, @R0

Start

Initialize Accumulator with 00 H and 40 H Initialize Pointer in R0 with 30 H Initialize Counter in R7 with 10H

Load accumulator from 40H

Is Cy = 1

Increment the pointer R0 Decrement the counter R7

Load 40H with Number

Subtract number from memory

Is R7 = 0

Stop

No

No

Yes

Yes

2. (c)

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INC SKIP MOV 40H, @R0 SKIP : INC R0 DJNZ R7, BACK HERE : LJMP HERE Serial I/O (UART) Operations in 8051

SCON Serial Configuration Register

SM0 SM1 1 Multiprocessor Mode Enabled 0 0 Mode 0 Shift register 0 1 Mode 1 8 Bit UART – Variable Baud Rate 1 0 Mode 2 9 Bit UART Variable Baud Rate 1 1 Mode 3 9 Bit UART Variable Baud Rate

REN 1 Receiver Enabled 0 Receiver Disabled TB8 Transmit Bit 8 (9th Bit) RB8 Received Bit 8 (9th Bit)

RI Receiver Interrupt (Receiver full) TI Transmitter Interrupt (Transmitter Empty)

Intel 8255 PPI Programmable Peripheral Interface

Pin Functions

SM0 SM1 SM2 REN TB8 RB8 RI TI

7 0 SCON (98H) (98H – 9FH)

0 Multiprocessor Mode disable

VCC

RESET

8 8

4

4

8 0BP

7BP

8255

GND WR

RD

CS

A0

A1

D0

D7

0CP

3CP

4CP

7CP

0AP

7AP

2. (d)

2. (e)

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8255 is a 40 pin DIP. It provides 3 input/output ports of 8 bit each on up side it has following signals. Databus D7 to D0 8 bit bidirectional Data Bus, A1 and A0 Address lines Reset Active high Reset Signal usually connected to RST out of 8085 CS (chip select) Active low chip select signal 8255 is selected only when

CS = 0. RD and WR Read and Write control signals connected toRD and WR of 8085 respectively.

Comparison of RISC and CISC

RISC Reduced Instruction Set

Computing

CISC Complex Instruction Set

Computing i) Very few instruction typically less than

256. Large no of distinct instructions typically more than 256.

ii) Limited no of Addressing modes typically less than or equal to 4.

Large no of addressing mode typically 5 to 20.

iii) Single size of instruction format. Variable size instruction format. iv) Limited instruction formats less than

or equal to 4. Large no of instruction format 5 or above.

v) Most of the instruction (around 80%) operate with register Operand ALU instructions used only register Operands.

Most of the instructions including ALU instruction can use register, memory or immediate Operands.

vi) Large register file (30 to 200) register. Small register file (5 to 30) register. vii) Uses hardwired control unit. Uses micro-programmed control

unit. Assembler Directives

Assembler Directives are not the instructions in the assembly language program but they are commands for the assembler to perform certain task

i) ORG Directive : ORG directive tells assembler to organize assembly

language code from the specified address. Syntax : ORG address Address can be specified in Decimal or hexadecimal. Example : ORG 0038H Organize code from 38 (decimal) address ORG 0070H Organizes code from 70H hexadecimal address

ii) EQU Directive : EQU tells the assembler to declare a constant Syntax : constantname EQU Value

Value can be specified in Decimal or hexadecimal

Assembler Program ASM

Machine code Assembly language

3. (a)

3. (b)

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Example : DNUM EQU 23 Assigns 23 (decimal) value to constant DNUM DHX EQU 4AH Assigns 4AH (Hex) value to constant DHX

iii) DB Directive : DB tell the assembler to Declare Byte site variable Syntax : var_name DB Value , Value ,...... Example : NUM 1 DB 6BH Inits variable NUM 1 with init value 6BH NUMX DB 12H, 23H, 46H Declares Carry of 3 Byte as NUMX DCHAR DB ‘A’ Declare DCHAR as character ‘A’ (AS ()) MSG DB ‘HELLO!’ Declares MSG as string ;HELLO!’

iv) END Directive : Tells assembler that end of source code is reached. It is the last statement of any assembler program.

Syntax : END

v) Data Directive Syntax Data : This directive tells assembler that data and area begins in the memory after the data directive is encountered. Lines subsequent to data will contain no instruction but only data.

vi) Code Code Syntax Code : This directive tells assembler that the code area starts after this directive is encounter. Lines subsequent to code contain only.

Microcontroller Systems 51 (MCS51) Family Over View :

MCS51 Family Standardizes Specific aspects of c Standard Instruction Set Standard Instruction Types/Format Standard Addressing Modes. (1) Immediately addressing mode

(2) Register addressing mode (3) Direct addressing mode (4) Register Specific addressing mode (5) Register Indirect addressing mode (6) Indexed addressing mode

Standard Program and Data Memory Access Standard Minimum Hardware Resources 8057 Compatible CPU Core ROM Less or Minimum 1KB ROM 128 Byte Static RAM Minimum 2 Times (8.116 Bit) One Serial Port (UART) Minimum 2 input/output ports. Fixed Reset/Interrupt Vector Locations.

3. (c)

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Example : 89C51 Is MCS51 Family 8 bit Micro controller with Flash ROM size 4KB and C MOS = 12 V programmable

8051 was very popular and therefore similar IC’s were manufactured by different manufacturer. However all of them conform to MCS 51 standard architecture and support for the standard instruction set. There are above 30 manufacture with at least 350 varients of 8051 manufactured all over the world to identify the chip with correct size of memory, type of memory programmability and other features above mentioned nomenclature was used

Program to perform Division of two 8-bit numbers

Consider two 8bit numbers stored in 8051 internal RAM locations 30H and 31H. Write the quotient in 32H and remainder in 33H.

START : MOV A, 30H MOV B, 31H DIV AB MOV 32H, A MOV 33H, B HERE : LJMP HERE TCON Timer configuration Register

TF1 and TF0 Timer Overflow Bits Set when T is reached Reset when serviced

TR1 and TR0 Timer Run stop Bits Timer starts when Set Timer stops when Reset

IE1 and IE0 Interrupt Enabled bits Set when Interrupt Detected Reset when serviced

8 X C X X

0 PROM F OTPROM 7 EPROM 9 flash

ROM Technology Memory

3 ROM Less 5 with ROM

ROM Size

1 4 KB 2 8 KB 3 12 KB 4 20 KB 8 32 KB

Programmability

C CMOS 12V Prog. L Low Power S In system programmable LV Low voltage (5V) Prog.

TF1 TR1 TF0 TR0 IF1 IT1 IF0 IT0

7 0 TCON (88H) (88 8FH)

3. (d)

3. (e)

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IT1 and IT0 Interrupt Trigger Bits Interrupt Edge triggered if Set Interrupt level triggered if Reset (i) Boolean Processor of 8051

Boolean Operations are Operations on Bit Operands 8051 Supports separate Data type Bit. Bit operands have 8 bit Address.

They are processed by separate set of Instructions called as Bit Manipulation as Boolean instructions.

Bit Addresses are

Bit Addresses

Byte Address Details

00H 7FH 20H 2FH Bit Addressable RAM 80H 87H 80H Port 0 90H 97H 90H Port 1 A0H A7H A0H Port 2 B0H B7H B0H Port 3 88H 8FH 88H TCON Register 98H 9FH 98H SCON Register D0H D7H D0H PSW Register E0H E7H E0H Accumalator A F0H F7H F0H B Register A8H AFH A8H IE Register B8H BFH B8H IP Register

The operations performed by Boolean processor of 8051 are using carry flag as equivalent of an accumulator i.e. carry flag can be visualize as single bit accumulator.

The operations performed on the bit operand are : i) Bit moves : This Operations move the bit operands from their bit

address location to carry flag and vise versa. ii) Bit logical operations : In this Operations bit Operands can be AND,

OR and complement. iii) Bit Conditional jumps ; In this operation a conditional jump can be

performed on the basis whether bit operand set (1) or Reset (0).

(ii) Stack Operations in 8051 In 8051, stack grows upwards. Stack is in Internal RAM stack addresses are 8 bit SP is also 8 bit

Register Stack transfers are also 8 bit. Adding a byte to stack is called PUSH Operation. In this operation SP is

first incremented by 1 and then a byte is pushed on the Top of the stack Removing byte from stack is called POP Operation. In this operation first

the byte is popped from the top of the stack and then SP is decremented by 1.

4. (a)

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Syntax PUSH instruction PUSH address

POP instruction POP address

No of bytes 2 2 Operation add Internal RAM or SFR, direct address

SP SP + 1 (SP) (add) SP is PreIncremented by 1. Then the Data Contents of the memory location pointed by address are pushed on the top of the stack.

(add) (SP) SP SP 1 The contents on stack top are popped into the memory location pointed by address. Then the SP is post decremented by 1.

Addressing Register Specific Register Specific Examples

(iii) Program to perform Blinking LED

This program sends 1 and 0 alternately on all the port pins and uses a software delay routine this program is used for checking weather the 8051 is in working condition or not it can be done by simply touching the LED to each one of the pins of 8051 ports.

START : MOV R0, #30H MOV R1,#40H MOV R7, #10H LOOP : MOV A, @R0 XCH A, @R1 MOV @ R0, A INC R0 INC R1 DJNZ R7, LOOP HERE : LJMP HERE END

(iv) PSW (Program Status Word) Registers :

CY Carry flag AC Auxillary carry flag F0 User Defined flag OV overflow flag P Parity flag

Rs1 Rs0 Register Bank mem. Address 0 0 Register Bank 0 00H 07H

0 1 Register Bank 1 08H 0FH

1 0 Register Bank 2 10H 17H 1 1 Register Bank 3 18H 17H

CY AC F0 RS1 RS0 OV P

PSW

7 0

4. (a)

4. (a)

43H

2CH

2CH

43H

44H

E0H

SP

A

(1)

(2)

62H

3FH

3FH

SP

D0H

PSW

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Program status word (PSW) is an 8 Bit register which is available at byte address D0H. It is bit addressable and it contains flags as shown above. Bit 0 Parity flag in PSW is set to 1 when ALU result has even parity other

wise it is reset to 0. Bit 1 not used. Bit 2 is over flow (OV) flag. This flag indicates over flow when an addition

or sub in ALU generates sign bits, inconsistancy this flag is set to 1. The flag is considered while following signed number convension. It can be ignored while using number.

Bit 3 and Bit 4 register bank select as per the table. Bit 5 F0, this flag can be defined by a user. Bit 6 AC auxillary carry flag, if there is carry out of Bit 3 while addition or

there is Borrow into Bit 3 while subtraction, this flag is set to 1. Bit 7 carry Flag CY if there is carry out of MSB while addition or if there is

borrow into bit 3 while subtraction. (i) Pin configuration

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

XTAL2

XTAL1

GND

VCC

P0.7 (AD7)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P0.1 (AD1)

P0.0 (AD0)

ALE / Prog

PSEN

EA /Vpp

P2.0 (A8)

P2.1 (A9)

P2.2 (A10)

P2.3 (A11)

P2.4 (A12)

P2.5 (A13)

P2.6 (A14)

P2.7 (A15)

1

8051

RD

(WR)

(T1)

(T0)

(INT1)

(INT0)

(TD)

(RD)

Port 1

Port 3

Port 0

Port 2

2

3

4

5

6

7

8

10

11

12

13

14

15

16

18

19

20

P3.7 17

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

RST 9

21

4. (b)

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Features : 8Bit Microcontroller 8bit ALU and internal Data Paths. Operates on +5V DC 0.5V Tolerance Operates at 6 MHZ (with 12MHZ Crystal) 128 Byte Static RAM 4 KB of ROM 4 input/output Ports of 8Bits each (Total if 32 Digital Input/Output Lines)

Bit Accessible. 2 Timer/Counter channels (8/16 Bit) 2 External Interrupts (Total 5 interrupt sources) 1 serial input/output Port (UART) Supports full duplex Asynchronous

serial Operation 8General Purpose Registers. Special Purpase register (SFR) for controlling Ports/Timers/Interrupt/UART Available as 40 Pin

(ii) 8255 PPI : Mode 1 Operations

(a) Mode 1 : Input Port : (Handshaked I/O)

IBRB

8

8

8

Input Device

Input Device

8255

IBFA

p

RD

7AP

AP

CP

CP

BP

0BP

CP

CP

IBRB

BSTD

ASTD

D0

D7

CP

0CP

4. (b)

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Port C Assignment :

CWR

(b) Mode 1 : Output Port : Handshaked Input/Output

7 0

1 0 1 1 1/0 1 1 X

Mode 1 Group A Mode 1

Group B

INTRB

8

8

8

Output Device

Output Device

8255

AOBF

WR

7AP

0AP

CP

CP

BP

0BP

CP

CP

AACK

D0

D7

CP

0CP

7 0

input/ output

IBFA ASTB INTRA BSTB IBFB INTRB input/ output

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Port C Assignments

CWR

8255 Mode 2 Operations (Group A Only) : Bidirectional Input/Output

Port C assignment

CWR :

7 0 1 1 X X X

Bidirectional Operation As per Group B Mode 2 Group A

7 0 1 0 1 0 1/0 1 0 X

Mode 1 Group B Mode 1 Group A

8

8

Output Device

8255

AOBF

WR

7AP

0AP

CP

CP

BP

0BP

CP

CP

AACK

D0

D7

CP

CP

8

3CPAs per Group B

p Side

7 0

AOBF AACK IBFA INTRA input/output

IBFB BOBF input/output

7 0

AOBF AACK IBFA ASTB INTRA input/ output

input/ output

input/ output Vidy

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(i) EA When = 0: external Access is enabled and program is executed from external program memory when EA = VCC (5V): external Access is disabled and program is executed from internal 4KB ROM When EA = VPP (typically 12V): 8051 enters into programming mode. In this situation the internal ROM can be programmed EA must be tied to GND or VCC while in operation it cannot be kept floating.

(ii) PSEN Program Stored Enable. This signal is high whenever External memory is accessed and addressed are issued on multiplexed Bus AD0 to AD7 (port 0) otherwise this signal is low indicating that the multiplexing is reserved for Data.

(iii) RST ACTIVE high RESET when this pin is made high, 8051 stopping in earlier operations and when the signal goes low again following events takes place.

(iv) XTAL1 Crystal Oscillator Connection Crystal Oscillator is Connected

across this 2 pins.

Comparison of Microprocessor and Micro-controller : Microprocessor Micro-Controller i) p are core computing devices

which contains the processing and alied logic. Only the integration is lower and focus is on CPU performance and speed.

The microcontroller combines the processing unit memory and input/output component into a single device. The integration is higher and the focus is on utility and application.

ii) p connects two system component through external address, data and control buses.

As many of the system component are the chip itself usually external buses are not used.

iii) There is no memory or input/output port directly available on the p chip

There is some amount of memory and input/output ports are available on c chip

iv) System implentation requires many design steps and therefore takes longer.

System implantation is fast as most system component are on chip.

v) The system configuration flexibility is fully available for the user.

c comes with a fixed system configuration and offer low flexibility.

vi) p based system are best suitable as commercial and core computing system.

c based system are best suitable as automation and embedded system.

5. (a)

5. (b)

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8051 : CALL Instructions

Syntax : A CALL Sadd 2 byte instruction

Operation : SP SP + 1 2K Scope (SP) PCH SP SP + 1 (SP) PCL PCNEW

15 11OLD(PC )

+ Sadd100

Existing PC is pushed to stack. SP is incremented by 2 net. Then the control is transferred to New PC which is generated by retaining Bits 1511 of OH PC loading bits 100 from 11 bit Sadd supplied in the instruction.

Syntax : L CALL ladd 3 byte instruction

Operation : SP SP + 1 64K Scope (SP) PCH SP SP + 1 (SP) PCL PC ladd

Existing PC is pushed to stack. The SP is incremented by 2. The new PC is loaded from ladd supplied in 2nd /3rd Byte of instruction.

Return instruction Syntax : RET Operation : PCL (SP)

SP SP 1 PCH (SP) SP SP 1

PC is popped from stack. The SP is not decremented by 2 Return from Interrupt Instruction Syntax : RETI Operation : PCL (SP)

SP SP 1 PCH (SP) SP SP 1 PSW (SP)

SP SP 1 PC is popped from stack followed by PSW SP is net decremented by 3.

5. (c)

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The program development cycle start with problem definition. In this stage the problem is defined i.e. what exactly the program is suppose to do when it is developed, it is then followed by analysis. In analysis we freeze the programming logic. The programming logic can be expressed in step by step textual sequence of statements it is called as Algorithm it can also be represented diagrammatically. The diagrammatic representation of programming logic is called flow chart. Next stage is developing the program in syntax or grammar of the assembly language or the high level language it is called as coding. Once the program is coded it is assembled with an assembler or is compiled with the help of compiler. If there are any syntax error they are corrected by modified coding and they are assembling again when the program is syntax error free and object code is generated when the object code is linked the executable code of the program is read. Then the program is burned into 8051 chip with the help of a programmer it is then tested for logical errors with the help of Debugger or sometime even with a simulator or Emulator. The logical errors are removed by repeating the cycle. When the program is free of logical errors the prog. Development is complete. ASM Files : This files contain the source code which is actually the machine

code generated by assembler or compiler. OBJ Files : This files contain the object code which is actually the machine

code generated by assembler or computer. Hex Files : This files contain the executable code in Intel Hex. decimal

Format ready to be downloaded and burn on 8051 chip. LST Files : This are least files generated by the debugger. It contains the

source code. Source code leasting with the line no. and debugging information.

(i) Square Wave START : MVI A, 80H OUT 83H LXI SP, 3000H LOOP : MVI A 00H OUT 80H CALL Delay MVI A FFH OUT 80H

Program Development Tools

Editor To write down the program

source code in Assembly

Language High level language as Embedded

‘C’

Assembler To generate

machine code from Assembly

language complier to generate

machine object code from HLL

Linker To convert

object code to Executable

Code

Debugger T debug the program

checking For errors

Programmer To download /

Burn the Exucatable

Code into 8051 chip.

Simulator / Emulator To test the program by simulation / Emulation

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CALL Delay JMP LOOP HLT (ii) Sawtooth Wave : START : MVI A, 80H OUT 83H LXI SP, 3000H MVI A, 00H LOOP : OUT 80H INRA JMP LOOP HLT (iii) Staircase wave : START : MVI A, 80H OUT 83H LXI SP, 3000H MVI A, 00H LOOP : OUT 80H ADI 40H CALL DELAY JMP LOOP HLT Addressing Modes in 8051

8051 Operates its instructions in six different addressing modes : i) Register addressing mode. ii) Register Specific addressing mode. iii) Immediate addressing mode. iv) Direct addressing mode. v) Register Indirect addressing mode. vi) Indexed addressing mode.

v

t 00H

FFH (5V)

v

t

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1. Register : The addressing Mode in which the data operand is in the Register. Register Ex. MOV A1R5

2. Register Specific : The addressing Mode in which the data operand is in the Specific register. Specific register Ex. CLRA

3. Immediate : The addressing Mode in which the data operand immediately supplied in the instruction it self

Instruction Ex MOV R2, # 2AH

4. Direct : The addressing mode in which the data is in the data memory whose addresses is directly applied in the instruction itself.

Instruction Ex MOV R4, 29H

5. Register Indirect : The addressing mode in which the Data Operand in data memory whose addresses is indirectly specified in the Register

6. Indexed : The addressing mode in which the Data operand is in program memory whose addressed is supplied through Index Register.

Port Description

Port 0 (P0.0 to P0.7) : It is an 8 bit Quasi – bidirectional general purpose input/output port. It has a fan Out of 8. It can be used for digital input/output. It is bit Accessible alternately when the external memory in being access it is used as multiplexed lower address cum bi-directional data bus AD0 to AD7.

Port 1 (P1.0 to P1.7) : It is a Quasi bidirectional 8 bit general purpose input/output part with a fan out of 4. It is a pure input/output port. There is no Alternate function. It is used for digital input/output and it is bit accessible.

Port 2 (P2.0 to P2.7) : It is Quasi bidirectional 8 bit general purpose input/output port with a fan out of 4. It is used for digital input/output and It is bit accessible alternately when external memory is being accessed it is used as Upper address bus A8 to A15.

Data

Data

Data Opcode Data Opcode

Opcode Address

Data

Address Registe Ex MOV A, @R0 Data

D.M

+ DPTR

Index register

Ex MOVC A, @A + DPTR

Data

P.M

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Port 3 (P3.0 to P3.7) : It is a Quasi bidirectional 8 bit general purpose input/output port with a fan out of 4. It is used for digital input/output and It is bit accessible alternately it is used for different function as per the table.

Port 3 : Alternate Functions Pin Signal Details P3.

0 RXD Receive Serial Data Serial input/output

P3.

1

TXD Transmit Serial Data (UART)

P3.2 INT0 External Interrupt Level 0 Interrupts

P3.3 INT1 External Interrupt Level 1 P3.4 T0 Timer 0Ext. clock Input

Timers P3.5 T1 Timer 1Ext. clock Input P3.6 WR Write control for Ext. Data Memory

External Data Memory P3.7 RD Read Control for Ext. Data Memory

Bit Manipulation Instructions Syntax Bytes Operation Example Bit Moves MOVB C, bit

MOV B bit, C 2 2

CY (bit) copy bit to carry (bit) CY copy carry to bit

MOV B C, 8.5H MOV B 97H, C

Bit logical Operations

SET B bit/SET BC CLR bit / CLRC ANL C,bit ANLC, / bit ORL C, bit ORL C,/bit

2 / 1 2 / 1

2 2 2 2

(bit) 1 /CY1 set the bit / set carry (bit) 0/CY 0 Reset the bit / Reset carry CY CY (bit) AND carry with bit & write result to carry

CY CY (bit) AND carry with complement of bit.

CY CY V (bit) OR carry with bit & write result to carry CY CY V (bit) OR carry with Complement of bit.

SETB 82H/SET B C CLR A2H / CLR C ANLC, 92H ANL C, /92H ORL C, B5H

ORL C, / B5H Bit conditional Jumps

JB bit, radd, JNB bit, radd JBC bit, road

3 3

3

If (bit) = 1 THEN PCNEW PCOLD + radd ELSE continue seg IF (bit) = 0 THEN PCNEW PCOLD + radd ELSE continue seg

IF (bit) = 1 THEN PCNEW PCOLD + radd (bit) (bit)

ELSE continue seg.

JB 83H, BACK JNB 94H, AGAIN JBC A1H, NEXT

Single Stepping

8051 does not provide any debugging mechanism or a software interrupt instruction that can be used for providing single step in 8051. However single stepping in 8051 can be achieved by using the hardware timer through loading the timer Bit. The count equivalent to machine cycle required for each instruction would cause time to interrupt after every instruction. After every instruction, it will wait for user input. When the user gives the required input, it will execute next instruction on wait for user input, again. Through this, the user will be able to debug each instruction by instruction, thus making debugging simple. This is how single stepping is used to debug 8051 programs.

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6. (c)

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PCON Register (Power configuration)

PD Set to enter Power Down Mode IDL Set to enter Idle Mode GF1/GF0 General Flags 1 and 0 (user defined) SMOD 0 Single Band Rate (Used by UART)

1 Double Band Rate (Used by UART)

IDL Mode : In IDL mode 8051 CPU logic is turned on However the CLK generator is operating and timer interrupt serial CLK continue to receive the CLK, due to this serial interrupt/Timer interrupt and external are recognized in IDL mode. All the contents of internal RAM, PORTS SFR are intack it consumed about 10% of the normal power. 8051 can come out of IDL mode by any valid interrupt (Time / Serial or external) or by hardware Reset.

Power Down mode : In this mode the oscillator is shut off therefore internal CLK is not generated. CPU and all other circuit of 8051 are shut OFF however 8051 holds on to the values. Internal RAM, PORTS and SFR it consumes 2% of the normal power. In this mode 8051 can come out of power down mode only through the hardware Reset.

IDL and powerdown mode of 8051 are called as power saving modes. They are very useful in 8051 based embedded application where the system runs on batteries and saving power is absolutely necessary.

8085 Based Minimum System Configuration :

uses only 3chips 8085, 8155, 8355 Provides following Resources

i) 8085 8 bit p ii) 256 Bytes RAM iii) 2KB ROM iv) Four input/output Ports of 8 Bits each v) 1 input/output Port of 6 Bits vi) 1 Serial Port (through SID/SOD Pins) vii) 1 Timer channel 14 bit

SNOD GF1 GF0 PD IDL

7 0 PCON

Crystal oscillator Oscillator

PD

Clock Generator

IDL

CPU

Timer / Serial Interrupts

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The minimum system has been decoded for the chip selection using partial decoding technique, chips are selected using only A15 line. Due to some address lines not being consider for decoding their existance shadows in the memory map. 8355 chip has been selected at memory address 0000H, to take case of the RESET Location of 8085 which is 0000H. This ensures that after RESET 8085 starts in ROM there by appropriately executing startup programs.

Device A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Addr

Range

8155

1 0 0 0 0 0 0 0 0 8000

1 1 1 1 1 1 1 1 1 80FF

8355

0 0 0 0 0 0 0 0 0 0 0 0 0000H

0 1 1 1 1 1 1 1 1 1 1 1 0000H

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Documents

2 MC Soln - Vidyalankarvidyalankar.org/file/diploma/prelim_paper_soln/SemV/ETRX/2_MC_Soln.pdfbegins with a start bit which is active low is then followed by a 8 data bits starting