1Analog Electronics material for GATE

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No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical,photocopying, or otherwise without the prior permission of the author.

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Electronics & Communication

Analog Electronics

Copyright By NODIA & COMPANY

Information contained in this book has been obtained by authors, from sources believes to be reliable. However,neither Nodia nor its authors guarantee the accuracy or completeness of any information herein, and Nodia nor itsauthors shall be responsible for any error, omissions, or damages arising out of use of this information. This bookis published with the understanding that Nodia and its authors are supplying information but are not attemptingto render engineering or other professional services.

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Ph : +91 - 141 - 2101150

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email : [email protected]


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ANALOG ELECTRONICS

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2013 ONE MARK

Q. 1 In the circuit shown below what is the output voltage Vout^ hif a silicon transistorQand an ideal op-amp are used?

(A) 15V- (B) 0.7V-

(C) 0.7V+ (D) 15V+

Q. 2 In a voltage-voltage feedback as shown below, which one of the following statementsis TRUE if the gain kis increased?

(A) The input impedance increases and output impedance decreases

(B) The input impedance increases and output impedance also increases

(C) The input impedance decreases and output impedance also decreases

(D) The input impedance decreases and output impedance increases

2013 TWO MARKS

Q. 3 The ac schematic of an NMOS common-source state is shown in the figure below,where part of the biasing circuits has been omitted for simplicity. For the n-channel MOSFET M, the transconductance 1 /mA Vgm= , and body effect and

channel length modulation effect are to be neglected. The lower cutoff frequencyin HZ of the circuit is approximately at


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(A) 8 (B) 32

(C) 50 (D) 200

Q. 4 In the circuit shown below, the knee current of the ideal Zener dioide is 10mA. To maintain 5Vacross RL , the minimum value of RL in Wand the minimumpower rating of the Zener diode in mW, respectively, are

(A) 125 and 125 (B) 125 and 250

(C) 250 and 125 (D) 250 and 250

Q. 5 In the circuit shown below the op-amps are ideal. Then, Voutin Volts is

(A) 4 (B) 6

(C) 8 (D) 10

Q. 6 In the circuit shown below, Q1 has negligible collector-to-emitter saturation

voltage and the diode drops negligible voltage across it under forward bias. If Vccis 5V+ , X and Y are digital signals with 0V as logic 0 and Vccas logic 1, then

the Boolean expression for Zis


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(A) X Y (B) X Y

(C) X Y (D) X Y

Q. 7 A voltage sin t1000 w Volts is applied across Y Z. Assuming ideal diodes, thevoltage measured across W X in Volts, is

(A) sin tw (B) /sin sint t 2w w+_ i

(C) /sin sint t 2w w-^ h (D) 0 for all tQ. 8 In the circuit shown below, the silicon npn transistor Qhas a very high value of

b. The required value of R2in kWto produce 1mAIC = is

(A) 20 (B) 30

(C) 40 (D) 50

2012 ONE MARK

Q. 9 The i-vcharacteristics of the diode in the circuit given below are

i. , .

.

A V

A V

vv

v

50007 07

0 07 1>b=

so g Vm1 1p i0=-

V

i0

1p gm1=-

Vi

i

0 gm1= V Vi1a =p

Sol. 123 Option (B) is correct.

Crossover behavior is characteristic of calss B output stage. Here 2 transistor

are operated one for amplifying +ve going portion and other for -ve going

portion.

Sol. 124 Option (C) is correct.

In Voltage series feedback mode input impedance is given by

Rin (1 )R Ai v vb= +

where feedback factorvb = , openloopgainA v=

and Input impedanceRi=

So, Rin 1 10 (1 0.99 100) 100k3 W# #= + =

Similarly output impedance is given by

ROUT (1 )AR

v v

0

b=

+ output impedanceR0 =

Thus ROUT ( . )1 099 100100 1

# W=

+ =


Regulation VV Vfull loadno load fuel load= -

-- -

%25

30 25 100 20#= -

=

Output resistance125 25W= =

Sol. 126 Option (D) is correct.

This is a voltage shunt feedback as the feedback samples a portion of output

voltage and convert it to current (shunt).

Sol. 127 Option (A) is correct.

In a differential amplifier CMRR is given by

CMRR (1 )V

I R

21 1

T

Q 0

bb

= + +; E

So where R0is the emitter resistance. So CMRR can be improved by increasing

emitter resistance.


We know that rise time (tr) is

tr .f

035H

=

where fH is upper 3 dB frequency. Thus we can obtain upper 3 dB frequency it

rise time is known.


In a BJ T differential amplifier for a linear responseV V


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In a shunt negative feedback amplifier.

Input impedance

Rin (1 )ARi

b= +

where Ri= input impedance of basic amplifier

b= feedback factor

A = open loop gain

So, R R


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Now, if CEis disconnected, resistance REappears in the circuit

Input impedance Rin || [ ( )]R r R1B Eb= + +p

Input impedance increases

Voltage gain A V g Rg R

1 m Em C=

+ Voltage gain decreases.


In common emitter stage input impedance is high, so in cascaded amplifiercommon emitter stage is followed by common base stage.


We know that collect-emitter break down voltage is less than compare to collector

base breakdown voltage.

B VCEO B V< CBOboth avalanche and zener break down. Voltage are higher than B VCEO.So B VCEO

limits the power supply.


If we assume consider the diode in reverse bias thenVnshould be greater thanVP.

V V

P n(so diode cannot be in reverse bias mode).

apply node equation at node a

V V V4

104 1

a a a- + + 2=

V6 10a - 8=

Va 3Volt=


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so current Ib 40 3

410 3= - + -

Ib 1amp410 6

= -

=


Applying node equation at terminal (2) and (3) of OP-amp

V Q V V

5 10a a 0- +

- 0=

V V V2 4a a 0- + - 0=

V0 V3 4a= -

V V V100 10

0a a0- + - 0=

V V V10a a0- + 0=

V11 a V0=

VaV

11

0=

So V0V113 40= -

V118 0 4=-

V0 5.5Volts=-


Circuit with diode forward resistance looks

So the DC current will

IDC ( )R RV

f L

m

p=

+


For the positive half cycle of input diode D1will conduct & D2will be off. In

negative half cycle of input D1will be off & D2conduct so output voltage wave

from across resistor (10 )kW is


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Ammeter will read rmsvalue of current

so Irms ( )half waverectifierRVmp

=

(10 )k

4pW

= .04p

= mA


In given circuit positive feedback is applied in the op-amp., so it works as a

Schmitt trigger.


Gain with out feedback factor is given by V0 kVi=

after connecting feedback impedance Z

given input impedance is very large, so after connecting Zwe have

Ii ZV Vi 0= - V kVi0 =

Ii ZV kVi i= -

input impedance Zin ( )IV

k

Z

1ii= =

-



For the circuit, In balanced condition It will oscillated at a frequency

w

.

10 / secrad

L C

1

10 10 01 10

13 6

5

# # #

= = =- -

In this condition

RR

2

1RR

4

3=

5100

R1

=

R 20k 2 104#W W= =


V0kept constant at V0 6volt=

so current in 50Wresistor

I 509 6W= -

I 60mamp=


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Maximum allowed power dissipation in zener

PZ 300mW=

Maximum current allowed in zener

PZ ( )V I 300 10maxZ Z3

#= = -

& ( )I6 300 10maxZ3

#= = -

& ( ) 50mampI maxZ= =

Given knee current or minimum current in zener

( )I minZ 5mamp=

In given circuit I I IZ L= +

IL I IZ= -

( )I minL ( )I I maxZ= -

(60 50)mamp mamp10= - =

( )I maxL ( )I I minZ= -

(60 5) 55mamp= - =

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1Analog Electronics material for GATE