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Abstract:
April 2009Book of Abstracts
Design and Implementation of 256K-bits Novel 9T SRAM Memoryfor
Enhanced Data Stability and Reduced Leakage Power
Delegates Name
AcademicSupervisors
IndustrialSupervisors
Khushboo Rathore VSD (FT-2007)
P. Chandramohan and Prakash Reddy
Keywords:
As the operating voltage scales down with the technology, the
stability concern for SRAM (Static Random AccessMemory) cells has
moved to the focus center. Moreover, memories have always been the
bottlenecks for high speed andlow power designs. The 9T SRAM with
inherent data stability and capability of reducing the leakage
power is adopted tomeet the stringent requirements of the low power
designs. The circuit techniques used to reduce the power
dissipation anddelay of these components have been explored and
optimum power consumption is obtained.
The building blocks of an SRAM, the row decoders, control block
and the IO blocks are designed and proper sizing isdone using
logical efforts method and mathematical equations. The architecture
of the SRAM is planned and a 32-bit data
bus is selected. The key to data stability is the isolation
between the bitlines and the data node in the 9T SRAM cell.
Thetransistor at the tail of the 9T memcell is implemented with
multiplying factor of 2 to reduce the leakage power comparedto that
of the conventional 6T SRAM cell. The division of read and write
sections provide reduction in the leakage power.To reduce the
overall power dissipation of the chip, the special hierarchical
technique has been adopted for implementation of the 10:1024 row
decoder.
Finally, a 256Kb prototype 9T SRAM has been designed and
implemented. The leakage power of the 9T memcell is0.02261nW which
is nearly 30% less than the conventional 6T SRAM cell. The mask
design of the constituent memory
blocks is done using Virtuoso tool, the DRC and LVS verified
through Hercules/Calibre. The complete 256Kb SRAMmemory comprises
of 2.4 million transistors. The design is simulated at a clock
speed of 3.33GHz. The read access time isfound to be 0.85ns while
the write access time is found to be 1.246ns at pre-layout
simulations. The total leakage power
dissipation is 20.579mW at pre-layout simulations. The SNM for
9T cell is 9.75% more than conventional 6T SRAM cell,with leakage
power reduced to half.
Khushboo [email protected]
Ph. No:0 92431 13071
Low Leakage Power 8Kb SRAM, Layout Design, SNM, Data
Stability
Comparison of pre and post-layoutsimulation for 256Kb SRAM
memory
Block diagram for the 256Kb SRAM
Low power 256Kb SRAM full chip layout Waveform for read/write
access time
