19-4598; Rev 1; 7/09 EVALUATION KIT 16-Bit, RISC, Microcontroller-Based, Ultrasonic ... · 2010. 1. 27. · time-of-flight ultrasonic distance-measuring solution. The device is optimized

General DescriptionThe MAXQ7667 smart system-on-a-chip (SoC) provides atime-of-flight ultrasonic distance-measuring solution. Thedevice is optimized for applications involving large dis-tance measurement with weak input signals or multipletarget identification. The MAXQ7667 features high signal-to-noise ratio achieved by combining flexible electronicswith the intelligence necessary to optimize each functionas environmental and target conditions change.

An integrated burst signal generator and echo receptioncomponents process ultrasonic signals between 25kHzand 100kHz. Echo reception components include a pro-grammable gain low-noise amplifier (LNA), a 16-bitsigma-delta ADC to digitize the received echo signals,and digital signal processing (DSP). DSP limits noisewith a bandpass filter, and creates an echo envelopethrough demodulation and lowpass filtering. Inputreferred noise is a low 0.7µVRMS. A programmablephase-locked loop (PLL) frequency synthesizer suppliesthe reference frequency for the burst generator and theclock for the echo receiver’s digital filter. An embedded16-bit MAXQ20 microcontroller (µC) controls all the pre-ceding functions.

The µC optimizes the burst frequency and receptionfrequency for each transmission at any temperature.The MAXQ7667 achieves smart sensing by monitoringthe echo signals and then actively changing the trans-mitted and received parameters to obtain optimumresults. Digital filtering and burst synthesis do notrequire CPU intervention. This leaves all the CPU poweravailable for echo optimization, communication, diag-nostics, and additional signal processing.

The MAXQ7667 operates with three different powersupply voltages: +5V, +3.3V, and +2.5V. Two internallinear regulators allow operation from a single +5V sup-ply when three external power supplies are not avail-able. Alternatively, the MAXQ7667 can control anexternal pass transistor to allow operation from a singlesupply voltage of +8V to +65V or more, depending onthe external component tolerance. The device is avail-able in a 48-pin LQFP package and is specified tooperate from -40°C to +125°C.

Applications

Features Smart Analog Peripherals

Dedicated Ultrasonic Burst GeneratorEcho Receiving Path (Includes LNA, Sigma-Delta ADC)5-Channel, 12-Bit SAR ADC with 250ksps Sampling RateInternal Bandgap Voltage Reference for theADCs (Also Accepts External Voltage Reference)

Timer/Digital I/O Peripherals High-Performance, Low-Power, 16-Bit RISC Core Program and Data Memory Crystal/Clock Module 16 x 16 Hardware Multiplier with 48-Bit

Accumulator, Single Clock Cycle Power-Management Module JTAG Interface Universal Asynchronous Receiver-Transmitter

(UART) Local Interconnect Network (LIN)

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16-Bit, RISC, Microcontroller-Based,Ultrasonic Distance-Measuring System

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-4598; Rev 1; 7/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any devicemay be simultaneously available through various sales channels. For information about device errata, go to: ww.maxim-ic.com/errata.

Pin Configuration appears at end of data sheet.

See the Detailed Features section for complete list of features.

Note: All devices are specified over the -40°C to +125°C oper-ating temperature range./V denotes an automotive qualified part.+Denotes a lead(Pb)-free/RoHS-compliant package.

PART PIN-PACKAGERAM (KB)

FLASH (KB)

MAXQ7667AACM/V+ 48 LQFP 4 32

Automotive Parking

Vehicle Security

Industrial Processing

Automation

Handheld Devices

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency(fBPF) = 50kHz, CREFBG = CREF = 1µF in parallel with 0.01µF, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unlessotherwise specified. Typical values are at TA = +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

DVDDIO, GATE5, REG3P3, REG2P5 to DGND................................................................-0.3V to +6.0V

AVDD to AGND .....................................................-0.3V to +4.0VDVDD to DGND.....................................................-0.3V to +3.0VDVDDIO to DVDD..................................................-0.3V to +6.0VAVDD to DVDD......................................................-0.3V to +4.0VAGND to DGND.....................................................-0.3V to +0.3VDigital Inputs/Outputs to DGND..........-0.3V to (VDVDDIO + 0.3V)

Analog Inputs/Outputs to AGND............-0.3V to (VAVDD + 0.3V)XIN, XOUT to DGND ..............................-0.3V to (VDVDD + 0.3V)Maximum Current into Any Pin............................................50mAContinuous Power Dissipation (TA = +70°C)

48-Pin LQFP (derate 21.7mW/°C above +70°C).....1739.1mWOperating Temperature Range .........................-40°C to +125°CStorage Temperature Range .............................-60°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ECHO INPUT (Low-Noise Amplifier and Sigma-Delta ADC)

VGA gain adjust = 1.55µVP-P/LSB 5.6 Input-Referred Noise (Note 1) VGA gain adjust = 0.1µVP-P/LSB 0.7

µVRMS

VGA gain adjust = 1.55µVP-P/LSB 80 Minimum Detectable Signal

VGA gain adjust = 0.1µVP-P/LSB 10 µVP-P

VGA gain adjust = 1.55µVP-P/LSB, unclipped

100

Operating Input Range VGA gain adjust = 0.1µVP-P/LSB, unclipped

6.7

mVP-P

VGA gain adjust = 1.55µVP-P/LSB

1.55

Programmable Gain From echo input to bandpass filter in reply to input VGA gain adjust

= 0.1µVP-P/LSB 0.1

µVP-P/LSB

Programmable-Gain Adjust Resolution

(Note 2) 10 %

LNA Bandwidth 150 kHz

ADC Sampling Rate 80 x fBPF kHz

ADC Output Data Rate 10 x fBPF kHz

ADC Output Data Resolution 16 Bits

Echo-Input Resistance RIN For each echo input 14 k

Echo-Input Capacitance 14 pF

Echo-Input DC Bias Voltage VAVDD/2 V

Maximum Overvoltage Recovery Time

Recover from 2VP-P input 10 µs

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ELECTRICAL CHARACTERISTICS (continued)(VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency(fBPF) = 50kHz, CREFBG = CREF = 1µF in parallel with 0.01µF, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unlessotherwise specified. Typical values are at TA = +25°C.)


BANDPASS FILTER

Center Frequency fBPF 25 100 kHz

Passband Width -3dB 0.14 x fBPF kHz

Minimum Stopband Rejection

One decade away from center frequency

-60 dB

Output Data Rate 10 x fBPF ksps

Output Data Resolution 16 Bits

LOWPASS FILTER

Corner Frequency fLPF -3dB 0.1 x fBPF kHz

Rolloff 40 dB/Decade

Output Data Rate 5 x fBPF ksps

Output Data Resolution 16 Bits

SAR ADC

Measurement 12 Resolution

No missing codes 11 Bits

Integral Nonlinearity Tested at 125ksps ±1 ±2 LSB

Differential Nonlinearity Tested at 125ksps -2 +2 LSB

Offset Error ±1 ±3 mV

Offset-Error Drift ±5 µV/°C

Gain Error ±1 %

Gain-Error Temperature Coefficient

±0.4 ppmFS/°C

Input-Referred Noise At ADC inputs 400 µVRMS

Unipolar 0 VREFDifferential Input Range

Bipolar -VREF/2 +VREF/2V

Absolute Input Range 0 VAVDD V

Input Leakage Current ±0.1 µA

Conversion Time 13 ADCCLK cycles at 2MHz 6.5 µs

Input Capacitance 14 pF

Track-and-Hold Acquisition Time

Three ADCCLK cycles at 2MHz 1.5 µs

Turn-On Time Eight ADCCLK cycles at 2MHz 4 µs Conversion Clock fADCCLK 0.5 4 MHz

Conversion Rate fADCCLK = 4MHz (not production tested)

250 ksps

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REFERENCE BUFFER

Offset 5 mV

Minimum Load 2.5 kΩOutput Bypass Capacitor 0.47 µF

EXTERNAL VOLTAGE REFERENCE (Reference Buffer Disabled)

Reference Input Range Applied at REF 1.0 VAVDD V

Reference Input ImpedanceMeasured at REF with the SAR andsigma-delta ADCs running atmaximum frequency

50 kΩ

INTERNAL VOLTAGE REFERENCE (REFBG)

Initial Accuracy 2.45 2.5 2.55 V

Maximum TemperatureCoefficient

100 ppm/°C

Output Impedance 1.1 kΩPower-Supply Rejection Ratio VAVDD = 3.0V to 3.6V 60 dB

Output Noise 0.5 mVRMS

PROGRAMMABLE BURST-FREQUENCY OSCILLATOR

Burst-Frequency Range 0.025 1.335 MHz

Burst-Frequency Resolution 0.1 %

Change from 40kHz to 60kHz 5Burst-Frequency LockingTime Change from 50kHz to 50.5kHz 2

ms

CRYSTAL OSCILLATOR

Tested crystal frequency 16

Minimum crystal frequency 4Frequency Range

External clock input 4 16

MHz

Temperature Stability Excluding crystal 25 ppm/°C

Startup Time 16MHz crystal 10 ms

XIN Input Low Voltage When driven with external clock source0.3 x

VDVDDV

XIN Input High Voltage When driven with external clock source0.7 x

VDVDDV

INTERNAL RC OSCILLATOR

Frequency 13.5 MHz

Initial Accuracy 10.5 %

Temperature Drift TA = TMIN to TMAX 700 ppm

Supply Rejection VDVDD = 2.25V to 2.75V -1.5 %

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Adjustable Frequency Range Using the RCTRM register -40 +40 %

Frequency AdjustmentResolution

0.2 %

SUPPLY VOLTAGE SUPERVISORS

DVDD Reset ThresholdAsserts RESET if VDVDD falls belowthis threshold

2.10 2.25 V

DVDD Interrupt ThresholdGenerates an interrupt if VDVDD fallsbelow this threshold

2.25 2.38 V

Minimum Reset and InterruptThreshold Difference

150 mV

AVDD Interrupt ThresholdGenerates an interrupt if VAVDD fallsbelow this threshold

2.95 3.15 V

DVDDIO Interrupt ThresholdGenerates an interrupt if VDVDDIO fallsbelow this threshold

4.5 4.75 V

Supervisor Operating Range At DVDD 1.5 2.75 V

Supervisor Hysteresis 1 %

RESET Release DelayAfter VDVDD rises above the resetthreshold

35 µs

Power-Up TimeTime from RESET is released to theexecution of the first instruction (serialbootloader off)

1 µs

+5V LINEAR REGULATOR (DVDDIO, GATE5, Requires External Pass Transistor, see the Typical ApplicationCircuit/Functional Diagram)

Regulator Output Voltage At DVDDIO 4.75 5.25 V

GATE5 Output High Voltage ISOURCE = 0µA (no load)VDVDDIO

- 0.1V

GATE5 Output Low Voltage ISINK = 500µA 2 V

GATE5 Output Resistance ISINK = 0µA to 50µA 330 ΩGain Bandwidth DVDDIO to GATE5 1.58 kHz

Gain DVDDIO to GATE5 1700 V/V

GATE5 Slew Rate 4.3 V/ms

Maximum Load CapacitanceMaximum capacitance on DVDDIOwhen using an external pass transistor

1 µF

+3.3V LINEAR REGULATOR (REG3P3)

REG3P3 Output Voltage 3.15 3.45 V

Load Current 50 mA

Output Short-Circuit Current REG3P3 shorted to AGND 150 mA

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+2.5V LINEAR REGULATOR (REG2P5)

REG2P5 Output Voltage 2.38 2.62 V

Load Current 50 mA

Output Short-Circuit Current REG2P5 shorted to DGND 100 mA

POWER REQUIREMENTS

DVDD 2.25 2.5 2.75

AVDD 3.00 3.3 3.6 Supply Voltage Range

DVDDIO 4.5 5.0 5.5

V

All analog functions enabled 12 18 mA

All analog functions disabled 3 10 µA

LNA 2.4

Sigma-delta ADC 12 mA

SAR ADC, 250ksps, fADCCLK = 4MHz

600

PLL 300

Supply voltage supervisors

3

Internal voltage reference

220

Reference buffer 300

µA

AVDD Supply Current Incremental AVDD supply current

Bias (any AVDD module enabled)

1.5 mA

DVDD Supply Current 11 mA

DVDDIO Supply Current 2.5 mA

DIGITAL INPUTS (GPIO, UART, JTAG, SPI™)

Input High Voltage VDVDDIO

- 1 V

Input Low Voltage 0.8 V

Input Hysteresis VDVDDIO = 5.0V 500 mV

Input Leakage Current Digital input voltage = DGND or DVDDIO, pullup disabled

±0.01 ±1 µA

Pullup/Pulldown Resistance Pulled up to DVDDIO internally, pulled down to DGND internally

150 k

Input Capacitance 15 pF

SPI is a trademark of Motorola, Inc.

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DIGITAL OUTPUTS (GPIO, UART, JTAG, SPI)

ISINK = 0.5mA, drive strength = low 0.4 Output Low Voltage

ISINK = 1.0mA, drive strength = high 0.4 V

ISOURCE = 0.5mA, drive strength = low

VDVDDIO - 0.5

Output High Voltage ISOURCE = 1.0mA, drive strength = high

VDVDDIO - 0.5

V

Drive strength = low 880 Maximum Output Impedance Drive strength = high 450

Three-State Leakage ±0.01 ±1 µA

Three-State Capacitance 15 pF

BURST OUTPUT

Output Low Voltage ISINK = 8mA 0.4 V

Output High Voltage ISOURCE = 8mA VDVDDIO -

0.5 V

Drive strength = low 90 Maximum Output Impedance Drive strength = high 45

Three-State Leakage ±0.01 ±1 µA

Three-State Capacitance 15 pF

Short-Circuit Current Burst drive set to high 50 mA

RESET

Internal Pullup Resistance Pulled up to DVDDIO 120 k

Output Low Voltage ISINK = 0.5mA 0.4 V

Output High Voltage No external load VDVDDIO -

0.5 V

Input Low Voltage When driven by external source 0.8 V

Input High Voltage When driven by external source VDVDDIO -

1 V

UART/LIN INTERFACE (UTX, URX)

Asynchronous mode (system clock/32)

500

Synchronous mode (system clock/8) 2000 UART Baud Rates

LIN 2.0 compatibility (Note 3) 1 20

kbps

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8 _______________________________________________________________________________________

Note 1: Noise measured at bandpass filter output with ECHO+ and ECHO- shorted divided by the gain with fBPF = 50kHz.Note 2: Gain adjust resolution typically ranges between 6.25% and 12.5%.Note 3: LIN 2.0 specifies a maximim data rate of 20kbps. Higher data rates could be possible with compatible devices and suitable

line conditions.



SPI INTERFACE TIMING (Figures 11 and 12)

SPI Master OperatingFrequency

1/tMCK 0.5 x fSYSCLK 8 MHz

SPI Slave OperatingFrequency

1/tSCK 0.25 x fSYSCLK 4 MHz

SCLK Output Pulse-WidthHigh/Low

tMCH,tMCL

tMCK/2- 25

ns

MOSI Output Hold TimeAfter SCLK Sample Edge

tMOHtMCK/2

- 25ns

MOSI Output Valid to SampleEdge

tMOVtMCK/2

- 25ns

MISO Input Valid to SCLKSample Edge

tMIS 25 ns

MISO Input Hold Time AfterSCLK Sample Edge

tMIH 0 ns

SCLK Inactive to MOSIInactive

tMLH 0 ns

SCLK Input Pulse-WidthHigh/Low

tSCH,tSCL

tSCK/2 ns

SS Active to First Shift Edge tSSE 4tSYSCLK ns

MOSI Input Setup Time toSCLK Sample Edge

tSIS 25 ns

MOSI Input Hold Time AfterSCLK Sample Edge

tSIH 25 ns

MISO Output Valid AfterSCLK Shift Edge Transition

tSOV 50 ns

SS Inactive Duration tSSHtSYSCLK +

25ns

SCLK Inactive to SS RisingEdge

tSDtSYSCLK +

25ns

FLASH PROGRAMMING

Mass erase 200Flash Erase Time

Page erase (512 bytes per page) 20ms

Flash Programming Time 20µs per word 657 ms

Write/Erase Cycles 10,000 Cycles

Data Retention Average temperature = +85°C 15 Years

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BURST OUTPUT FREQUENCY vs. TEMPERATURE

MAX

Q766

7 to

c01

TEMPERATURE (°C)

BURS

T OU

TPUT

FRE

QUEN

CY (k

Hz)

5025 100750-25

49.96

49.97

49.98

49.99

50.00

50.01

50.02

50.03

50.04

50.05

49.95-50 125

USING PLL

LOWPASS FILTER OUTPUTvs. ECHO INPUT AMPLITUDE

MAX

Q766

7 to

c02

ECHO INPUT AMPLITUDE (VP-P)

LPF

OUTP

UT (L

SB)

0.040.02 0.080.06

24,576

32,768

8192

16,384

40,960

49,152

57,344

65,536

00 0.10

PROGRAMMABLE ECHO GAIN = MINIMUM

LOWPASS FILTER OUTPUTvs. ECHO INPUT FREQUENCY

MAX

Q766

7 to

c03

ECHO INPUT FREQUENCY (kHz)

LPF

OUTP

UT (L

SB)

5540 8570

1000

100

10,000

100,000

1025 100

PROGRAMMABLE ECHO GAIN = MINIMUMECHO INPUT AMPLITUDE = 20mVP-P

BANDPASS FILTER OUTPUT NOISE FLOOR vs. BANDPASS FILTER CENTER FREQUENCY

MAX

Q766

7 to

c04

FREQUENCY (kHz)

BAND

PASS

FIL

TER

OUTP

UT (L

SBRM

S)

806040

9

3

6

12

15

020 100

RECEIVE PATH GAIN AT MAXIMUM

TA = +105°C

TA = +25°C

TA = -40°C

RECEIVE PATH RESPONSE TIME(ECHO INPUT TO LOWPASS FILTER OUTPUT)

MAX

Q766

7 to

c05

TIME (µs)

ADC

COUN

T (L

SB)

400200 800600

6000

4000

10,000

2000

8000

14,000

12,000

16,000

00 1000

MINIMUM ECHO GAIN20mVP-P ECHO AMPLITUDE

50kHz ECHO FREQUENCY250ksps

INPUT ON

INPUT OFF

LOWPASS FILTER OUTPUT RIPPLE vs. TIME

MAX

Q766

7 to

c06

TIME (ms)

LPF

OUTP

UT (L

SB)

2 4 6 108

12,500

12,000

14,500

11,500

14,000

10,500

13,000

11,000

13,500

15,000

10,0000 12

MINIMUM ECHO GAIN20mVP-P ECHO AMPLITUDE50kHz ECHO FREQUENCY250ksps

SAR ADC OFFSET ERRORvs. TEMPERATURE

MAX

Q766

7 to

c07

TEMPERATURE (°C)

OFFS

ET E

RROR

(mV)

0 7525-25 10050

0.5

-0.5

0

1.0

1.5

2.0

-1.0-50 125

VAVDD = 3.3V

VAVDD = 3.6V

VAVDD = 3V

Typical Operating Characteristics(VDVDDIO = +5V, VAVDD = +3.3V, VDVDD = +2.5V, fSYSCLK = 16MHz, burst frequency = bandpass frequency = 50kHz, TA = +25°C,unless otherwise noted.)

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10 ______________________________________________________________________________________

SAR ADC GAIN ERRORvs. TEMPERATURE

MAX

Q766

7 to

c08

TEMPERATURE (°C)

GAIN

ERR

OR (m

V)

0 7525-25 10050

2.0

1.0

1.5

2.5

3.0

0.5-50 125

VAVDD = 3.3V

VAVDD = 3.6V

VAVDD = 3V

SAR ADC INL vs. CODE

MAX

Q766

7 to

c09

CODE

INL

(LSB

)

307220481024

0

-0.5

1.5

-1.0

1.0

-1.5

0.5

2.0

-2.00 409625601536512 3584

SAR ADC DNL vs. CODE

MAX

Q766

7 to

c10

CODE

DNL

(LSB

)

307220481024

0

-0.5

1.5

-1.0

1.0

-1.5

0.5

2.0

-2.00 409625601536512 3584

REFERENCE OUTPUT VOLTAGEvs. SUPPLY VOLTAGE

MAX

Q766

7 to

c11

AVDD SUPPLY VOLTAGE (V)

REF

OUTP

UT V

OLTA

GE (V

)

3.53.33.2

2.516

2.515

2.519

2.514

2.518

2.513

2.517

2.520

2.5123.0 3.63.1 3.4

REFERENCE OUTPUT VOLTAGEvs. TEMPERATURE

MAX

Q766

7 to

c12

TEMPERATURE (°C)

REF

OUTP

UT V

OLTA

GE (V

)

0 25 10075

2.53

2.51

2.49

2.47

2.55

2.45-50 12550-25

SUPPLY BROWNOUT THRESHOLDSvs. TEMPERATURE

MAX

Q766

7 to

c13

TEMPERATURE (°C)

SUPP

LY T

HRES

HOLD

(V)

25 1000-25 75

4.5

4.0

3.5

3.0

2.5

5.0

2.0-50 12550

DVDDIO INTERRUPT

AVDD INTERRUPT

DVDD INTERRUPTDVDD RESET

TEMPERATURE (°C)25 1000-25 75-50 12550

REGULATOR OUTPUT VOLTAGEvs. TEMPERATURE

MAX

Q766

7 to

c14

REGU

LATO

R OU

TPUT

VOL

TAGE

(V)

4.5

4.0

3.5

3.0

2.5

5.0

2.0

DVDDIO

AVDD

DVDD

Typical Operating Characteristics (continued)(VDVDDIO = +5V, VAVDD = +3.3V, VDVDD = +2.5V, fSYSCLK = 16MHz, burst frequency = bandpass frequency = 50kHz, TA = +25°C,unless otherwise noted.)

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REG2P5 REGULATOR OUTPUT VOLTAGEvs. LOAD CURRENT

MAX

Q766

7 to

c17

REG2P5 LOAD CURRENT (mA)

REG2

P5 R

EGUL

ATOR

OUT

PUT

VOLT

AGE

(V)

6040

2.5

2.0

1.5

1.0

0.5

3.0

00 12010020 80

RC OSCILLATOR FREQUENCYvs. TEMPERATURE

MAX

Q766

7 to

c18

TEMPERATURE (°C)

RC O

SCIL

LATO

R FR

EQUE

NCY

(MHz

)

0 7525-25 10050

13.5

12.5

13.0

14.0

14.5

15.0

12.0-50 125

VDVDD = 2.25V

VDVDD = 2.75V

VDVDD = 2.50V

DVDDIO REGULATOR OUTPUT VOLTAGEvs. LOAD CURRENT

MAX

Q766

7 to

c15

DVDDIO LOAD CURRENT (mA)

DVDD

IO R

EGUL

ATOR

OUT

PUT

VOLT

AGE

(V)

10050

5.0

4.5

4.0

3.5

5.5

3.00 200150

DRAIN = 8V

DRAIN = 14V

EXTERNAL VOLTAGE SOURCE CONNECTEDTO THE DRAIN OF EXTERNAL PASSTRANSISTOR BSP129

REG3P3 REGULATOR OUTPUT VOLTAGEvs. LOAD CURRENT

MAX

Q766

7 to

c16

REG3P3 LOAD CURRENT (mA)RE

G3P3

REG

ULAT

OR O

UTPU

T VO

LTAG

E (V

)

6040

3.0

2.5

2.0

1.5

1.0

0.5

3.5

00 12010020 80

Typical Operating Characteristics (continued)(VDVDDIO = +5V, VAVDD = +3.3V, VDVDD = +2.5V, fSYSCLK = 16MHz, burst frequency = bandpass frequency = 50kHz, TA = +25°C,unless otherwise noted.)

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Pin DescriptionPIN NAME FUNCTION

1 P1.3/TCK Port 1 Data 3/JTAG Serial Clock Input. P1.3 is a general-purpose digital I/O. TCK is the JTAG serial test clock input. Refer to the MAXQ7667 User’s Guide Sections 5 and 11.

2 P1.4/MOSI Port 1 Data 4/SPI Serial Data Output. P1.4 is a general-purpose digital I/O. MOSI is the master output, slave input for the SPI interface. Refer to the MAXQ7667 User’s Guide Sections 5 and 9.

3 P1.5/MISO Port 1 Data 5/SPI Serial Data Input. P1.5 is a general-purpose digital I/O. MISO is the master input, slave output for the SPI interface. Refer to the MAXQ7667 User’s Guide Sections 5 and 9.

4 P1.6/SCLK Port 1 Data 6/SPI Serial Clock Output. P1.6 is a general-purpose digital I/O. SCLK is the serial clock for the SPI interface. SCLK is an input when operating as a slave and an output when operating as a master. Refer to the MAXQ7667 User’s Guide Sections 5 and 9.

5 P1.7/SYNC/SS

Port 1 Data 7/Schedule Timer Sync Input/SPI Slave Select. P1.7 is a general-purpose digital I/O. A rising edge on the SYNC input resets the schedule timer. In SPI slave mode, SS is the SPI slave-select input. In SPI master mode, use SS or a GPIO to manually select an external slave. Refer to the MAXQ7667 User’s Guide Sections 5, 7, and 9.

6, 19, 42 DVDD Digital Supply Voltage. Connect DVDD directly to a +2.5V external source or to REG2P5 output for single supply operation. Bypass DVDD to DGND with a 0.1µF capacitor as close as possible to the device. Connect all DVDD nodes together.

7, 18, 43 DGND Digital Ground. Connect all DGND nodes together. Connect to AGND at a single point.

8, 17, 44 DVDDIO Digital I/O Supply Voltage. DVDDIO powers all digital I/Os except for XIN and XOUT. Bypass DVDDIO to DGND with a 0.1µF capacitor as close as possible to the device. Connect all DVDDIO nodes together.

9 P0.0/URX Port 0 Data 0/UART Receive Data Input. P0.0 is a general-purpose digital I/O. URX is a UART or LIN data receive input. Refer to the MAXQ7667 User’s Guide Sections 5 and 8.

10 P0.1/UTX Port 0 Data 1/UART Transmit Data Output. P0.1 is a general-purpose digital I/O. UTX is a UART or LIN data transmit output. Refer to the MAXQ7667 User’s Guide Sections 5 and 8.

11 P0.2/TXENPort 0 Data 2/UART Transmit Output. P0.2 is a general-purpose digital I/O. TXEN asserts low when the UART is transmitting. Use TXEN to enable an external LIN/UART transceiver. Refer to the MAXQ7667 User’s Guide Sections 5 and 8.

12P0.3/T0/ ADCCTL

Port 0 Data 3/Timer 0 I/O/ADC Control Input. P0.3 is a general-purpose digital I/O. T0 is the primary Type 2 timer/counter 0 output or input. ADCCTL is a sampling/conversion trigger input for the SAR ADC. Refer to the MAXQ7667 User’s Guide Sections 5, 6, and 14.

13 P0.4/T0B Port 0 Data 4/Timer 0B I/O/Comparator Output. P0.4 is a general-purpose digital I/O. T0B is the secondary Type 2 timer/counter 0 output or input. Refer to the MAXQ7667 User’s Guide Sections 5 and 6.

14 P0.5/T1 Port 0 Data 5/Timer 1 I/O. P0.5 is a general-purpose digital I/O. T1 is the primary Type 2 timer/counter 1 output or input. Refer to the MAXQ7667 User’s Guide Sections 5 and 6.

15 P0.6/T2 Port 0 Data 6/Timer 2 I/O. P0.6 is a general-purpose digital I/O. T2 is the primary Type 2 timer/counter 2 output or input. Refer to the MAXQ7667 User’s Guide Sections 5 and 6.

16 P0.7/T2B Port 0 Data 7/Timer 2B I/O. P0.7 is a general-purpose digital I/O. T2B is the secondary Type 2 timer/counter 2 output or input. Refer to the MAXQ7667 User’s Guide Sections 5 and 6.

20 XIN Crystal Oscillator Input. Connect an external crystal or resonator between XIN and XOUT. When using an external clock source drive XIN with 2.5V level clock while leaving XOUT unconnected. Connect XIN to DGND when an external clock source is not used.

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Pin Description (continued)PIN NAME FUNCTION

21 XOUT Crystal Oscillator Output. Connect an external crystal or resonator between XIN and XOUT. Leave XOUT unconnected when driving XIN with a 2.5V level clock or when an external clock source is not used.

22 REG2P5 +2.5V Voltage Regulator Output

23 REG3P3 +3.3V Voltage Regulator Output

24 GATE5 +5V DVDDIO Voltage Regulator Control Output. GATE5 controls an external npn or nMOS transistor that passes power to DVDDIO.

25 RESETReset Input/Output. RESET is open drain with an internal pullup resistor to DVDDIO. Internal circuitry pulls RESET low when VDVDDIO falls below its brownout reset value or watchdog reset is enabled and the watchdog timeout period expires. Force RESET low externally for manual reset.

26 FILT PLL VCO Control Input. Connect external filter components on FILT for the internal PLL circuit. See the Typical Application Circuit/Functional Diagram.

27, 32 AVDD Analog Supply Voltage. Connect all AVDD inputs directly to a +3.3V source or to REG3P3 for self-powered operation. Bypass each AVDD to AGND with a 0.1µF capacitor as close as possible to the device.

28, 31, 33 AGND Analog Ground. Connect all AGND nodes together. Connect to DGND at a single point.

29 ECHON Negative Echo Input. AC-couple ECHON to an ultrasonic transducer.

30 ECHOP Positive Echo Input. AC-couple ECHOP to an ultrasonic transducer.

34 REF

ADC Reference Input/Reference Buffer Output. When using the internal reference, the buffered bandgap reference voltage (VREF) is provided for both SAR and sigma-delta ADCs. When using an external reference, apply an external voltage source ranging between 1V and VAVDD at REF. Disable the reference buffer when applying an external reference at REF. Bypass REF to AGND with a 0.47µF capacitor.

35 REFBG +2.5V Reference Output/Reference Buffer Input. Bypass to AGND with a 0.47µF capacitor.

36 AIN0 SAR ADC Input 0. AIN0 pairs with AIN1 in differential mode.




40 AIN4 SAR ADC Input 4

41 N.C. No Connection. Internally connected. Leave unconnected.

45 BURST Burst Output. Burst is the ultrasonic transducer excitation pulse output. BURST remains in three-state mode on power-up.

46 P1.0/TDO Port 1 Data 0/JTAG Output. P1.0 is a general-purpose digital I/O. TDO is the JTAG serial data output. Refer to the MAXQ7667 User’s Guide Sections 5 and 11.

47 P1.1/TMS Port 1 Data 1/JTAG Test Mode-Select Input. P1.1 is a general-purpose digital I/O. TMS is the JTAG mode-select input. Refer to the MAXQ7667 User’s Guide Sections 5 and 11.

48 P1.2/TDI Port 1 Data 2/JTAG Input. P1.2 is a general-purpose digital I/O. TDI is the JTAG serial data input. Refer to the MAXQ7667 User’s Guide Sections 5 and 11.

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BURST ENABLEBURST

TRANSDUCER

ECHON

ECHOP

GATE5

DVDDIO

BSP129

BURST OUTPUT DUTY CYCLE AND PULSE COUNTER

2mVP-P0V

SIGMA- DELTA ADC

12-BIT SAR ADC

0.47µF 0.47µF

VOLTAGE REFERENCE

THRESHOLD ADJUST

MAXQ20 RISC µC

PROGRAMMABLE PLL

CLOCK PRESCALER DIVIDE BY 1 TO 128

DIGITAL BANDPASS

FILTERLNA

SCHEDULE TIMER

CRYSTAL OSCILLATOR

13.5MHz RC

OSCILLATORWATCHDOGPOR/

BROWNOUT

INTERFACE MODULE

LIN TRANSCEIVER

CONN

ECTO

R

TIMER 2

PO.6/T2

PO.7/T2B

PO.3/T0/ADCCTL

PO.4/T0B

PO.5/T1

RESETAGND

TIMER 1 TIMER 0

FULL- WAVE

RECTIFIER

DIGITAL LOWPASS

FILTER

INTERRUPT

FIFO

ROM

FLASH

RAM

16 x 16 HW MULT

PLUS ACCUM

AIN0

REFREFBG

AIN1AIN2

AIN3 THERMISTOR

BATTERY+

AIN4

FILT

24kΩ

33nF

330pF

AVDD

20pF

XIN XOUT

16MHz

0.1µF

0.01µF

0.01µF

470pF

470pF

20pF

REG3P3

AVDD0.1µF

REG2P5

DVDD

DGND

GPIO/JTAG

GPIO/SPI

P0.0/URXRx

LIN

+8V TO +20V

LIN

GND

V+

TxP0.1/UTX

0.1µF

MAXQ7667

Typical Application Circuit/Functional Diagram

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Detailed Features Smart Analog Peripherals

Dedicated Ultrasonic Burst GeneratorEcho Receiving Path

Low-Noise AmplifierTime Variable Gain Amplifier16-Bit Sigma-Delta ADCDigital Bandpass FilterFull-Wave Rectifier and Digital Lowpass Filter8-Deep, 16-Bit Wide FIFO Simplifies Real-TimeProcessingMagnitude Comparator

5-Channel, 12-Bit SAR ADC with 250kspsSampling RateInternal Bandgap Voltage Reference for the ADCs(Also Accepts External Voltage Reference)

Timer/Digital I/O PeripheralsSPI InterfaceThree 16-Bit (or Six 8-Bit) Programmable Type 2Timers/Counters16-Bit Schedule TimerProgrammable Watchdog Timer16 General-Purpose Digital I/Os withMultipurpose Capability

High-Performance, Low-Power, 16-Bit RISC Core1MHz–16MHz Operation, Approaching 1MIPS per1MHzLow Power (< 2.5mA/MIPS, DVDD = +2.5V)16-Bit Instruction Word, 16-Bit Data Bus33 Instructions (Most Require Only One ClockCycle)16-Level Hardware StackThree Independent Data Pointers with AutomaticIncrement/Decrement

Program and Data MemoryInternal 32KB Program FlashInternal 4KB Data RAMInternal 8KB Utility ROM

Crystal/Clock Module1MHz–16MHz External Crystal Oscillator13.5MHz Internal RC OscillatorExternal Clock Source Operation

16 x 16 Hardware Multiplier with 48-BitAccumulator, Single Clock Cycle Operation

Power-Management ModulePower-On Reset (POR)Power-Supply Supervisor/Brownout Detection forAll SuppliesOn-Chip +5V, +3.3V, and +2.5V Regulators forSingle Supply Operation

JTAG InterfaceExtensive Debug and Emulation SupportIn-System Test CapabilityFlash-Memory-Program Download

UARTSynchronous and Asynchronous TransfersIndependent Baud-Rate Generator2-Wire InterfaceTransmit and Receive FIFOs

LINSupports LIN 1.3, LIN 2.0, and SAE J2602Automatic Baud-Rate Detection and LIN FrameSynchronizationUp to 64 Bytes Frame LengthAutomatic Calculation of Standard (LIN 1.3) andEnhanced (LIN 2.0) Checksums

7mm x 7mm, 48-Pin LQFP Package -40°C to +125°C Operating Temperature Range

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16 ______________________________________________________________________________________

Detailed DescriptionThe ultrasonic distance-measurement peripherals in theMAXQ7667 include a burst signal generator foracoustic transmission and mixed signal circuits foramplifying and digitizing echo signals ranging between25kHz and 100kHz. The burst signal is a square wavewith adjustable duty cycle and pulse count. The burst isderived either directly from the system clock or from aprogrammable PLL locked to the system clock. TheMAXQ7667 effectively digitizes the echo signalsreceived at the ECHOP and ECHON inputs using anLNA, sigma-delta ADC with variable analog gain ampli-fier, noise-limiting digital bandpass filter, digital full-wave rectifier, and a digital lowpass filter (see theTypical Application Circuit/Functional Diagram). Thedevice detects echo signals at the burst frequency withamplitudes ranging from 10µVP-P to 100mVP-P. Echoesgreater than 100mVP-P and less than 2VP-P are internal-ly clipped but do not saturate the receiver. To optimizeecho reception, the clock used for processing the echolocks to the burst frequency. The MAXQ7667’s burstgenerator can generate higher frequencies, but themaximum usable frequency for the echo receive path is100kHz . For applications requiring transducer frequen-cies above 100kHz, implement an external echoreceive path. The SAR ADC can then digitize the fil-tered echo envelope.

An integrated 16-bit RISC µC (MAXQ20) provides tim-ing control, signal processing, and data I/O. The 16-bitHarvard architecture RISC core executes most instruc-tions in a single clock cycle from instruction fetch tocycle completion. The MAXQ20 provides optimal per-formance for noise-sensitive analog applications.

The MAXQ7667 includes a 13.5MHz RC oscillator,external crystal oscillator, watchdog timer, scheduletimer, three general-purpose Type 2 timers/counters,two 8-bit GPIO ports, SPI interface, JTAG interface, LINcapable UART interface, 12-bit SAR ADC with five mul-tiplexed input channels, supply-voltage monitors, and avoltage reference for communication, diagnostics, andmiscellaneous support.

Burst ControllerThe MAXQ7667 provides a square-wave burst signal atthe BURST output. Use the burst control to transmit anultrasonic signal. Typical applications use the burst sig-nal to switch an external transistor that drives a high-voltage transformer, which excites the transducer (seethe Typical Application Circuit/Functional Diagram).Use software to configure the duty cycle, frequency,number of pulses, and drive current of the burst. SeeSection 17 of the MAXQ7667 User’s Guide.

Derive the burst signal either directly from the systemclock or from a programmable oscillator phase lockedto the system clock (Figure 1). Using the system clocklimits the burst frequency to one of 16 choices. Integerdivision of the system clock generates these 16 fre-quencies. The PLL allows a fractional division of thesystem clock. Any frequency within the PLL range isselectable to a resolution of 0.13% or better.

When using the internal PLL, connect external filtercomponents (C1, R1, and C2) to FILT as shown inFigure 1. These components filter the analog voltagethat controls the VCO in the PLL. The filter componentvalues shown in the figure are suitable for the entirePLL frequency range.

MAXQ7667

C2330pF

SYSTEMCLOCK

(fSYSCLK)

ECHORECEIVECLOCK

PLL

C133nF

FILT

R124kΩ

PWM

2mVP-PDIAGNOSTIC

BURST

1

0

BTRN.10:BCKS

BPH[9:0]

PLLF[10:9]:PLLC[1:0]

BTRN[15:12]:BDIV[3:0]

BTRN[7:0]:BCNT[7:0]

BPH.15:BSTT

BTRN.9:BTRI

BPH.14:BDSBTRN.11:BPOL

BTRN.8:BGT

BURST

PLLF[8:0]

BURST CLOCKGENERATOR

RECEIVE CLOCKPRESCALE

Figure 1. Burst Transmission Stage

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Echo Receive PathLow-Noise Amplifier (LNA)

The LNA provides a 40V/V fixed gain to the input signal.The differential inputs of the LNA are ECHOP andECHON. For proper biasing of the LNA, AC-couple thetransducer or any external circuitry to ECHOP andECHON. For a single-ended input signal, AC-couple thesignal to ECHOP with a 0.01µF capacitor and connectECHON to AGND through a 0.01µF capacitor placed asclose as possible to the signal source. The outputs of theLNA connect to the inputs of a 16-bit sigma-delta ADCand can connect internally to the AIN0 and AIN1 inputsof the SAR ADC for external monitoring (Figure 2).

Diagnostic SignalsAn analog multiplexer located at the input of the LNAselects one of three possible signals for processing bythe echo receive path; the normal echo signal AC-cou-pled to the ECHOP and ECHON inputs, 0V signal, or a2mVP-P internally generated signal (Figure 2). The2mVP-P square-wave signal, with frequency and dutycycle matching the burst signal, allows the echoreceive chain to process a simulated echo.

MAXQ7667

0.47µF

AGND

REFGB

0.47µF

TO EXTERNAL VOLTAGEREFERENCE

AGND

REF

VARIABLEGAIN SIGMA-DELTA ADC

FIFO8 x 16

FIFOCONTROL

BANDPASSFILTER

CLOCKCONTROL

ECHORECEIVECLOCK

RCVC[4:0]:RCVGN[4:0]RCVC[7:6]:LNAISEL[1:0]

RCVC.8:LNAOSEL

BPFI[15:0]

APE.13:RSARE

2.5VBANDGAP REF

APE.12:BGE

FULL-WAVERECTIFIER PLUSLOWPASS FILTER

R*

R*

*R = ECHO INPUT RESISTANCE. SEE THE ELECTRICAL CHARACTERISTICS SECTION.

40R*

AIN0TO SAR ADC

AIN1

0V

2mVP-P

40R*

LNAAVDD/2

ECHOP

ECHON

MUX

BPFO[15:0]

LPFD[15:0]

CMPC[14:0]:CMPH[14:0]

CMPT[15:0]

LPFC[15:12]:FFIL[3:0]

LPFC[2.0]:FFLS[2:0]LPFC.7:FFOV

ASR.2:LPFFL

LPFC[11:8]:FFDP[3:0]

CMPC.15:CMPP

ASR.12:CMPLVL

AIE.3:CMPIE

LPFF[15:0]

ASR.3:CMPI

COM

PARA

TOR

AIE.1:LPFIE

ASR.1:LPFRDY

LPFC.3:FFLD

TIMER 0TIMER 1TIMER 2

DATA READYINTERRUPT

AIE.2:LFLIE

Figure 2. Echo Receive Path


______________________________________________________________________________________ 17

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18 ______________________________________________________________________________________

Sigma-Delta ADCThe MAXQ7667 features a 16-bit sigma-delta ADC withan analog gain adjustable from 38dB to 60dB (includ-ing the fixed LNA gain) with a maximum gain step of12.5% (typical). Gain changes settle within one ADCconversion. Use software to create a virtual time vari-able gain amplifier. A digital bandpass and lowpass fil-ters remove switching glitches and DC offset at theoutput of the ADC.

In a typical application, the software sets the gain to alow value when the burst is first sent and increases thegain as the time from when the burst was sent increas-es. As a result, strong echoes from nearby objects areprocessed without clipping while small signals from dis-tant objects are processed with the maximum gain. TheADC samples the amplified echo signal from the LNA at80 times the burst output frequency. The ADC providesconversion results at a data rate equal to 10 times theburst output frequency. The ADC conversion resultsalso load to an 8-deep first-in-first-out (FIFO) at thenative data rate or a separate time base without loadingthe CPU.

Digital Bandpass FilterThe digital bandpass filter has a center frequency thattracks the burst output frequency. The bandpass widthis 14% of the center frequency. The bandpass filter pro-vides the 16-bit output data at a data rate equal to 10times the burst output frequency.

Full-Wave RectifierThe full-wave rectifier detects the envelope of the digitalbandwidth filter output to generate a DC output propor-tional to the peak-to-peak amplitude of the input signal.Full-wave rectification allows the digital lowpass filter torespond faster without excessive ripple.

Digital Lowpass FilterThe lowpass filter removes the ripple from the full-wavedetector output. The output of the lowpass filter is avail-able at a data rate equal to five times the burst outputfrequency. The corner frequency is 1/5 the burst fre-quency with approximately 40dB per decade rolloff.The 16-bit output data of the lowpass filter is stored in aFIFO register with a depth of eight samples. TheMAXQ7667 allows data transfer from the lowpass filter

SARC[2:0]:SARS[2:0]

SARC[11:9]:SARMX[2:0]

REFERENCE TOSIGMA-DELTA ADC

ADC DATAREADY INTERRUPT

ASR.0:SARRDY

APE.12:BGE

APE.14:RBUFE

AIE.0:SARIE

BANDGAPREF

SARC.3:SARBY

SARC.6:SARDUL

SARC.4:SARASD

SARC.7:SARBIP

SARC.8:SARDIF

OSCC[3:2]:SARCD[1:0]

ADCCLOCK

DIV

TIMER 0TIMER 1TIMER 2

APE.4:SARE ADCCLK

AVDDVREF

MUX

SARC[11:9]:SARMX[2:0]

12-BITADC

AIN0

MUX

AIN1AIN2AIN3

DATA BUS[15:0]

AIN4VREF

AGND

AVDDAGND

REFBG

ADCCTL

REF

SYSCLK

BUFx1.0

Figure 3. SAR ADC Block Diagram

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______________________________________________________________________________________ 19

output to the FIFO automatically each time the lowpassfilter output updates, through the control of one of thetimer outputs, or through software. The device includesa FIFO depth counter with programmable interrupt lev-els and generates an interrupt if a FIFO overflow condi-tion occurs. The output of the digital lowpass filterconnects to a digital comparator that can generate aninterrupt for a specified echo signal level.

Digital Comparator and Threshold AdjustThe digital comparator output asserts when the echoamplitude at the output of the digital lowpass filter cross-es a given threshold. The comparator’s threshold level,hysteresis, and interrupt polarity are programmable.

SAR ADCThe MAXQ7667 incorporates a 12-bit unbuffered SARADC with sample-and-hold and conversion rate up to250ksps. The ADC allows measurements of tempera-

ture, battery voltage, or other parameters using five sin-gle-ended or two fully differential analog inputs(AIN0–AIN4). All of the analog inputs have a range of 0to VREF in unipolar mode and ±VREF/2 in bipolar mode.

The SAR ADC supports three different conversion startsources: timers, ADC control input (ADCCTL), and soft-ware write. The conversion start source triggers theADC acquisition and conversion. The system clock pro-vides the ADC clock frequency programmable to 1/2,1/4, 1/8, or 1/16 of the system clock. Use internalbandgap reference, external reference, or AVDD forvoltage reference of the SAR ADC. Figure 3 shows asimplified block diagram of the SAR ADC.

The output of the SAR ADC is straight binary in unipolarmode and two’s complement in bipolar mode. Figures 4and 5 show the ADC transfer functions in unipolarmode and bipolar mode.

000

001

002

003

004

FFC

FFB

FFD

FFE

FFF

0 1 2 3 4 FSFS - 1.5 LSB

FULL-SCALETRANSITIONFS = REF

ZS = 01 LSB = REF/4096

OUTP

UT C

ODE

(hex

)

DIFFERENTIAL INPUT VOLTAGE (LSB)

Figure 4. Unipolar Transfer Function

800

801

FFE

001

000

FFF

7FE

7FF

-FS 0 +FS

OUTP

UT C

ODE

(hex

)

DIFFERENTIAL INPUT VOLTAGE (LSB)

+FS - 1.5 LSB

FULL-SCALETRANSITION+FS = REF/2

ZS = 0-FS = -REF/21 LSB = REF/4096

-FS + 0.5 LSB

Figure 5. Bipolar Transfer Function

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20 ______________________________________________________________________________________

SAR ADC Analog Input Track-and-Hold (T/H)Figures 6 and 7 show the equivalent input circuit of theMAXQ7667 analog input architecture. During acquisi-tion (track), a sampling capacitor charges to the posi-tive input voltage at AIN0–AIN4 in single-ended modeor AIN0 and AIN2 in differential mode while a secondsampling capacitor connects to AGND in single-endedmode or AIN1 and AIN3 in differential mode. The ADCconversion start source and the ADC dual mode selec-tion bits control the T/H timing.

Voltage ReferenceThe MAXQ7667 supports three possible voltage refer-ence sources for ADC conversion; 2.5V internalbuffered bandgap reference, external source, andAVDD. The internal 2.5V bandgap reference has highinitial accuracy and temperature coefficient of typicallyless than 100ppm/°C. When operating in internal refer-ence mode, either the buffered output of the internalreference or AVDD connects to the SAR ADC while thebuffered output of the internal reference connects to thesigma-delta ADC. When operating in external referencemode, an external source ranging between 1V andVAVDD applied at either the REF or REFBG inputs pro-

vides the reference to the SAR ADC and sigma-deltaADC. Bypass REFBG and REF to AGND with a 0.47µFcapacitor for optimum performance. See Section 14 ofthe MAXQ7667 User’s Guide.

Schedule TimerThe MAXQ7667’s schedule timer provides general time-keeping and software synchronization to an external I/O.The schedule timer features include the following:

• 16-bit autoreload up-counter for the timer

• Programmable 16-bit alarm register

• Alarm interrupts

• Schedule timer incremented by a programmablesystem clock prescaler (1, 1/2, 1/4, 1/8, 1/16, 1/32,1/64, 1/128)

• Schedule timer up-counter resettable through anexternal I/O pin, which allows synchronization of aschedule timer to an external event

• Wake-up alarm to pull the system clock from stop-mode to normal operation

Figure 8 shows a simplified block diagram of theschedule timer.

AGND

AIN+

AIN-

CIN+

AVDD

CIN-

RIN+

RIN-

Figure 6. Equivalent Input Circuit (Track/Acquisition Mode)

AGND

AIN+

AIN-

CIN+

CIN-

RIN+

RIN-

AVDD

Figure 7. Equivalent Input Circuit (Hold/Conversion Mode)

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______________________________________________________________________________________ 21

MAXQ is a registered trademark of Maxim Integrated Products, Inc.

Type 2 Timers/CountersThe MAXQ7667 includes three 16-bit timers/counterswith programmable I/O (Figure 9). Each timer is a Type2 timer implemented in the MAXQ® family. The Type 2timer is an autoreload 16-bit timer/counter offering thefollowing functions:

• 8-bit/16-bit timer/counter

• Up/down autoreload

• Counter function of external pulse

• Capture

• Compare

Clock SourcesThe MAXQ7667 oscillator module supplies the systemclock for the µC core and all of the peripheral modules.The high-frequency oscillator operates with a 1MHz to16MHz crystal. Use the internal RC oscillator as thesystem clock for applications that do not require pre-cise timing. See Section 15 of the MAXQ7667 User’sGuide.

The MAXQ7667 supports the following master clocksources:

• Internal high-frequency oscillator drives an exter-nal 1MHz–16MHz crystal or ceramic resonator

• Internal, fast-starting, 13.5MHz RC oscillator(default oscillator at startup and in the event theexternal crystal fails)

• External 4MHz–16MHz clock input

Crystal SelectionThe MAXQ7667 requires a crystal with the followingspecifications:

Frequency: 1MHz–16MHz

CLOAD: 6pF (min)

Drive level: 5µW

Series resonance resistance: 30Ω (max)

Note: Quartz crystal vendors often specify series reso-nance resistance (R1). Series resonance resistance isthe resistance observed when the resonator is in theseries resonant condition. When a resonator is used inthe parallel resonant mode with an external load capac-itance, as is the case with the MAXQ7667 oscillator cir-cuit, the effective resistance at the loaded frequency ofoscillation is:

R1 x (1 + (CO/CLOAD))2

For typical shunt capacitance (CO) and load capaci-tance (CLOAD) values, the effective resistance poten-tially exceeds R1 by a factor of 2.

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22 ______________________________________________________________________________________

T2Vx REGISTER16-BIT UP-COUNTER

T2Rx REGISTER16-BIT RELOAD

CAPTURE

EQUAL

OVERFLOW

RELOAD

CLOCK

T2Cx REGISTER16-BIT CAPTURE/COMPARE

OUTPUT CONDITIONINGPOLARITY SELECTION

INPUT CONDITIONINGSCALINGGATING

Figure 9. Type 2 Timer/Counter in 16-Bit Mode

PROGRAMMABLEDIVIDE BY

1, 2, 4, ..., 128

COMPARATORSTIM = SALM

SALMREGISTER

SALM

[15:

0]

STIM16-BIT UP-COUNTER

SCNT.11:STDIV2

SCNT.0:STIME

CLR

CLR

SCHEDULE TIMER

SYSTEMCLOCK

MAXQ7667

SCNT.8:SSYNC_EN

SCNT.7:SALIE

SCNT.1:SALME

INT

AN INTERRUPT ISGENERATED WHEN

SALIE = 1 ANDSALMF = 1

SCNT.6:SALMF

STIM

[15:

0]

P1.7/SYNC

Figure 8. Schedule-Timer Module Block Diagram

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______________________________________________________________________________________ 23

7 6 5 4 3 2 1 0 S1 S0

4 3 2 1 0SYSTEM PROGRAMMING REGISTER

2 P1.0/TDO1 0P1.2/TDI

P1.1/TMS

P1.3/TCK

DVDDIOINSTRUCTION REGISTER

POWER-ONRESET

TAPCONTROLLER

BYPASS

DEBUG REGISTER

SHADOW REGISTER

DVDDIO

READ

WRITE

DVDDIO

UPDATE-DR

UPDATE-DR

MAXQ7667

MUX

MUX

MUX

DVDDIO

MUX

TO DEBUGENGINE

Figure 10. JTAG Interface Block Diagram

JTAG InterfaceThe joint test action group (JTAG) IEEE 1149.1 standarddefines a unique method for in-circuit testing and pro-gramming. The MAXQ7667 conforms to this standard,implementing an external test access port (TAP) andinternal TAP controller for communication with a JTAGbus master, such as an automatic test equipment (ATE)system. The MAXQ7667 JTAG interface does not allowboundary scan. For detailed information on the TAP andTAP controller, refer to IEEE Std 1149.1 “IEEE StandardTest Access Port and Boundary-Scan Architecture” onthe IEEE website at www.standards.ieee.org.

The TAP controller communicates synchronously withthe host system (bus master) through four digital I/Os:test mode select (TMS), test clock (TCK), test datainput (TDI), and test data output (TDO). The internalTAP module consists of shift registers and a TAP con-troller (Figure 10). The shift registers serve as transmitand receive data buffers for a debugger. Maintain themaximum TCK clock frequency to below 1/8 the systemclock frequency for proper operation.

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24 ______________________________________________________________________________________

The following four digital I/Os form the TAP interface:

• TDO—Serial output signal for test instruction anddata. Data transitions on the falling edge of TCK.TDO idles high when inactive. TDO serially trans-fers internal data to the external host. Data trans-fers lease significant bit first.

• TDI—Serial input signal for test instruction anddata. Transition data on the rising edge of TCK.TDO pulls high when unconnected. TDI seriallytransfers data from the external host to the internalTAP module shift registers. Data transfers leastsignificant bit first.

• TCK—Serial clock for the test logic. When TCKstops at 0, storage elements in the test logic mustretain their data indefinitely. Force TCK high wheninactive.

• TMS—Test mode selection. The rising edge of TCKsamples the test signals at TMS. The TAP controllerdecodes the test signals at TMS to control the testoperation. Force TMS high when inactive.

UART/LIN InterfaceThe MAXQ7667 includes a UART/LIN transceiver com-bination that supports communication speeds up2MBd. The LIN standard for example limits communica-tion speed to 20kBd or less. Connect a LIN transceiveror other UART connections such as RS-232 and RS-485directly to the MAXQ7667’s 2-wire interface: URX andUTX. The MAXQ7667 operates as a LIN slave or LINmaster device. The UART provides the programmablebaud-rate generators to communicate effectively to orfrom the LIN transceiver. The device holds up to 8bytes of data in each of the transmit and receive FIFOs.The following characteristics apply to the MAXQ7667UART/LIN interface:

• Full-duplex operation for asynchronous data trans-fers up to 500kBd (system clock/32)

• Half-duplex operation for synchronous data trans-fers up to 2MBd (system clock/8)

• 8-deep receive and transmit FIFO with program-mable interrupt for receive and transmit

• Independent baud-rate generator

• Programmable 9th data bit (commonly used forparity or address/data selection)—UART modeonly

• Hardware support for LIN including break detec-tion, autobaud, address identity filtering, check-sum calculation, and block length checking

• Supports common RS-232 and LIN baud rates:1000, 1200, 2400, 4800, 9600, 19,200, 20,000,38,400, 57,600, and 115,200 with system clock =16MHz.

SPI InterfaceThe MAXQ7667 supports 4-wire SPI interface communi-cation with 8-bit or 16-bit data streams operating ineither master mode or slave mode. The SPI interfaceallows synchronous half-duplex or full-duplex serialdata transfers to a wide variety of external serialdevices using MISO, MOSI, SS, and SCLK signals.Collision detection is provided when two or more mas-ters attempt a data transfer at the same time. SeeSection 9 of the MAXQ7667 User’s Guide.

General-Purpose Digital I/O PortsTwo 8-bit digital I/O ports (P0._ and P1._), with dedicat-ed one or more alternative functions, are available asgeneral-purpose I/Os (GPIOs) under the control of theintegrated MAXQ20. Set each I/O within each port indi-vidually as an input or output. The GPIOs incorporate aSchmitt trigger receiver and a full CMOS output driver(Figure 13). Each GPIO configures as an input withpullup to DVDDIO at power-up. When programmed asan input, each I/O is configurable for high-impedance,weak pullup to DVDDIO or pulldown to DGND. Whenprogrammed as an output, writing to the port outputregister (PO) controls the output logic state. The out-puts source or sink at least 1.6mA. Configure the drivestrength for each I/O within each port to high or lowusing the pad drive strength register for optimum EMIperformance. All the I/O ports have interrupt capabilitythat wake up the device while in stop mode and haveprotection circuitry to DVDDIO and DGND.

Supply-Voltage RegulatorsThe MAXQ7667 requires three different power-supplyvoltages. DVDDIO, nominally +5V, allows interfacing tostandard 5V logic on all the digital I/Os including theLIN/UART, JTAG, and SPI ports. DVDD, nominally+2.5V, powers all the high-speed digital circuits. AVDD,nominally 3.3V, powers the analog circuits.

External power supplies or internal voltage regulatorsprovide each of the supply voltages. The internal volt-age regulators provide 3.3V and 2.5V supplies from the5V DVDDIO input. Obtain the 5V supply from a higherexternal voltage supply by using a few external compo-nents. The MAXQ7667 includes an internal error ampli-fier used to regulate the voltage on DVDDIO by drivingthe gate or base of an external pass transistor. Refer tothe MAXQ7667 User’s Guide for more details on theexternal components needed for 5V regulation.

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______________________________________________________________________________________ 25

SCLKCKPOL/CKPHA

0/1 OR 1/0

SS

MISO

MOSI

SCLKCKPOL/CKPHA

0/0 OR 1/1

SHIFT SAMPLE SHIFT

MSB - 1

MSB - 1

SAMPLE

tMCH

tMCK

tMCL

tMOH

tMOV

tMIS tMIH

MSB LSB

MSB LSB

tMLH

Figure 11. SPI Timing Diagram in Master Mode

SCLKCKPOL/CKPHA

0/1 OR 1/0

SS

SCLKCKPOL/CKPHA

0/0 OR 1/1

SHIFT SAMPLE SHIFT SAMPLE

tSCK

tSCLtSCH

tSSE

tSOV

tSIHtSIS

tSSH

MOSI

MISO

MSB LSBMSB - 1

MSB MSB - 1

tSD

Figure 12. SPI Timing Diagram in Slave Mode

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26 ______________________________________________________________________________________

Connect bypass capacitors at each power-supply inputas close as possible to the device. Use a bypasscapacitor less than 0.47µF on DVDDIO. For most appli-cations, 0.1µF bypass capacitors are adequate.

Supply Brownout MonitorPower supplies DVDD, AVDD, and DVDDIO eachinclude a brownout monitor/supervisor that alerts theµC when their corresponding supply voltages dropbelow the interrupt threshold. Activate each brownoutmonitor independently using the correspondingbrownout enable bits: VDBE, VIBE, and VABE.

ResetIn reset mode, no instruction execution occurs and allinputs/outputs return to their default states. Code exe-cution resumes at address 8000h (in the utility ROM)once the reset condition is removed.

Four different sources reset the MAXQ7667: POR,watchdog timer reset, external reset, and internal sys-tem reset.

During normal operation, force RESET low for at leastfour system clock cycles for an external reset. Set theROD bit in the SC register, while the SPE bit in the ICDFregister is set, for an internal system reset. See Section16 of the MAXQ7667 User’s Guide.

Power-On Reset (POR)The MAXQ7667 includes a DVDD voltage supervisor tocontrol the µC POR. On power-up, internal circuitrypulls RESET low and resets all the internal registers.RESET is held low for the duration of the power-ondelay after VDVDD rises above the DVDD reset thresh-old. The internal RC oscillator starts up and softwareexecution begins at the reset vector location 8000himmediately after the device exits POR while RESET is

I/O PAD DVDDIO

P0._

100ΩK

100ΩK

DGND

DGND

EIE0._

EIES0._

DETECTCIRCUIT

INTERRUPTFLAG

PS0._

PR0._

PD0._

PO0._

SF DIRECTION

SF ENABLE

SF OUTPUT

PI0._ ORSF INPUT

FLAG

MUX

MUX

MAXQ7667

Figure 13. Port 0 Digital I/O Basic Circuitry. Port 1 Circuitry is the Same as Port 2.

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______________________________________________________________________________________ 27

not externally forced low. An internal POR flag indicatesthe source of a reset. Ramp up the DVDD supply at aminimum rate of 60mV/ms to keep the device in PORuntil DVDD fully settles.

Watchdog TimerThe primary function of the watchdog timer is to watchfor stalled or stuck software. The watchdog timer per-forms a controlled system restart when the µP fails towrite to the watchdog timer register before a selectabletimeout interval expires. The internal 13.5MHz RC oscil-lator drives the MAXQ7667’s watchdog timer.

Figure 14 shows the watchdog timer functions as thesource of both the watchdog interrupt and watchdogreset. The watchdog interrupt timeout period is pro-grammable to 212, 215, 218, or 221 cycles of the RCoscillator resulting in a nominal range of 273µs to139.8ms. The watchdog reset timeout period is a fixed512 RC clock cycles (34µs). When enabled, the watch-dog generates an interrupt upon expiration; then, if notreset within 512 RC clock cycles, the watchdog assertsRESET low for eight RC clock cycles.

Hardware Multiplier/AccumulatorA hardware multiplier supports high-speed multiplica-tions. The multiplier completes a 16-bit x 16-bit multipli-cation in a single clock cycle and contains a 48-bitaccumulator. The multiplier is a peripheral that per-forms seven different multiplication operations:

• Unsigned 16-bit multiplication

• Unsigned 16-bit multiplication and accumulation

• Unsigned 16-bit multiplication and subtraction

• Signed 16-bit multiplication

• Signed 16-bit multiplication and negation

• Signed 16-bit multiplication and accumulation

• Signed 16-bit multiplication and subtraction

MAXQ Core ArchitectureThe MAXQ20 µC is an accumulator-based Harvardmemory architecture. Fetch and execution operationscomplete in one clock cycle without pipelining becausethe instruction contains both the op code and data. TheµC streamlines 16 million instructions per second(MIPS). Integrated 16-level hardware stack enables fastsubroutine calling and task switching. Manipulate dataquickly and efficiently with three internal data pointers.Multiple data pointers allow more than one function toaccess data memory without having to save andrestore data pointers each time. The data pointers auto-matically increment or decrement following an opera-tion, eliminating the need for software intervention.

Instruction SetThe instruction set consists of a total of 33 fixed-length16-bit instructions that operate on registers and memo-ry locations. The highly orthogonal instruction set allowsarithmetic and logical operations to use any registeralong with the accumulator. System registers controlfunctionality common to all MAXQ µCs, while peripheralregisters control peripherals and functions specific tothe MAXQ7667. All registers are subdivided into regis-ter modules.

The architecture is transport-triggered. Writes or readsfrom certain register locations potentially have sideeffects. These side effects form the basis for the higherlevel op codes defined by the assembler, such asADDC, OR, JUMP, etc. The op codes are implementedas MOVE instructions between system registers. Theassembler handles all the instruction encoding.

Memory OrganizationIn addition to the internal register space, the deviceincorporates several memory areas:

• 16Kwords of flash memory for program storage

• 2Kword of SRAM for storage of temporary variables

• 4Kwords utility ROM

• 16-level, 16-bit-wide hardware stack for storage ofprogram return addresses and general-purpose use

Use the internal memory-management unit (MMU) tomap data memory space into a predefined programmemory segment for code execution from data memory.Use the MMU to map program memory space as dataspace for access to constant data stored in program

EWDI

WD0RWT

WD1

RC CLOCK (13.5MHz)

INTERRUPT

WTRF

RESET

WDIF

TIMEOUT

TIME212

DIV 212 DIV 23 DIV 23 DIV 23

215 218 221

EWT

RESET

Figure 14. Watchdog Functional Diagram

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28 ______________________________________________________________________________________

memory. Access physical memory segments (otherthan the stack and register memories) as either pro-gram memory or data memory, but not both at once.

By default, the memory is arranged in a Harvard archi-tecture, with separate address spaces for program anddata memory. The configuration of program and dataspace depends on the current execution location.

• When executing code from flash memory, accessthe SRAM and utility ROM in data space.

• When executing code from SRAM, access theflash memory and utility ROM in data space.

• When executing code from the utility ROM, accessthe flash memory and SRAM in data space.

Utility ROM (see Section 18 ofthe MAXQ7667 User’s Guide)

The utility ROM is a 4K x 16 block of internal ROMmemory that defaults to a starting address of 8000h.The utility ROM consists of subroutines called fromapplication software. The subroutines include:

• In-system programming (bootloader) over theJTAG or UART interface

• In-circuit debug routines

• Test routines (internal memory tests, memoryloader, etc.)

• User-callable routines for in-application flash pro-gramming and code space table lookup

Following any reset, execution begins in the utility ROM.The ROM software determines whether the programexecution immediately jumps to the start of the user-application code (located at address 0000h) or to oneof the special routines mentioned above. Call the rou-tines within the utility ROM using the application soft-ware. Refer to the MAXQ7667 User’s Guide for moreinformation on the utility ROM contents.

Password protect in-system programming, in-applica-tion programming, and in-circuit debugging functionsusing a password-lock (PWL) bit. The PWL bit is imple-mented in the SC register. When the PWL bit is set toone (POR default), the password is required to accessthe utility ROM, including in-circuit debug and in-sys-tem programming routines that allow reading or writingof internal memory. When the PWL bit is cleared tozero, these utilities are fully accessible without thepassword. The password is automatically set to all onesfollowing a mass erase.

Data MemoryThe 2K x 16 internal data SRAM maps into either pro-gram or data space. The contents of the SRAM aremaintained during stop mode and across non-PORresets, as long as DVDD remains within the operatingvoltage range.

A data memory cycle requires only one system clockperiod to support fast internal execution. This allows acomplete read or write operation on SRAM in one clockcycle. The MMU handles data memory mapping andaccess control. Read or write to the data memory withword or byte-wide commands.

Stack MemoryThe MAXQ7667 provides a 16 x 16 hardware stack tosupport subroutine calls and system interrupts. A 16-bitwide internal hardware stack provides storage for pro-gram return addresses and general-purpose use. Thestack is used automatically by the processor when theCALL, RET, and RETI instructions are executed andinterrupts serviced.

Register SetSets of registers control most functions. These registersprovide a working space for memory operations as wellas configuring and addressing peripheral registers onthe device. Registers are divided into two major types;system registers and peripheral registers. The registerset common to most MAXQ-based devices, also knownas the system registers, includes the ALU, accumulatorregisters, data pointers, interrupt vectors and control,and stack pointer. The peripheral registers define addi-tional functionality. Tables 1 and 3 show the MAXQ7667register set.

ProgrammingTwo different methods program the flash memory: in-system programming and in-application programming.Both methods afford great flexibility in system designas well as reduce the life-cycle cost of the embeddedsystem. The MAXQ7667 password protects these fea-tures to prevent unauthorized access to code memory.

In-System ProgrammingAn internal bootstrap loader reloads the device over asimple JTAG or UART interface allowing cost savings insystem software upgrade. During power-up, theMAXQ7667 first checks for activity on the JTAG port. Ifno activity is present, the device checks if a password-protected program is present. If the password is set,

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______________________________________________________________________________________ 29

the application code executes. The application codesinitiate reprogramming. If the password is not set, theMAXQ7667 monitors the UART for an autobaud char-acter (0x0D). If this character is received, the devicesets its serial baud rate and initiates a boot loader pro-cedure. If 0x0D is not received after five seconds, thedevice begins execution of the application code.

The following bootloader functions are supported:

• Load

• Dump

• CRC

• Verify

• Erase

In-Application ProgrammingThe in-application programming feature allows the µCto modify its own flash program memory while simulta-neously executing its application software. This allowson the fly software updates in mission-critical applica-tions that cannot afford downtime. Erase and programthe flash memory using the flash programming func-tions in the utility ROM. Refer to Section 18 of theMAXQ7667 User’s Guide for a detailed description ofthe utility ROM functions.

Stop ModePower consumption reaches its minimum in stop mode(STOP = 1). In this mode, the external oscillator, inter-nal RC oscillator, system clock, and all processinghalts. Trigger an enabled external interrupt input ordirectly apply an external reset on RESET to exit stopmode. Upon exiting stop mode, the µC either waits forthe external high-frequency crystal to complete itswarmup period or starts execution immediately from itsinternal RC oscillator while the crystal warms up.

InterruptsMultiple interrupt sources quickly respond to internaland external events. The MAXQ architecture uses asingle interrupt vector (IV) and single interrupt-serviceroutine (ISR) design. Enable interrupts globally,

individually, or by module. When an interrupt conditionoccurs, its individual flag is set even if the interruptsource is disabled at the local, module, or global level.Clear interrupt flags within the interrupt routine to avoidrepeated false interrupts from the same source.Provide an adequate delay between the write to theflag and the RETI instruction using application softwareto allow time for the interrupt hardware to remove theinternal interrupt condition. Asynchronous interruptflags require a one-instruction delay and synchronousinterrupt flags require a two-instruction delay.

When an enabled interrupt is detected, software jumpsto a user-programmable interrupt vector location. TheIV register defaults to 0000h on reset or power-up.Once software control transfers to the ISR, use theinterrupt identification register (IIR) to determine if thesource of the interrupt is a system register or peripheralregister. The specified module identifies the specificinterrupt source. The following interrupt sources areavailable:

• Watchdog interrupt

• External interrupts 0–7 on port 0 and port 1

• Timer 0 low compare, low overflow, capture/com-pare, and overflow interrupts

• Timer 1 low compare, low overflow, capture/com-pare, and overflow interrupts

• Timer 2 low compare, low overflow, and overflowinterrupts

• Schedule timer alarm interrupt

• SPI data transfer complete, mode fault, write colli-sion and receive overrun interrupts

• UART transmit, receive interrupts

• LIN mode master or slave interrupt

• SAR ADC data ready interrupt

• Echo envelope LPF output, FIFO full, and com-parator interrupts

• Digital and I/O voltage brownout interrupts

• High-frequency oscillator failure interrupt

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30 ______________________________________________________________________________________

MODULE NAME (BASE SPECIFIER) REGISTER INDEX AP (8h) A (9h) PFX (Bh) IP (Ch) SP (Dh) DPC (Eh) DP (Fh)

0h AP A[0] PFX[0] IP — — —

1h APC A[1] PFX[1] — SP — —

2h — A[2] PFX[2] — IV — —

3h — A[3] PFX[3] — — OFFS DP[0]

4h PSF A[4] PFX[4] — — DPC —

5h IC A[5] PFX[5] — — GR —

6h IMR A[6] PFX[6] — LC[0] GRL —

7h — A[7] PFX[7] — LC[1] BP DP[1]

8h SC A[8] — — GRS —

9h — A[9] — — — GRH —

Ah — A[10] — — — GRXL —

Bh IIR A[11] — — — FP —

Ch — A[12] — — — — —

Dh — A[13] — — — — —

Eh CKCN A[14] — — — — —

Fh WDCN A[15] — — — — —

Table 1. System Register Map

Note: Registers in italics are read-only. Registers in bold are 16-bit wide.

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______________________________________________________________________________________ 31

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0

—

—

—

—

A

P (

4 B

its)

AP

0 0

0 0

0 0

0 0

C

LR

IDS

—

—

—

M

OD

2 M

OD

1 M

OD

0 A

PC

0 0

0 0

0 0

0 0

Z

S

—

G

PF1

G

PF0

O

V

C

E

PS

F

1 0

0 0

0 0

0 0

—

—

C

GD

S

—

—

—

INS

IG

E

IC

0 0

0 0

0 0

0 0

IM

S

—

IM5

IM4

IM3

IM2

IM1

IM0

IMR

0 0

0 0

0 0

0 0

TA

P

—

CD

A1

CD

A0

—

RO

D

PW

L —

S

C

1

0 0

0 0

0 s*

0

IIS

—

II5

II4

II3

II2

II1

II0

IIR

0 0

0 0

0 0

0 0

X

TRC

—

R

GM

D

STO

P

SW

B

PM

ME

C

D1

CD

0 C

KC

N

s*

0

0 0

0 0

0 0

P

OR

E

WD

I W

D1

WD

0 W

DIF

W

TRF

EW

T R

WT

WD

CN

s*

s*

0 0

0 s*

s*

0

A[n

] (1

6 B

its)

A[n

] (0

..15)

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

PFX

[n]

(16

Bits

) P

FX[n

] (0

..7)

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

IP (

16 B

its)

IP

1 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

—

—

—

—

SP

(4

Bits

) S

P0

0 0

0 0

0 0

0 0

0 0

0 1

1 1

1

IV (

16 B

its)

IV

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

LC[0

] (1

6 B

its)

LC[0

] 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

LC[1

] (1

6 B

its)

LC[1

] 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

Tab

le 2

. Sys

tem

Reg

iste

r B

it a

nd

Res

et V

alu

es

*Bits

ind

icat

ed b

y an

“s”

are

onl

y af

fect

ed b

y a

PO

R a

nd n

ot b

y ot

her

form

s of

res

et. T

hese

bits

are

set

to 0

afte

r a

PO

R. R

efer

to th

e M

AX

Q76

67 U

ser’s

Gui

de

for

mor

e in

form

atio

n.

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32 ______________________________________________________________________________________

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0

O

FFS

(8

Bits

) O

FFS

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

—

—

—

WB

S2

WB

S1

WB

S0

SD

PS

1 S

DP

S0

DP

C

0 0

0 0

0 0

0 0

0 0

0 1

1 1

0 0

GR

15

GR

14

GR

13

GR

12

GR

11

GR

10

GR

9 G

R8

GR

7 G

R6

GR

5 G

R4

GR

3 G

R2

GR

1 G

R0

GR

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

G

RL7

G

RL6

G

RL5

G

RL4

G

RL3

G

RL2

G

RL1

G

RL0

G

RL

0

0 0

0 0

0 0

0

BP

(16

Bits

) B

P

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

GR

S15

G

RS

14

GR

S13

G

RS

12

GR

S11

G

RS

10

GR

S9

GR

S8

GR

S7

GR

S6

GR

S5

GR

S4

GR

S3

GR

S2

GR

S1

GR

S0

GR

S

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

G

R15

G

R14

G

R13

G

R12

G

R11

G

R10

G

R9

GR

8 G

RH

0 0

0 0

0 0

0 0

GR

XL1

5 G

RX

L14

GR

XL1

3 G

RX

L12

GR

XL1

1 G

RX

L10

GR

XL9

G

RX

L8

GR

XL7

G

RX

L6

GR

XL5

G

RX

L4

GR

XL3

G

RX

L2

GR

XL1

G

RX

L0

GR

XL

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

FP (

16 B

its)

FP

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

DP

[0]

(16

Bits

) D

P[0

] 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

DP

[1]

(16

Bits

) D

P[1

] 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

Tab

le 2

. Sys

tem

Reg

iste

r B

it a

nd

Res

et V

alu

es (

con

tin

ued

)

*Bits

ind

icat

ed b

y an

“s”

are

onl

y af

fect

ed b

y a

PO

R a

nd n

ot b

y ot

her

form

s of

res

et. T

hese

bits

are

set

to 0

afte

r a

PO

R. R

efer

to th

e M

AX

Q76

67 U

ser’s

Gui

de

for

mor

e in

form

atio

n.

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______________________________________________________________________________________ 33

MODULE NAME (BASE SPECIFIER)REGISTERINDEX M0 (0h) M1 (1h) M2 (2h) M3 (3h) M4 (4h) M5 (5h)

0h PO0 MCNT T2CNA0 T2CNA2 — BPH

1h PO1 MA T2H0 T2H2 — BTRN

2h — MB T2RH0 T2RH2 — SARC

3h EIF0 MC2 T2CH0 T2CH2 — RCVC

4h EIF1 MC1 T2CNA1 — — PLLF

5h — MC0 T2H1 CNT1 — AIE

6h — SPIB T2RH1 SCON — CMPC

7h — SPICN T2CH1 SBUF — CMPT

8h PI0 SPICF T2CNB0 T2CNB2 — ASR

9h PI1 SPICK T2V0 T2V2 — SARD

Ah — — T2R0 T2R2 — LPFC

Bh EIE0 — T2C0 T2C2 — OSCC

Ch EIE1 MC1R T2CNB1 FSTAT — BPFI

Dh — MC0R T2V1 ERRR — BPFO

Eh — SCNT T2R1 CHKSUM — LPFD

Fh — STIM T2C1 ISVEC — LPFF

10h PD0 SALM T2CFG0 T2CFG2 — APE

11h PD1 FPCTL T2CFG1 STA0 — —

12h — — — SMD — FGAIN

13h EIES0 — — FCON — B1COEF

14h EIES1 — — CNT0 — B2COEF

15h — — — CNT2 — B3COEF

16h — — — IDFB — A2A

17h — RCTRM — SADDR — A2B

18h PS0 — ICDT0 SADEN — —

19h PS1 — ICDT1 BT — A2D

1Ah — — ICDC TMR — —

1Bh PR0 — ICDF — — A3A

1Ch PR1 ID0 ICDB — — A3B

1Dh — ID1 ICDA — — —

1Eh — — ICDD — — A3D

1Fh — — — — — —

Table 3. Peripheral Register Map

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34 ______________________________________________________________________________________

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0—

——

——

——

—

PO

07

PO

06

PO

05

PO

04

PO

03

PO

02

PO

01

PO

00

PO

0 0

00

00

00

0 1

1 1

1 1

1 1

1 —

——

——

——

—

PO

17

PO

16

PO

15

PO

14

PO

13

PO

12

PO

11

PO

10

PO

1 0

00

00

00

0 1

1 1

1 1

1 1

1 —

——

——

——

—

IE7

IE6

IE5

IE4

IE3

IE2

IE1

IE0

EIF

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

IE7

IE6

IE5

IE4

IE3

IE2

IE1

IE0

EIF

1 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

PI0

7 P

I06

PI0

5 P

I04

PI0

3 P

I02

PI0

1 P

I00

PI0

0

00

00

00

0 S

T S

T S

T S

T S

T S

T S

T S

T —

——

——

——

—

PI1

7 P

I16

PI1

5 P

I14

PI1

3 P

I12

PI1

1 P

I10

PI1

0

00

00

00

0 S

T S

T S

T S

T S

T S

T S

T S

T —

——

——

——

—

EX

7 E

X6

EX

5 E

X4

EX

3 E

X2

EX

1 E

X0

EIE

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

EX

7 E

X6

EX

5 E

X4

EX

3 E

X2

EX

1 E

X0

EIE

1 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

PD

07

PD

06

PD

05

PD

04

PD

03

PD

02

PD

01

PD

00

PD

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

PD

17

PD

16

PD

15

PD

14

PD

13

PD

12

PD

11

PD

10

PD

1 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

IT7

IT6

IT5

IT4

IT3

IT2

IT1

IT0

EIE

S0

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

IT

7 IT

6 IT

5 IT

4 IT

3 IT

2 IT

1 IT

0 E

IES

1 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

PS

07

PS

06

PS

05

PS

04

PS

03

PS

02

PS

01

PS

00

PS

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

PS

17

PS

16

PS

15

PS

14

PS

13

PS

12

PS

11

PS

10

PS

1 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

PR

07

PR

06

PR

05

PR

04

PR

03

PR

02

PR

01

PR

00

PR

0 0

00

00

00

0 1

1 1

1 1

1 1

1 —

——

——

——

—

PR

17

PR

16

PR

15

PR

14

PR

13

PR

12

PR

11

PR

10

PR

1 0

00

00

00

0 1

1 1

1 1

1 1

1 —

——

——

——

—

OF

MC

W

CLD

S

QU

O

PC

S

MS

UB

M

MA

C

SU

S

MC

NT

00

00

00

00

0 0

0 0

0 0

0 0

MA

15

MA

14

MA

13

MA

12

MA

11

MA

10

MA

9 M

A8

MA

7 M

A6

MA

5 M

A4

MA

3 M

A2

MA

1 M

A0

MA

0

00

00

00

0 0

0 0

0 0

0 0

0 M

B15

M

B14

M

B13

M

B12

M

B11

M

B10

M

B9

MB

8 M

B7

MB

6 M

B5

MB

4 M

B3

MB

2 M

B1

MB

0 M

B

00

00

00

00

0 0

0 0

0 0

0 0

MC

215

MC

214

MC

213

MC

212

MC

211

MC

210

MC

29

MC

28

MC

27

MC

26

MC

25

MC

24

MC

23

MC

22

MC

21

MC

20

MC

2 0

00

00

00

0 0

0 0

0 0

0 0

0 M

C11

5 M

C11

4 M

C11

3 M

C11

2 M

C11

1 M

C11

0 M

C19

M

C18

M

C17

M

C16

M

C15

M

C14

M

C13

M

C12

M

C11

M

C10

M

C1

00

00

00

00

0 0

0 0

0 0

0 0

MC

015

MC

014

MC

013

MC

012

MC

011

MC

010

MC

09

MC

08

MC

07

MC

06

MC

05

MC

04

MC

03

MC

02

MC

01

MC

00

MC

0 0

00

00

00

0 0

0 0

0 0

0 0

0 S

PIB

15

SP

IB14

S

PIB

13

SP

IB12

S

PIB

11

SP

IB10

S

PIB

9 S

PIB

8 S

PIB

7 S

PIB

6 S

PIB

5 S

PIB

4 S

PIB

3 S

PIB

2 S

PIB

1 S

PIB

0 S

PIB

0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

STB

Y

SP

IC

RO

VR

W

CO

L M

OD

F M

OD

FE

MS

TM

SP

IEN

S

PIC

N

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

E

SP

II S

AS

—

—

—

C

HR

C

KP

HA

C

KP

OL

SP

ICF

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

S

PIC

K7

SP

ICK

6 S

PIC

K5

SP

ICK

4 S

PIC

K3

SP

ICK

2 S

PIC

K1

SP

ICK

0 S

PIC

K

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

FB

US

Y

—

—

—

—

FC2

FC1

FC0

FCN

TL

00

00

00

00

1 0

0 0

0 0

0 0

MC

1R15

M

C1R

14

MC

1R13

M

C1R

12

MC

1R11

M

C1R

10

MC

1R9

MC

1R8

MC

1R7

MC

1R6

MC

1R5

MC

1R4

MC

1R3

MC

1R2

MC

1R1

MC

1R0

MC

1R

00

00

00

00

0 0

0 0

0 0

0 0

MC

0R15

M

C0R

14

MC

0R13

M

C0R

12

MC

0R11

M

C0R

10

MC

0R9

MC

0R8

MC

0R7

MC

0R6

MC

0R5

MC

0R4

MC

0R3

MC

0R2

MC

0R1

MC

0R0

MC

0R

00

00

00

00

0 0

0 0

0 0

0 0

Tab

le 4

. Per

iph

eral

Reg

iste

r B

it F

un

ctio

ns

and

Res

et V

alu

es

MA

XQ

76

67


______________________________________________________________________________________ 35

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0—

——

—S

TDIV

2 S

TDIV

1 S

TDIV

0 S

SY

NC

_EN

S

ALI

E

SA

LMF

—

—

—

—

SA

LME

S

TIM

E

SC

NT

00

00

00

00

0 0

0 0

0 0

0 0

STI

M15

S

TIM

14

STI

M13

S

TIM

12

STI

M11

S

TIM

10

STI

M9

STI

M8

STI

M7

STI

M6

STI

M5

STI

M4

STI

M3

STI

M2

STI

M1

STI

M0

STI

M

00

00

00

00

0 0

0 0

0 0

0 0

SA

LM15

S

ALM

14

SA

LM13

S

ALM

12

SA

LM11

S

ALM

10

SA

LM9

SA

LM8

SA

LM7

SA

LM6

SA

LM5

SA

LM4

SA

LM3

SA

LM2

SA

LM1

SA

LM0

SA

LM

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

—

—

—

—

—

—

—

D

PM

G

FPC

NTL

0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

RC

TRM

8 R

CTR

M7

RC

TRM

6 R

CTR

M5

RC

TRM

4 R

CTR

M3

RC

TRM

2 R

CTR

M1

RC

TRM

0 R

CTR

M

00

00

00

00

0 0

0 0

0 0

0 0

ID01

5 ID

014

ID01

3 ID

012

ID01

1 ID

010

ID09

ID

08

ID07

ID

06

ID05

ID

04

ID03

ID

02

ID01

ID

00

ID0

00

00

00

00

0 0

0 0

0 0

0 0

ID11

5 ID

114

ID11

3 ID

112

ID11

1 ID

110

ID19

ID

18

ID17

ID

16

ID15

ID

14

ID13

ID

12

ID11

ID

10

ID1

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

E

T2

T2O

E0

T2P

OL0

TR

2L

TR2

CP

RL2

S

S2

G2E

N

T2C

NA

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

T2H

07

T2H

06

T2H

05

T2H

04

T2H

03

T2H

02

T2H

01

T2H

00

T2H

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

T2R

H07

T2

RH

06

T2R

H05

T2

RH

04

T2R

H03

T2

RH

02

T2R

H01

T2

RH

00

T2R

H0

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

T2

CH

07

T2C

H06

T2

CH

05

T2C

H04

T2

CH

03

T2C

H02

T2

CH

01

T2C

H00

T2

CH

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

ET2

T2

OE

0 T2

PO

L0

TR2L

TR

2 C

PR

L2

SS

2 G

2EN

T2

CN

A1

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

T2

H17

T2

H16

T2

H15

T2

H14

T2

H13

T2

H12

T2

H.1

T2

H10

T2

H1

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

T2

RH

17

T2R

H16

T2

RH

15

T2R

H14

T2

RH

13

T2R

H12

T2

RH

11

T2R

H10

T2

RH

1 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

T2C

H17

T2

CH

16

T2C

H15

T2

CH

14

T2C

H13

T2

CH

12

T2C

H11

T2

CH

10

T2C

H1

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

E

T2L

T2O

E1

T2P

OL1

—

TF

2 TF

2L

TCC

2 TC

2L

T2C

NB

0 0

00

00

00

0 0

0 0

0 0

0 0

0 T2

V01

5 T2

V01

4 T2

V01

3 T2

V01

2 T2

V01

1 T2

V01

0 T2

V09

T2

V08

T2

V07

T2

V06

T2

V05

T2

V04

T2

V03

T2

V02

T2

V01

T2

V00

T2

V0

00

00

00

00

0 0

0 0

0 0

0 0

T2R

015

T2R

014

T2R

013

T2R

012

T2R

011

T2R

010

T2R

09

T2R

08

T2R

07

T2R

06

T2R

05

T2R

04

T2R

03

T2R

02

T2R

01

T2R

00

T2R

0 0

00

00

00

0 0

0 0

0 0

0 0

0 T2

C01

5 T2

C01

4 T2

C01

3 T2

C01

2 T2

C01

1 T2

C01

0 T2

C09

T2

C08

T2

C07

T2

C06

T2

C05

T2

C04

T2

C03

T2

C02

T2

C01

T2

C00

T2

C0

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

E

T2L

T2O

E1

T2P

OL1

—

TF

2 TF

2L

TCC

2 TC

2L

T2C

NB

1 0

00

00

00

0 0

0 0

0 0

0 0

0 T2

V11

5 T2

V11

4 T2

V11

3 T2

V11

2 T2

V11

1 T2

V11

0 T2

V19

T2

V18

T2

V17

T2

V16

T2

V15

T2

V14

T2

V13

T2

V12

T2

V11

T2

V10

T2

V1

00

00

00

00

0 0

0 0

0 0

0 0

T2R

115

T2R

114

T2R

113

T2R

112

T2R

111

T2R

110

T2R

19

T2R

18

T2R

17

T2R

16

T2R

15

T2R

14

T2R

13

T2R

12

T2R

11

T2R

10

T2R

1 0

00

00

00

0 0

0 0

0 0

0 0

0 T2

C11

5 T2

C11

4 T2

C11

3 T2

C11

2 T2

C11

1 T2

C11

0 T2

C19

T2

C18

T2

C17

T2

C16

T2

C15

T2

C14

T2

C13

T2

C12

T2

C11

T2

C10

T2

C1

00

00

00

00

0 0

0 0

0 0

0 0

——

——

——

——

T2

C1

T2D

IV2

T2D

IV1

T2D

IV0

T2M

D

CC

F1

CC

F0

C/T

2 T2

CFG

0 0

00

00

00

0 0

0 0

0 0

0 0

0 —

——

——

——

—

T2C

1 T2

DIV

2 T2

DIV

1 T2

DIV

0 T2

MD

C

CF1

C

CF0

C

/T2

T2C

FG1

00

00

00

00

0 0

0 0

0 0

0 0

ICD

T015

IC

DT0

14

ICD

T013

IC

DT0

12

ICD

T011

IC

DT0

10

ICD

T09

ICD

T08

ICD

T07

ICD

T06

ICD

T05

ICD

T04

ICD

T03

ICD

T02

ICD

T01

ICD

T00

ICD

T0

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

ICD

T115

IC

DT1

14

ICD

T113

IC

DT1

12

ICD

T111

IC

DT1

10

ICD

T19

ICD

T18

ICD

T17

ICD

T16

ICD

T15

ICD

T14

ICD

T13

ICD

T12

ICD

T11

ICD

T10

ICD

T1

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

DB

D

B

——

——

——

——

D

ME

—

R

EG

E

—

CM

D3

CM

D2

CM

D1

CM

D0

ICD

C0

00

00

00

0 D

W

0 D

W

0 D

W

DW

D

W

DW

Tab

le 4

. Per

iph

eral

Reg

iste

r B

it F

un

ctio

ns

and

Res

et V

alu

es (

con

tin

ued

)

MA

XQ

76

67


36 ______________________________________________________________________________________

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0—

—

—

—

—

—

—

—

—

—

—

—

P

SS

1 P

SS

0 S

PE

TX

C

ICD

F 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

IC

DB

.7

ICD

B.6

IC

DB

.5

ICD

B.4

IC

DB

.3

ICD

B.2

IC

DB

.1

ICD

B.0

IC

DB

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 IC

DA

15

ICD

A14

IC

DA

13

ICD

A12

IC

DA

11

ICD

A10

IC

DA

9 IC

DA

8 IC

DA

7 IC

DA

6 IC

DA

5 IC

DA

4 IC

DA

3 IC

DA

2 IC

DA

1 IC

DA

0 IC

DA

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 IC

DD

15

ICD

D14

IC

DD

13

ICD

D12

IC

DD

11

ICD

D10

IC

DD

9 IC

DD

8 IC

DD

7 IC

DD

6 IC

DD

5 IC

DD

4 IC

DD

3 IC

DD

2 IC

DD

1 IC

DD

0 IC

DD

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

ET2

T2

OE

0 T2

PO

L0

TR2L

TR

2 C

PR

L2

SS

2 G

2EN

T2

CN

A2

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

T2H

27

T2H

26

T2H

25

T2H

24

T2H

23

T2H

22

T2H

21

T2H

20

T2H

2 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

T2

RH

27

T2R

H26

T2

RH

25

T2R

H24

T2

RH

23

T2R

H22

T2

RH

21

T2R

H20

T2

RH

2 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

T2

CH

27

T2C

H26

T2

CH

25

T2C

H24

T2

CH

23

T2C

H22

T2

CH

21

T2C

H20

T2

CH

2 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

R

TN

CK

FL

5 FL

4 FL

3 FL

2 FL

1 FL

0 C

NT1

0

0 0

0 0

0 0

0 1

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

S

M0/

FE

SM

1 S

M2

RE

N

TB8

RB

8 TI

R

I S

CO

N

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

SB

UF7

S

BU

F6

SB

UF5

S

BU

F4

SB

UF3

S

BU

F2

SB

UF1

S

BU

F0

SB

UF

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

ET2

L T2

OE

1 T2

PO

L1

—

TF2

TF2L

TC

C2

TC2L

T2

CN

B2

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

T2V

215

T2V

214

T2V

213

T2V

212

T2V

211

T2V

210

T2V

29

T2V

28

T2V

27

T2V

26

T2V

25

T2V

24

T2V

23

T2V

22

T2V

21

T2V

20

T2V

2 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 T2

R21

5 T2

R21

4 T2

R21

3 T2

R21

2 T2

R21

1 T2

R21

0 T2

R29

T2

R28

T2

R27

T2

R26

T2

R25

T2

R24

T2

R23

T2

R22

T2

R21

T2

R20

T2

R2

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

T2C

215

T2C

214

T2C

213

T2C

212

T2C

211

T2C

210

T2C

29

T2C

28

T2C

27

T2C

26

T2C

25

T2C

24

T2C

23

T2C

22

T2C

21

T2C

20

T2C

2 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

—

—

TF

F TF

AE

TF

E

RFF

R

FAF

RFE

FS

TAT

0 0

0 0

0 0

0 0

0 0

0 0

1 0

0 1

—

—

—

—

—

—

—

—

—

OTE

D

ME

C

KE

P

1 P

IE

P0

PO

E

ER

RR

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 C

HK

SUM

15

CH

KSU

M14

C

HK

SUM

13

CH

KSU

M12

C

HK

SUM

11

CH

KSU

M10

C

HK

SUM

9 C

HK

SUM

8 C

HK

SUM

7 C

HK

SUM

6 C

HK

SUM

5 C

HK

SUM

4 C

HK

SUM

3 C

HK

SUM

2 C

HK

SUM

1 C

HK

SUM

0 C

HK

SU

M

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

—

—

—

—

ISV

EC

3 IS

VE

C2

ISV

EC

1 IS

VE

C0

ISV

EC

0

0 0

0 0

0 0

0 0

0 0

0 1

1 1

1 —

—

—

—

—

—

—

—

T2

C1

T2D

IV2

T2D

IV1

T2D

IV0

T2M

D

CC

F1

CC

F0

C/T

2 T2

CFG

2 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

—

—

—

—

—

—

IN

P

BU

SY

S

TA0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

—

—

—

EIR

O

FS

—

—

—

IE

SM

OD

FE

DE

S

MD

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

FT

F FR

F TX

FT1

TXFT

0 R

XFT

1 R

XFT

0 O

E

FEN

FC

ON

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

W

U

FP1

FP0

INE

A

UT

INIT

LU

N1

LUN

0 C

NT0

0

0 0

0 0

0 0

0 1

0 0

0 1

0 0

0 —

—

—

—

—

—

—

—

—

—

—

D

MIS

P

M

HD

O

FBS

B

TH

CN

T2

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

IDFB

H5

IDFB

H4

IDFB

H3

IDFB

H2

IDFB

H1

IDFB

H0

—

—

IDFB

L5

IDFB

L4

IDFB

L3

IDFB

L2

IDFB

L1

IDFB

L0

IDFB

0

0 1

1 1

1 1

1 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

S

AD

DR

7 S

AD

DR

6 S

AD

DR

5 S

AD

DR

4 S

AD

DR

3 S

AD

DR

2 S

AD

DR

1 S

AD

DR

0 S

AD

DR

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

S

AD

EN

7 S

AD

EN

6 S

AD

EN

5 S

AD

EN

4 S

AD

EN

3 S

AD

EN

2 S

AD

EN

1 S

AD

EN

0 S

AD

EN

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

Tab

le 4

. Per

iph

eral

Reg

iste

r B

it F

un

ctio

ns

and

Res

et V

alu

es (

con

tin

ued

)

MA

XQ

76

67


______________________________________________________________________________________ 37

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0B

T15

BT1

4 B

T13

BT1

2 B

T11

BT1

0 B

T9

BT8

B

T7

BT6

B

T5

BT4

B

T3

BT2

B

T1

BT0

B

T 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 TM

R15

TM

R14

TM

R13

TM

R12

TM

R11

TM

R10

TM

R9

TMR

8 TM

R7

TMR

6 TM

R5

TMR

4 TM

R3

TMR

2 TM

R1

TMR

0 TM

R

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

BS

TT

BD

S

—

—

—

—

BP

H9

BP

H8

BP

H7

BP

H6

BP

H5

BP

H4

BP

H3

BP

H2

BP

H1

BP

H0

BP

H

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

BD

IV3

BD

IV2

BD

IV1

BD

IV0

BP

OL

BC

KS

B

TRI

BG

T B

CTN

7 B

CTN

6 B

CTN

5 B

CTN

4 B

CTN

3 B

CTN

2 B

CTN

1 B

CTN

0 B

TRN

1

0 0

1 0

1 0

0 0

0 0

0 0

0 0

0 —

—

—

—

S

AR

MX

2 S

AR

MX

1 S

AR

MX

0 S

AR

DIF

S

AR

BIP

S

AR

DU

L S

AR

RS

EL

SA

RA

SD

S

AR

BY

S

AR

C2

SA

RC

1 S

AR

C0

SA

RC

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

LN

AO

SE

L LN

AIS

EL1

LN

AIS

EL0

—

R

CV

GN

4 R

CV

GN

3 R

CV

GN

2 R

CV

GN

1 R

CV

GN

0 R

CV

C

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

—

—

—

—

—

PLL

C1

PLL

C0

PLL

F8

PLL

F7

PLL

F6

PLL

F5

PLL

F4

PLL

F3

PLL

F2

PLL

F1

PLL

F0

PLL

F 0

0 0

0 0

0 0

1 0

0 0

0 0

0 0

0 —

—

—

—

—

—

—

—

X

TIE

V

IBIE

V

DB

IE

VA

BIE

C

MP

IE

LFLI

E

LPFI

E

SA

RIE

A

IE

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

CM

PP

C

MP

H14

C

MP

H13

C

MP

H12

C

MP

H11

C

MP

H10

C

MP

H9

CM

PH

8 C

MP

H7

CM

PH

6 C

MP

H5

CM

PH

4 C

MP

H3

CM

PH

2 C

MP

H1

CM

PH

0 C

MP

C

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

CM

PT1

5 C

MP

T14

CM

PT1

3 C

MP

T12

CM

PT1

1 C

MP

T10

CM

PT9

C

MP

T8

CM

PT7

C

MP

T6

CM

PT5

C

MP

T4

CM

PT3

C

MP

T2

CM

PT1

C

MP

T0

CM

PT

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

VIO

LVL

DV

LVL

AV

LVL

CM

PLV

L —

—

—

X

TRD

Y

XTI

V

IBI

VD

BI

VA

BI

CM

PI

LPFF

L LP

FRD

Y

SA

RR

DY

A

SR

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 —

—

—

—

S

AR

D11

S

AR

D10

S

AR

D9

SA

RD

8 S

AR

D7

SA

RD

6 S

AR

D5

SA

RD

4 S

AR

D3

SA

RD

2 S

AR

D1

SA

RD

0 S

AR

D

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

FFIL

3 FF

IL2

FFIL

1 FF

IL0

FFD

P3

FFD

P2

FFD

P1

FFD

P0

FFO

V

—

—

—

FFLD

FF

LS2

FFLS

1 FF

LS0

LPFC

0

0 0

0 0

0 0

0 0

0 0

0 0

1 1

1 —

—

—

—

—

—

—

—

—

—

—

—

S

AR

CD

1 S

AR

CD

0 X

TE

RC

E

OS

CC

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 B

PFI

15

BP

FI14

B

PFI

13

BP

FI12

B

PFI

11

BP

FI10

B

PFI

9 B

PFI

8 B

PFI

7 B

PFI

6 B

PFI

5 B

PFI

4 B

PFI

3 B

PFI

2 B

PFI

1 B

PFI

0 B

PFI

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 B

PFO

15

BP

FO14

B

PFO

13

BP

FO12

B

PFO

11

BP

FO10

B

PFO

9 B

PFO

8 B

PFO

7 B

PFO

6 B

PFO

5 B

PFO

4 B

PFO

3 B

PFO

2 B

PFO

1 B

PFO

0 B

PFO

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 LP

FD15

LP

FD14

LP

FD13

LP

FD12

LP

FD11

LP

FD10

LP

FD9

LPFD

8 LP

FD7

LPFD

6 LP

FD5

LPFD

4 LP

FD3

LPFD

2 LP

FD1

LPFD

0 LP

FD

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

LPFF

15

LPFF

14

LPFF

13

LPFF

12

LPFF

11

LPFF

10

LPFF

9 LP

FF8

LPFF

7 LP

FF6

LPFF

5 LP

FF4

LPFF

3 LP

FF2

LPFF

1 LP

FF0

LPFF

N

OT

INIT

IALI

ZE

D

—

RB

UFE

R

SA

RE

B

GE

LR

IOP

D

LRD

PD

LR

AP

D

VIB

E

VD

PE

V

DB

E

VA

BE

S

AR

E

PLL

E

MD

E

LNA

E

BIA

SE

A

PE

0

0 0

0 0

0 0

0 1

0 0

0 0

0 0

0

Tab

le 4

. Per

iph

eral

Reg

iste

r B

it F

un

ctio

ns

and

Res

et V

alu

es (

con

tin

ued

)

MA

XQ

76

67


38 ______________________________________________________________________________________

RE

GIS

TE

R B

IT

RE

GIS

TE

R15

1413

1211

109

87

65

43

21

0[1

5:0]

FG

AIN

0x

7B5C

[1

5:0]

B

1CO

EF

0x24

92

[15:

0]

B2C

OE

F 0x

5820

[1

5:0]

B

3CO

EF

0x24

10

[15:

0]

A2A

0x

30F4

[1

5:0]

A

2B

0x33

69

[15:

0]

A2D

0x

3A28

[1

5:0]

A

3A

0xE

20E

[1

5:0]

A

3B

0xE

1E3

[15:

0]

A3D

0x

E55

9

Tab

le 4

. Per

iph

eral

Reg

iste

r B

it F

un

ctio

ns

and

Res

et V

alu

es (

con

tin

ued

)

Bits

ind

icat

ed b

y “S

T” r

efle

ct th

e in

put

sig

nal s

tate

.

Bits

ind

icat

ed b

y “P

” ar

e cl

eare

d to

00h

on

PO

R a

nd th

en, i

f req

uire

d, i

nitia

lized

to a

val

ue s

tore

d w

ithin

the

flash

info

rmat

ion

blo

ck.

Bits

ind

icat

ed b

y “D

B”

have

rea

d/w

rite

acce

ss o

nly

in b

ackg

roun

d o

r d

ebug

mod

e. T

hese

bits

are

cle

ared

afte

r a

PO

R.

Bits

ind

icat

ed b

y “D

W”

are

only

writ

ten

to in

deb

ug m

ode.

The

se b

its a

re c

lear

ed a

fter

a P

OR

.

The

OS

CC

reg

iste

r is

cle

ared

to 0

002h

afte

r a

PO

R a

nd is

not

affe

cted

by

othe

r fo

rms

of r

eset

.

MA

XQ

76

67


______________________________________________________________________________________ 39

Applications InformationDevelopment and Technical Support

A variety of highly versatile, affordably priced develop-ment tools for this µC are available from Maxim andthird-party suppliers, including:

– Compilers

– Evaluation kit

– Integrated development environments (IDEs)

– JTAG-to-serial converters for programming anddebugging

A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools.

Technical support is available at https://support.maxim-ic.com/micro.

Additional DocumentationDesigners must have the following documents to fullyuse all the features of this device. This data sheet con-tains pin descriptions, feature overviews, and electricalspecifications. Errata sheets contain deviations frompublished specifications. The user’s guides offerdetailed information about device features and opera-tion. The following documents can be downloaded from www.maxim-ic.com/microcontrollers.

• This MAXQ7667 data sheet, which contains electri-cal/timing specifications and pin descriptions.

• The MAXQ7667 revision-specific errata sheet(www.maxim-ic.com/errata).

• The MAXQ7667 Family User's Guide, which containsdetailed information on core features and operation,including programming.

Package InformationFor the latest package outline information and land patterns, goto www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

48 LQFP C48+2 21-0054

LQFP

+

MAXQ7667

TOP VIEW

AIN1 37

AIN2 38

AIN3 39

AIN4 40

N.C. 41

DGND 43

DVDDIO 44

BURST 45

42DVDD

47P1.1/TMS48 P1.2/TDI

46P1.0/TDO

1

P1.3

/TCK

2

P1.4

/MOS

I

3

P1.5

/MIS

O

4

P1.6

/SCL

K

5

P1.7

/SYN

C/SS

6

DVDD

7

DGND

8

DVDD

IO

9

PO.O

/URX

10

PO.1

/UTX

11

PO.2

/TXE

N

12

PO.3

/TO/

ADCC

TL

GATE524

REG3P323

REG2P522

XOUT21

XIN20

DGND18

DVDDIO17

PO.7/T2B16

DVDD19

PO.5/T114

PO.4/TOB13

PO.6/T215

AINO

3536

REFB

G

34

REF

33

AGND

32

AVDD

31

AGND

30

ECHO

P

29

ECHO

N

28

AGND

27

AVDD

26

FILT

25

RESE

T

Pin Configuration

Chip InformationPROCESS: CMOS

http://pdfserv.maxim-ic.com/package_dwgs/21-0054.PDF

MA

XQ

76

67


Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISION NUMBER

REVISION DATE

DESCRIPTION PAGES CHANGED

0 4/09 Initial release —

1 7/09 Updated Ordering Information to indicate automotive qualified part 1

Documents

19-4598; Rev 1; 7/09 EVALUATION KIT 16-Bit, RISC, Microcontroller-Based, Ultrasonic ... · 2010. 1. 27. · time-of-flight ultrasonic distance-measuring solution. The device is optimized