18-545: Final Report – Solid State DriveWinston Wan, Tao Yang, and Timothy Tan

Carnegie Mellon University{wwan1, taoy, tgt}@andrew.cmu.edu

December 9, 2009

Contents

1 Introduction 4

2 Purpose and Goals 4

3 System Overview 4

4 System Setup 54.1 Hardware for SSD components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.2 Software for SSD components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.3 Software for Virtex-5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 Custom-fabricated SODIMM 65.1 Why use the SODIMM slot? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65.2 Components of the SODIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65.3 Voltage issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75.4 Schematic, Layout and other details . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Host Interface 76.1 Host Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96.3 Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96.4 PCI Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Flash Translation Layer 97.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107.2 Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107.3 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.4 Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.4.1 Handling Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.4.2 Finding Free Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.4.3 Erasing Obsolete Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.5 Data Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8 DDR2 SDRAM Controller 12

9 NAND Peripheral 129.1 FSL Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139.2 Page Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149.3 ECC Calculation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149.4 NAND Controller Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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10 NAND Controller 1410.1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410.2 Initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410.3 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510.4 Controller Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.4.1 Read Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610.4.2 Write Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710.4.3 Erase Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710.4.4 Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10.5 NAND Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810.6 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

11 State of the System 19

12 Running the System 2012.1 Block Device Driver, PCI Express DMA Kernel Module, Basic FTL . . . . . . . . . 20

13 Major Decisions and Issues 2013.1 SATA vs. PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2013.2 Software vs. Hardware FTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113.3 FTL Design and Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113.4 FTL vs Memory Technology Device (MTD) . . . . . . . . . . . . . . . . . . . . . . . 2113.5 FPGA Board Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113.6 Motherboard Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213.7 Processor Local Bus vs Fast Simplex Link . . . . . . . . . . . . . . . . . . . . . . . . 2213.8 NAND controller implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

14 Unexpected Issues 22

15 Words of Wisdom 23

16 Future Work 24

17 Individual Contributions 2417.1 Winston Wan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417.2 Tao Yang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2517.3 Timothy Tan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18 Class Impressions/Improvements 26

19 References 26

A Custom-fabricated SODIMM Design Details 29A.1 Original Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29A.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33A.3 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38A.4 Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40A.5 Silk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46A.6 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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A.7 End Product/Photos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

List of Figures

1 Top level system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 The entire setup - 11 computers and counting . . . . . . . . . . . . . . . . . . . . . . 63 SODIMM components block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PCIe Interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 FTL components block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Flash page header definition (in undefined bits of page) . . . . . . . . . . . . . . . . 117 “Interface FSM” for the NAND Peripheral . . . . . . . . . . . . . . . . . . . . . . . . 138 FSM for NAND commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 FSM for NAND read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710 FSM for NAND write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711 FSM for NAND erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812 FSM for other NAND commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813 Frontal view of the custom-fabricated SODIMM . . . . . . . . . . . . . . . . . . . . 5114 Rear view of the custom-fabricated SODIMM . . . . . . . . . . . . . . . . . . . . . . 5115 Xilinx LX110T board with the custom-fabricated SODIMM installed, inserted into

a PCI Express x1 lane on the Gigabyte GA-G31M-ES2L motherboard . . . . . . . . 52

List of Tables

1 Host DMA communication protocol over PCIe . . . . . . . . . . . . . . . . . . . . . 92 NAND Controller - Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 NAND Controller - NAND signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Decision Matrix for Host Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . 215 Decision Matrix for FTL Implementation . . . . . . . . . . . . . . . . . . . . . . . . 21

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1 Introduction

This final report covers the progress that was made on the FPGA-based Solid State Drive (SSD)project during the Fall 2009 semester. We outline the details of our system, document the decisionsthat have been made, provide directions understanding and using the project, and give insights tofuture developments that may be made in continuation.

2 Purpose and Goals

The purpose of this project is to create a flexible, extensible platform by adapting an FPGA as aSSD controller. We hope that the system will facilitate rapid SSD controller research and testingin the future.

The initial primary goal for the end of this semester was to be able to connect the FPGA toa host computer via Serial ATA, mount the SSD on a computer and verify reads and writes to thedrive. Midway through the project, due to time constraints, the implementation of the Serial ATAinterface was dropped in favor of one using the PCI Express interface and a custom-written blockdevice driver.

As of the end of the Fall 2009 semester, the PCI Express and block device driver host inter-face, the custom SODIMM, and a rudimentary FTL was complete. The NAND chip controllerand FSL connection to the FTL was fully implemented and simulated, but encountered issues withdeployment to real hardware. However, a demostration of the drive capabilities from the hostperspective was possible by using DRAM on the custom SODIMM as temporary storage in placeof the permanent Flash storage.

3 System Overview

The FPGA-based SSD can be viewed as four major subsystems:

1. the PCIe host interface with the PC and a customized block device driver

2. the Flash Translation Layer (FTL) that provides the hard disk abstraction and managementof the flash NAND chips

3. the DDR2 DRAM memory chip on the custom-fabricated SODIMM and the modified con-troller required to access it

4. the NAND Flash storage on the custom-fabricated SODIMM and the peripheral and controllerneeded to access it

Figure 1 below shows a diagram of these subsystems. These four major subsystems are imple-mented in a combination of three methods - physical hardware, programmed hardware (FPGA)and software.

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Figure 1: Top level system diagram

4 System Setup

4.1 Hardware for SSD components

• Xilinx Virtex-5 LX110T FPGA

• Gigabyte GA-G31M-ES2L motherboard

• Intel Core 2 Duo processor (LGA775)

• 2GB DDR2 SDRAM

• Custom-fabricated SODIMM (with NAND chips and DDR2 SDRAM)

• (optional) 48-pin TSOP socket for testing a single NAND chip.

4.2 Software for SSD components

• Ubuntu Linux running kernel version 2.6.28.16

• Modified PCI Express DMA kernel device driver

• Custom block device driver

4.3 Software for Virtex-5 Programming

• Windows XP (downloading a bitstream in Windows Vista/7 doesn’t seem to work right)

• Xilinx ISE, EDK and XPS 11.3

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Figure 2: The entire setup - 11 computers and counting

5 Custom-fabricated SODIMM

The SODIMM that was custom-fabricated for this project consisted of an array of four 16 Gb MicronNAND Flash chips for storage, one 256 Mb DDR2 DRAM chip, and a Complex ProgrammableLogic Device (CPLD) for voltage translation between the flash chips and the FPGA. All theseelements share the 122 usable signal pins on the SODIMM.

5.1 Why use the SODIMM slot?

The SODIMM slot was chosen to be used as expansion header for our NAND and DDR2 SDRAMchips due to the large number of pins available for data and signal transfer, and because the signalrouting for the SODIMM pins are known to be able to tolerate a 266 MHz clock. Unfortunately theXGI expansion headers on the LX110T have no published maximum signal speed rating, as far aswe could tell. As our NAND chips can be clocked as fast as 50 MHz, signal integrity is importantand we thus went with the safer option of using the SODIMM slot.

5.2 Components of the SODIMM

• NAND Flash - 4 x 16 Gbit Micron MT29F16G08DAAWP

• DDR2 SDRAM - 256 Mbit Micron MT47H32M8-37E

• CPLD - Xilinx CoolRunner-II XC2C256 (FT256)

• JTAG header - Digikey: S6009-07-ND

• 4-pin power header - Digikey: A30513-ND

• 2-pin power header - 2 x Digikey: A30511-ND

• Several sets of capacitors for decoupling, according to the Qimonda DDR2 Design Guide(refer to Appendix A.1 for more information)

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Figure 3: SODIMM components block diagram

Our design called for each NAND chip to be wired up through the CPLD to the FPGA indepen-dently (as opposed to chaining them together like a RAID-0 setup). This allows for the greatestflexibility in routing signals, at the expense of being able to squeeze one or two more chips into thecustom SODIMM for a larger overall capacity (we trade more control signals for fewer data buses).Also, the DDR2 SDRAM chip had to be appropriately wired up, as there were some restrictionson the FPGA pins (and thus SODIMM pins) it can connect to.

The CPLD has two main banks - they are configured to run at 1.8V (LVCMOS18 IOSTANDARD)and 3.3V (LVCMOS33 IOSTANDARD) respectively. Signals were carefully routed to the banksrunning at their respective voltage levels. Also, all remaining signal pins on the SODIMM that didnot have a signal assigned were still connected to the CPLD as spares.

Last but not least, as the SODIMM slot did not provide 3.3V rails, power headers were mountedon the custom SODIMM, allowing us to connect an external 3.3V source to it. Additional powerheaders were also provided for the various 1.8V rails, just in case the need arose.

5.3 Voltage issues

Since DDR2 specifies a voltage of 1.8V but the NAND flash chips operate at 3.3V, voltage transla-tion is required. Instead of going with traditional voltage translation devices, a CPLD was used toperform the said translation as it was of a much more compact size and suited our space restrictionswell. The DDR2 DRAM chip runs natively at 1.8V, and so does not pass through the CPLD.

5.4 Schematic, Layout and other details

The schematic, layout, pictures, and other details of the Custom-fabricated SODIMM can be foundin Appendix A.

6 Host Interface

The host interface that was decided to be the most effective and simple to implement was the directPCIe connection between the PC host and the Virtex 5 FPGA board. Since read/write commandssent to the drive must be translated to a format that can be sent and interpreted over a PCIeinterface, a block device driver was developed to handle the abstraction for the operating system,a protocol for data transfer was defined for communication over PCIe, and code was adapted to

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facilitate the use of the PCIe port. The figure below shows the layered structure of the hostinterface, where the block device abstraction is built on top of the character device abstraction ofthe PCI device. The physical data transfer is implemented by the operating system through DirectMemory Access (DMA).

Figure 4: PCIe Interface block diagram

6.1 Host Components

The host, commonly the PC, side of the PCIe connection has all of the hardware in place, andmuch of the software stack is provided by the operating system. In Linux, PCI devices are char-acter devices that stream data, whereas a disk is a randomly addressable block device. A blockdevice driver is needed to provide a block layer on top of the existing PCI functionality. Code wasadapted from a previous project by Eric Chung that implemented the PCI drivers for the Virtex5 LX110T FPGA. These existing components are shown as the highlighted blocks in the figureabove. To adapt the code for our purposes, the “DMA Driver” code that was implemented in userspace by Chung was moved into kernel space by removing the memory mappings to user space andremoving the need to open the PCI device with a file descriptor. In the first implementation of thenew kernel module, we attempted to merge the block device driver into the existing code to createa single module. We ran inconsistent crashing of the kernel using this design, which may have beencaused by the fact that the module was trying to act as a PCI driver and a block device driver atthe same time. After exporting the read/write function symbols in the PCI portion of the module,the block device driver was split into a separate module which called the PCI read/writes.

It is important to note that these drivers are highly dependent on the kernel version 2.6.28. BetweenLinux 2.6.28 and 2.6.31, the block subsystem went through many changes in respect to the eleva-tor and request architectures. Currently, we use the old and simplest form of the request system.A point of future progress would be to remove the use of the request and directly use the blockinput/output structure, the bio. This will reduce overhead because a solid state drive has no need

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for queuing and consolidating requests like a physical disk does, and efficiency optimizations shouldbe primarily placed in the Flash Transition Layer, or any specialized solid state drive managementsystem, whether onboard or on the host.

6.2 Board Components

The hardware required on the FPGA side of the PCI interface consists of a large 8 KB data bufferand a set of control registers. This memory space allows DMA transactions between the PC andthe board. A controller that is part of the FTL on the FPGA board manages the signaling. Thedata buffer is treated like an address mapped queue by the MicroBlaze code, which can make readand writes to the queue. It is important that the size of each data transfer match both on theMicroBlaze and the host.

The code on the MicroBlaze simply waits to read one synchronization byte, which then lets aconstant loop of receiving and responding to requests. The command protocol that was definedis described below. The code also performs any necessary initialization of the MicroBlaze cachespre-synchronization and runs the FTL initialization of the drive.

6.3 Command Flow

A read or write command is issued by the kernel driver when reads are needed or when the kerneldata caches run out of space. These calls are mapped in a device struct to functions in the kernelmodule. These functions then complete the action by setting the DMA control registers to signalthe device. Table 1 describes these steps in detail.

Step Read command Write command1 Reset the device control register (DCR) Reset the DCR2 Determine values for size and count registers Copy data into data buffer3 Store address into read address register Determine values for size and count registers4 Signal read command register Store address into read address register5 Wait for response in status register Signal write command register6 Copy data out of data buffer Wait for count register to empty

Table 1: Host DMA communication protocol over PCIe

6.4 PCI Command Protocol

The simple protocol currently implemented for communication over PCIe is as follows:

1. Send 8-byte header with logical block address and command type

2. Send or read a full page of data associated with that logical block address

7 Flash Translation Layer

The Flash Translation Layer receives commands and data through the PCIe interface, and outputstranslated commands with the data to the NAND chip controller. At the host interface, the FTLmust provide the logical block abstraction for the disk drivers to treat the device as a disk. At

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the storage interface, the FTL must maintain the health of the NAND chips. Lastly, the FTLimplements caching to improve performance. Each operation in the FTL must be transactionallysafe, which means that power loss to the system at any point in any data transfer should notcorrupt the system.

Figure 5: FTL components block diagram

7.1 Initialization

When the drive is started, the FTL immediately begins to probe the header block of each page inorder to set up the necessary data structures in memory. Although initialization is slow, storing alldrive metadata on each page allows simpler algorithms and eliminates the concern about certaintable pages receiving high write loads.

If two pages are discovered to contain the same Logical Block Address (this can only occur due toan improper shutdown), the page with the higher physical address will be invalidated. Pages foundto have invalid LBAs will also be likewise invalidated.

7.2 Command Flow

The FTL listens to the DMA registers for new commands. When a command is received, the logicalblock address known by the host must be translated into the physical address of a page on one ofthe Flash chips using the mapping tables. In the case of a read, data is forwarded from the chipsto the DMA data buffer. In the case of a write, a free page must be found to write the data to.The new page is assigned the same logical block address as the old page that used to hold thepage being written. Finally, the old page is invalidated and updates to the erase priority queue aremade. With a cache-suppported system, which is not currently implemented, the logical addresswill be searched for in the cache, thus eleiminating the need to access the Flash chips.

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7.3 Address Mapping

A Logical Block Address to Physical Address mapping is maintained by the FTL through a one-level page table. During each read or write, these tables will be accessed to achieve the translation.The tables are loaded into memory during initialization of the drive by reading the headers for eachpage. When a new page is written, first all the data is copied to the new page. Then, the headersare set with the same logical block address as the old page. Finally, the old page can be invalidatedand the in-memory table can be updated.

7.4 Block Management

Blocks and pages on the storage chips are subject to a number of states, such as free vs. used, validvs. invalid, or bad. This information is used by the Block Management system to determine thelocation of the next free page. Block management is maintained in memory and implemented as asoftware algorithm, but the backing metadata is transactionally persistent in the headers for eachpage. Wear leveling is a block management algorithm that determines when to erase pages, andwhich pages to erase. Repeated use of the same pages is avoided by neglecting to erase pages withheavy use.

Figure 6: Flash page header definition (in undefined bits of page)

7.4.1 Handling Bad Blocks

During initialization, a block is found to be bad if the bad block bit in any page is set to 1. Thesebits will be stored in a bit array that acts as a bad block table in memory. When searching forfree pages, this bit array will be indexed into by the block number in the physical page address.This feature is not currently implemented since the demonstration version runs on DRAM storage,which has no risk for bad blocks.

7.4.2 Finding Free Pages

Free physical blocks will be maintained in an implicit list. A new free block is not needed untilthe previous one is completely allocated. Free pages in storage will be allocated sequentially froma physical block, since pages are mapped to logical blocks anyway. The current implementation ofthis feature is to consecutively issue free pages, without consideration for the block number, sinceerases have not been completed. Clearly, should the target of the next free page were to extendpast the end of the capacity of the drive, a fatal error will arise.

7.4.3 Erasing Obsolete Pages

When a page is marked obsolete, or found as obsolete during initialization, the block it belongs tois stored into a priority queue sorted by the priority of the block being erased. This priority will

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be determined by a formula that accounts for the block’s wear count and number of obsolete pagesit contains. The more obsolete pages in a block, the more effecient the block erasure will be to freepages. The higher the wear count, the less advantangeous it is to further progress that count, sinceat some point we risk losing blocks due to lifetime. This operation is the most critical operationfor an effective solid state drive, and therefore deserves additional attention and consideration. Inthe future, many strategies for optimizing erases should be compared.

7.5 Data Caching

Caching pages as they are read is a common way to drastically improve performance in transaction-intensive systems. There is currently no caching implemented in the system, but there are manyways in which our design supports caching. Function prototypes for cached reads and writes havebeen included in the FTL code, and the DDR2 controller is already in place. By caching data intoRAM, better performance is expected, since the DDR2 reads are slightly faster than the NANDreads. However, caching introduces many transaction and consistency issues that will need to bedesigned against.

8 DDR2 SDRAM Controller

The default DDR2 SDRAM controller that comes with the Xilinx LX110T board that we are usingis meant to be used with a 256MB DDR2 SDRAM SODIMM (with four 512 Mb chips on it).However, since we are interfacing our custom-fabricated SODIMM which only contains one 256 MbDDR2 SDRAM chip, there is thus has a very different routing and signalling scheme compared tothe original SODIMM module, and so the controller must be modified.

With reference to the Xilinx Multi-Port Memory Controller (MPMC) Data Sheet, there are stepsto be followed to use Xilinx’s Core Generator (Coregen) tool to prepare a new MPMC core that istailored to our single DDR2 SDRAM chip. Once a new core is generated, the Universal ConstraintsFile (UCF) has to be modified to reflect the specific SODIMM pins (and thus FPGA pins) thatwe will be routing our signals through. Once this is done, the UCF file is verified to be correctusing Coregen, and converted to work with the existing PCIe project we started with. Unfortu-nately things (as usual) didn’t go as per Xilinx’s plan, and there were many perplexing synthesiserror messages that resulted from the drop from 256MB to 32MB of DDR2 SDRAM - errors thatconsumed yet more time to guess and attempt to resolve.

Nonetheless, a working DDR2 SDRAM controller was eventually synthesized correctly, and testsfor accuracy passed.

9 NAND Peripheral

The NAND Peripheral is connected to the MicroBlaze via bi-directional Fast Simplex Links (FSL).The peripheral also contains a Block RAM (BRAM) buffer, an Error Correcting Code (ECC)module and the NAND Controller module. The peripheral is driven by an “interface FSM” asshown in Figure 7.

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Figure 7: “Interface FSM” for the NAND Peripheral

9.1 FSL Communication

The FSL was selected over the PLB due to its higher data transfer rate achieved during character-ization tests.

Any request is always enacted from the Microblaze, and so the interface FSM in the Nand Pe-ripheral idles in the “In Control” state. When the Microblaze sends a request to the peripheral,it first sends a two-dword long header (each transfer is 1 dword in width), giving the command,size of the request (if any) and the address to perform the request on. In the case of a Write,the interface FSM will continue reading in the specified number of bytes into a local BRAM pagebuffer. For Reads and Erases, control is passed to the NAND controller.

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9.2 Page Buffering

Data is buffered in the BRAM page buffer in order to facilitate the calculation of ECC checksums(in the case of a write) and the verification of data read from the NAND controller (in the case ofa read). Since the data is buffered, corrections to bit errors are easy.

9.3 ECC Calculation and Verification

A ECC module was written to do process 32 bits at an instance, to perform realtime calculation ofthe checksum as the data is streamed in. The ECC algorithm allows for Single Error Correction,Double Error Detection (SECDED). The interface FSM calculates and verifies ECC during eachread or write of 4096 bytes (one logical block), and tags it to the ECC checksum to the end of thepage (pages are 4314 bytes). As such, this whole process and the extra bytes for ECC are totallytransparent to the host system.

9.4 NAND Controller Communication

To initiate a transaction, the host will first signal the address and command to the NAND controller,and give a start signal in the status register. The interface FSM will also be watching the statusregisters for signs from the NAND controller that it is sending data out, so that the data can bebuffered and then verified.

10 NAND Controller

The interface FSM and the controller will communicate through a custom designed protocol. Onthe other end the nand controller will be issuing commands to the flash chip through the nandinterface, which will be mapped to the pins on the SODIMM slot.

10.1 Signal Description

Table 2 contains the descriptions for all the top level ports of the NAND controller module hand-shaking with the NAND peripheral FSM, and Table 3 contains the descriptions of the the top levelports connected to the physical NAND chips.

Note: Signals i, o, dir are merged into a single bidirectional IO bus at the top level. The reasonthey are separate here is because the Virtex 5 does not support tri-state buffers except at the toplevel driving external ports.

10.2 Initialization sequence

According to the Micron datasheet, the NAND chip requires at least 100 ns after Vdd reaches 2.5Vto stabilize. Therefore, upon receiving a reset from the interface logic, the controller will count upto 16384 before start accepting commands (assuming the clock cycle is at least 10ns). Once thatis completed, the controller will signal DONE so the interface FSM can start issuing commands.Though not explicitly designed, the first two commands from the interface FSM must be RESETcommands to both chips, according to the datasheets. After both resets are done, the NAND chipsare available for normal usage.

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Signal Type Descriptionclk I Clock, should be between 20-100 Mhzreset I On posedge, resets the NAND controllerDONE O Signals the end of a transaction to the interface FSMDATA DONE O Signals the byte has been written, ready to receive new dataDATA READY O Signals the byte read from the NAND chip is in DATA OUTStatus[7:0] O Stores the results of a read status commandsDATA OUT[7:0] O Stores the byte read from the NAND chip, only valid after DATA READYDATA IN[7:0] I On a write, interface FSM will put the data into DATA INADDR[31:0] I Indicates the target address

ADDR[31]: chip select within the deviceADDR[30:19]: block address within a chipADDR[18:13]:page address within a blockADDR[12:0]: column address within a page

CMD[2:0] I Indicates the CMD0: Reset 1:Read status 2:Block erase3: Program page 5:Read Page

DATA LOADED I Indicate the data to be written is in DATA INCMD LOADED I Indicate the next command is in CMDLEN[12:0] I Indicate the number of bytes to be read/written

Table 2: NAND Controller - Interface signals

Signal Type Descriptionn ce1 l O Chip enable for the first chipn ce2 l O Chip enable for the second chipn ale O Address latch enable, indicate the address is being latchedn cle O Command latch enable, indicate commands are being latchedn re l O Read enable, strobe to transfer data from NAND chip to controllern we l O Write enable, strobe to transfer data from controller to NAND chipn o[7:0] O Data output from FPGA to NAND chipn i[7:0] I Data input from NAND to FPGAdir O Indicate direction of CPLD data,tied directly to re ln rb1 l I Ready/Busy from chip 1n rb2 l I Ready/Busy from chip 2

Table 3: NAND Controller - NAND signals

10.3 Protocols

To initiate a transaction, the host will first put commands into CMD, and assert CMD LOADED.For a read/write/erase operation, address should also be put in ADDR, length into LEN beforeCMD LOADED is asserted. CMD LOADED and CMD can be de-asserted in the following cycle.However LEN and ADDR [31] need to be held throughout the transaction. Once the CMD isreceived, the controller will move to different states depending on the command.

Read:

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The controller will move to the read state, issue the instruction to the nand chip, and start readingdata from the NAND chip by strobing re l. Then it will put the data in DATA OUT and signalsDATA READY. Note the controller does not require another explicit handshake at this point, itwill move on to read the next byte, therefore the controller must pick up the data in DATA OUTwithin 2 cycles of DATA READY being asserted. The controller will continue to read data until itsinternal count reaches LEN. Note the NAND controller does not implement page bounds checking.In which case it will signal DONE after the last DATA READY to conclude the transaction.

Write:Similar to a read, the interface FSM will first put out CMD, ADDR, LEN and signals CMD LOADED.Note that CMD and LEN can be de-asserted after 12 cycles. Then the interface FSM can startputting out data to be written into DATA IN. After DATA LOADED is asserted and de-asserted inthe following cycle, the interface FSM will wait for DATA DONE to be asserted by the controller.After the last DATA DONE, the controller will assert DONE to conclude the transaction. Notesimilar to READ, bounds checking are not implemented.

Other commands:The controller will put command into CMD and assert CMD LOADED and then wait for DONE.In the case of Read status, the result of status will be put into the status port when DONE isasserted.

10.4 Controller Logic

The controller will be waiting in the start states until it sees rising edge of CMD LOADED. Asshown below:

Figure 8: FSM for NAND commands

10.4.1 Read Logic

To execute a read command, the controller first latches the command, followed by 5 cycles ofaddress. After another cycle of command, it will wait for the nand chip to toggle the R/B line.After that data can be read out sequentially by toggling re l line.

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Figure 9: FSM for NAND read command

10.4.2 Write Logic

Figure 10: FSM for NAND write command

The write logic is similar, after the address is latched in, the controller will start sending out thedata to the data registers on the nand chip by toggling the we l lines. After a command cycle tosignal the data transfer is done, the controller will wait for the nand chip to finish programming(250 us). A read status command is needed at the end of verify the integrity of the page writtento. The write command will fail (status [0] == 0) if the controller is writing to a used page.

10.4.3 Erase Logic

Since erase can only be done at the block granularity, only 3 address cycles will be needed. Uponsending the address, the controller will wait for the nand chip to signal done by toggling R/B lines(700 us). Like write, a read status command is needed at the end to verify the integrity of thepage.

10.4.4 Other Commands

The other commands (reset, read status) do not require address or data cycles. The controllersimply issues the command and wait for the reply from the nand chips. Read status is mostly used

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Figure 11: FSM for NAND erase command

Figure 12: FSM for other NAND commands

to verify if a transaction is successful.

10.5 NAND Chips

Each NAND chip constains 16Gb of storage and is operated through a 17 pin interface, driven bythe NAND controller. Each device consists of 2 dies, each with 8192 blocks, and each block contains64 page. Each page can store 4314 bytes of data. Typically, this is segmented into the first 4096bytes for actual data, 194 bytes for book keeping and as spare space, and the remaining 24 bytesfor storing a Single Error Correct, Double Error Detect (SECDED) Error Correcting Code (ECC).

The details of the pins and bus timing diagram will not be shown due to non-disclosure agree-ments.

10.6 Verification

The design is verified through simulation. Courtesy of Micron, we have an unsynthesizable verilogmodel for the NAND chip that we are using. Through simulation, we have verified the protocolsand more importantly, that all the timing constraints are met. We have also modeled a CPLD

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module after the NAND controller but before the NAND chip verilog model, to ensure that theextra delay through the CPLD will not cause our design to fail. We are still in the process ofverifying the NAND controller with real NAND chip.

11 State of the System

PCI Express DMA Kernel Module:This module was modified and is fully functional, and provided to the other SSD team to aid theirMTD development.

Block Device Driver, Basic FTL, DDR2 Controller, 32MB DDR2 SDRAM:These subsystems are fully operational and tested. The lab demonstration showed the capabilitiesof these parts to appear as a block drive and write data to temporary storage.

CPLD:The CPLD module was written and the RTL schematic generated by ISE matches our intent forthe device. However, more concrete tests should be run. This module was provided to the otherSSD team.

NAND Peripheral FSM, Fast Simplex Link, Buffer:These subsystems, while tested to work in simulation, have worked in hardware when standing byitself. However, hooking the NAND controller to it has not been successful yet. These subsystemsare provided to the other SSD team.

NAND Controller:The NAND controller was tested with the specific Micron simulation model for the chip we areutilizing, and it was successful. However, the controller has not been successfully integrated intohardware at this point. Currently, if the controller is run at a 50MHz clock, we do see the NANDchip responding to the reset commands given to both dies (ready/busy line goes down, then backup, deterministically). However, the NAND chip does not seem to be responding to any additionalcommands. One possibly to be explored is that the CPLD may not be passing signals to the NANDcontroller truthfully, especially on the bidirectional data bus. This is work in progress.

This component was worked on by both SSD teams.

ECC module:The ECC module was verified to be working in simulation, but has not been integrated into actualhardware yet.

Custom SODIMM:The custom SODIMM was completely designed, fabricated, and tested. There were two identicalparts produced, to be shared between the SSD teams.

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12 Running the System

12.1 Block Device Driver, PCI Express DMA Kernel Module, Basic FTL

1. Load the Xilinx XPS project “pcie04”.

2. Insert the Xilinx LX110T FPGA board onto the Gigabyte motherboard. Connect the serialcable to a computer to monitor debug messages.

3. Power on the Xilinx LX110T board and download the bitstream to the board before turningthe computer on. Once downloaded and the processor started, there should be some outputon the serial port regarding the initialization of the drive.

4. Turn on the computer.

5. If the driver is not compiled, run “make”.

6. Install the PCI Express DMA kernel device driver. (“sudo insmod ssd dma.ko”)

7. Load the custom block device driver. (“sudo ./ssd block load”)

8. The debug console should show that a synchronization byte was received.

9. Build a filesystem on the drive (“mkfs -t ext2 /dev/ssd blocka”)

10. Mount device to a mount point (“sudo mount /dev/ssd blocka drive”);

11. Create files on mounted device.

12. One good test is to reboot the system while the FPGA is still running. When the drive isremounted after reboot, the files created earlier should still exist. This ensures that you willnot be reading data cached by the OS.

13 Major Decisions and Issues

At this point in the project, there have been some major design decisions that have been made, aswell as some tricky issues of note.

13.1 SATA vs. PCIe

The decision of how the drive interfaced with the host computer was a choice between a direct PCIex1 connection and a SATA connection. The benefit of SATA was that it would not require anyspecial driver code and should work on any computer and operating system with SATA support.Unfortunately, the SATA network layers were deemed to complex to implement a hardware driverfor, especially since we did not have access to any suitable debugging tools, like a SATA protocolanalyser.

However, the rest of the system was nonetheless designed with the possibility of swapping thePCI express controller with a SATA controller in the future.

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Option Pros ConsSATA Plugs into any computer Complex design

Implements error checking Hardware implementationCommunication protocol predefined No suitable debug tools

PCIe Existing DMA code Must write custom block device driverMostly software Must find/define documentation

Table 4: Decision Matrix for Host Interface Protocol

13.2 Software vs. Hardware FTL

The decision to implement FTL logic in software was due to ease in development and debugging.System performance of this design is not dependant on the FTL, so the slower software FTLimplementation is irrelevant. Also, since the algorithms behind the FTL management have notbeen completely decided upon, it is important to maintain some flexibility in the implementation.

Option Pros ConsSoftware Easier to implement Processor and Bus are slow

Can change algorithms quicklyHardware Faster performance Harder to implement

FSM is appropriate

Table 5: Decision Matrix for FTL Implementation

13.3 FTL Design and Algorithms

The design details of the FTL are the least finalized portion of the overall system. Initial imple-mentation will begin with the design and algorithms outlined in Section 4. However, more researchwill be conducted in this area and the FTL may change as we discover or design more possiblesolutions.

13.4 FTL vs Memory Technology Device (MTD)

The MTD is a generic Linux subsystem created specifically for Flash memory devices that wasvery recently introduced. It is neither a block nor a character device. Although going the routeof implementing the MTD is easier, as all the necessary Flash management features are alreadyimplemented in the software stack, we decided to stick with implementing a traditional FTL forour SSD as that would give us the flexibility to swap out the PCI express controller and replace itwith a SATA controller in the future, as per the original plan.

13.5 FPGA Board Choice

The decision to use the Virtex 5 LX110T FPGA over the Virtex 5 FX was primarily based onthe fact that the existing PCIe interface code was written for the LX. Other considerations werethat the MicroBlaze processor on the LX board was fast enough to power the FTL, rendering thePowerPC on the FX unnecessary. The MicroBlaze offers better support for faster connections tomemory and the NAND controller via the Fast Simplex Link.

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13.6 Motherboard Compatibility

Inserting the the Virtex 5 LX110T board into the x16 lane slot on the lab’s Dell Precision’s moth-erboard caused it to fail to boot, after the FPGA and MicroBlaze processor was initialized. Wheninserted into the Dell’s x8 lane slot on the motherboard, the Virtex 5 LX110T was detected as aninvalid Network Interface Card. One suspected cause of this issue is that lane width negotiation onthe PCIe bus did not succeed. When we moved to the motherboard (Gigabyte GA-G31M-ES2L)that Eric Chung used for development of the PCIe Interface code, the Virtex 5 LX was detected inthe PCIe x1 slot.

13.7 Processor Local Bus vs Fast Simplex Link

Initially we were planning to use Processor Local Bus (PLB) to communicate between PowerPCcore and our controller logic. However after further study and characterization experiments, werealized that the PLB is very slow. Both DRAM and SRAM requests go through the PLB, andthe maximum observed throughput under 15MB/s. Characterization tests for the Fast SimplexLink (FSL) that connects the Microblaze directly to the peripheral show maximum throughput atapproximately 35MB/s.

Since the PLB is likely to be a performance bottleneck, we chose to use the FSL instead. Thedownside is by that time, we already designed the protocols for the controller module using PLBand memory mapped registers (probably no longer feasible given the speed of PLB anyway). Rather,we need to write a interface FSM to send/receive data packets from the FSL, decode them andissue commands to the controller. This unexpected increase in design complexity set our scheduleback considerably. However, this being an ongoing research project, we decided to optimize forbetter performance(we believe this will become the performance bottleneck), at the cost of ease ofimplementation.

13.8 NAND controller implementation

We have access to another NAND controller with ECC integrated into it, from Micron. While it wasdesigned for an older generation of NAND chips, for the Spartan III board, we were hoping to be ableto reuse the code there for our newer chips. Unfortunately, after further study we found out thatthere were pretty significant differences between the two chips. While the protocols were similar,the timing constraints are significantly different. It did not help that the NAND controller camewith relatively limited documentation. Although we know that the NAND controller implementedan SRAM interface to the Microblaze host, we could not find any examples or documentation onhow the embedded core is supposed to communicate via the interface. As such, in order to makeit work, significant modifications are needed. As the module is also written in VHDL, none of ushad any experience in it. In order to reduce the risk of introducing new bugs due to the generallack of familiarity with VHDL constructs, we decided to rewrite the NAND controller from scratchin Verilog.

14 Unexpected Issues

1. Nobody had expected that the Xilinx provided template file used by the Base System Builderfor the Xilinx LX110T boards that we were using had errors and generated a project that didnot synthesize. It took some time to debug before the root cause of the issues were found.Xilinx code can’t always be trusted.

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2. We had severely underestimated the amount of time needed to get the custom-fabricatedSODIMM design correct - selecting the right components and verifying all the connectionstook ages. Sending the SODIMM out for layout and fabrication also took longer than ex-pected, due to the company requiring us to verify their work after every stage.

3. After following all of Xilinx’s steps in their specifications sheet on how to modify and replacethe Multi-Port Memory Controller (MPMC) very closely, it was a major surprise that therewere countless error messages that appeared on synthesis, requiring plenty

4. The standard 14-pin Xilinx JTAG cable configuration is defined as having 7 pins connectedto ground, 1 pin connected to Vref (typically 1.5V - 5V), 4 pins connected to signals, and2 pins unconnected. Being the first time wiring up a JTAG connector to a device, we didnot realise that the Vref line is an input to both the CPLD as well as the USB programmingdongle - neither drove a voltage on the line. It took us a while to figure out what was wrong,and then come up with a quick hack to supply a voltage on the Vref line.

5. In the latest versions of the Linux Kernel (¿ 2.6.28), the block device subsystem in the kernelwas rewritten and the APIs were completely changed. Unfortunately, none of the onlinedocumentation for writing a block device driver explained any of the new changes as theywere still based on the older kernels. As such, much time was spent on trying to figure outthe differences in the API and how they are used.

6. “ERROR:MapLib:824 - Tri-state buffers are not supported in Virtex5. Block nand 01 0/nand 01 0/n iomust be removed from the design.” This error drove us nuts for a good week, seemingly in-dicating that there is no way we could interface our FPGA with the NAND flash chips, asthe data bus are bi-directional. Google wasn’t too kind either, as most responses from peoplewere just as cryptic. Turns out that specifying the port as “inout” in the port list in themodule is not sufficient - in fact, in addition to the original inout port, there must also bea corresponding in, out, and direction port(s) of the same width. Only by editing the MPDfile of the peripheral can you specify that in, our and direction ports actually drive an inoutport, and tell XST to use a tri-state buffer.

7. Many other issues too numerous to remember - however, one thing is for sure - with Xilinx,something that is unexpected will happen, always.

15 Words of Wisdom

1. While ChipScope may seem utterly terrible to use initially, it is an excellent tool for debugging.Learn it very early in the semester. Learn to use the triggers judiciously.

2. Xilinx’s example code often isn’t written in the best way (especially if it’s a Verilog example).If you think there’s a better way, there probably is.

3. Know that Xilinx’s code and instructions often cannot be taken for granted. It is highly likelythat you will encounter bugs.

4. Verilog and VHDL are treated very differently by Xilinx, even though they’re both popularhardware description languages - something that works on VHDL may not be supported inVerilog, or vice versa.

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5. You can never delay something by one day from your schedule and think you can make upfor it later.

6. When the going gets tough, it might be a good idea to consider pushing your fellow teammatesalong.

7. One can very readily get burnt out - so keep a look out for it coming!

8. Do not change the (SO)DIMM on the FPGA - doing so may cause the memory controller,and thus the entire project, to fail.

9. If you are intending to use the DDR2 SDRAM, make sure you are not overwriting mem-ory containing your program. The default address to store a program when initializing theMicroblaze can be set under the Application’s settings.

16 Future Work

There are plans to carry on this project as a part of a research project under Professor Ken Mai.The main issues to work out is to firstly verify that the CPLD is working as we expect it to, andsecondly, to find out why the NAND flash chips are not responding to the commands and signalssent to it. After basic functionality is achieved, the remaining components, like the ECC and AESmodules should be put into place.

The current implementation of the FTL is also somewhat inefficient and not highly robust. Fixesfor these shortcomings would be necessary for the drive to be a long lasting device. Caching bythe FTL has not been done, and could provide a speed-up. As always, new algorithms for wearleveling and erase management are welcome updates.

The block device driver could be updated to not use the request and elevator systems, thus makingit more flexible across kernel versions, as well as removing unhelpful overheads.

17 Individual Contributions

17.1 Winston Wan

During the first weeks of the project, I primarily focused on learning about the SATA protocol andthe requirements to making a SATA compliant drive. In the meanwhile, I tried to organize the toplevel design of the project and create a wiki for our own note-taking purposes. We worked closelywith the other group and Professor Mai to determine that SATA was going to be too major of anundertaking, and decided on using the PCIe port. In the following weeks, I worked on familiarizingmyself with Eric Chung’s existing codebase, and running his basic tests on his machine with muchhelp from Tim and Will. Also during this time, I tried to solidify all the interfaces between eachof the subsystems. The majority of the semester was spent trying to adapt Eric’s user space codeinto the kernel, as well as adapting the generic block device driver into the system. Due to majormisunderstandings of the capabilities of the loadable kernel modules and trouble with differentkernel versions on different computers of ours, this work took very long. In parallel, I begandeveloping a simple FTL in user space. This rudimentary FTL was very easily inserted for use onthe Microblaze. After completing the block driver and PCI driver as kernel modules with Tim’shelp, I spent some time aiding the other group with similar struggles that plagued us earlier as

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they attempted to build their MTD module. In the last week of class, I prepared the demo codeand the demo poster to allow Tim and Tao to focus on the NAND controller issues. I think eachmember of our group did a great job of balancing out the amount of work and helping each otherwhen needed. Tim was especially helpful in all parts of the project.

17.2 Tao Yang

During the first two months, I helped Will and Tim designed the DIMM (3 weeks). We createdthe initial schematics (in excel) using the flash chip and CPLD we picked. We also finished thelabs (2 weeks), collectively came up with the overall architecture, refined our design, and madevarious design decisions such as PCI Express/Serial ATA, FX boards/LX boards etc (a month).Around mid to late October, I started working on the NAND controller (joined by Myyk 2 weekslater). To verify my understanding of the bus protocols, I first modeled and tested the controllerthrough unsynthesizable verilog, and later converted it into a FSM design. After the FSM was fullyimplemented and simulated against the test bench I wrote, we ran into some synthesizability issues,which set us back for about a week. However, even though we finished testing our module aroundmid November, we could not test it against real chip since we need to interface it through microblaze. Though we decided the protocols a while ago, implementing and testing the FSL interfacemodule (by Tim) turned out to be a much more difficult job then we envisioned. While helpingTim writing and debugging the interface logic, I also implemented and tested the ECC module(though it was never integrated into the system due to lack of time). Around thanksgiving, we(we and Tim) finally finished our initial implementation of the FSL interface module and startedtesting our controller against the real chip (note the DIMM arrived the day before Thanksgiving,surface mount sockets and spare flash chips a few days before that). We spent the rest of the timedebugging and eventually got some response and the NAND chip (the reset commands works, atleast we think).

17.3 Timothy Tan

The initial few weeks of the project was spent trying to study various interface options for the vari-ous chips we needed connected to the FPGA (didn’t want to settle for the SODIMM slot initially),and to figure out what devices and chips we needed, and the differences between all of them. I alsojumped into picking up the SATA specification and protocols, to get an understand of the typeof FSM we would need to write - it being my second task at that stage of the project. At thesame time, one of the immediate issues faced was that in order to use the Virtex-5 LX110T boardsprovided by Professor Ken Mai, the Xilinx software had to be reinstalled, and licenses located forversion 11.

Unfortunately, just as I had created a SATA RocketIO core and convinced myself that writingthe SATA controller FSM was doable, I received a dose of reality, that it was very unlikely thatthe SATA controller could be completed without the use of more sophisticated analysis tools. PCIExpress had much greater odds of success, and so it was - dropping everything SATA and pickingup books on kernel device drivers. The next stage of the SODIMM design was to create a schematicthat contained our design, which could be sent out for a company to do the layout and fabrication.Unfortunately we ran into major issues with the design tools available in the school and wasted agreat deal of time working things out with the department IT admins. While the schematic, layoutand fabrication work was eventually outsourced to Cirexx to do, it still involved many rounds ofchecking and rechecking by Will, Tao and I to make sure we did not misread any datasheets or

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leave out a crucial wire between components. And it was a good thing we labored on, as we soondiscovered several problems which required some rethinking.

Besides working with Winston on the kernel drivers, I worked on characterizing the speeds ofthe various buses and interfaces available on the FPGA - turns out that the FSL was the fastest,and as such was selected to interface our MicroBlaze and the NAND controller. I initially startedwith Xilinx’s example code with an implicit FSM for FSL data transfer, and wrote a transfer testbetween the Microblaze and a 4KB buffer - it worked beautifully, and we called it the “interfaceFSM”. Not giving it too much though I worked on extending the “interface FSM” to communicatewith the NAND controller. Unfortunately, that is where things went wrong. With the larger “inter-face FSM”, XST became confused and took 12 hours to synthesize the design! There was no choicebut to immediately rewrite the “interface FSM” explicitly. This cost a few days, but thankfully,with Tao’s help, the Modelsim simulations eventually gave a green light again. Unfortunately agreen light in simulation translated to no-go in hardware when we used both the surface mountand the actual SODIMM. Tao and I spent the entire Thanksgiving and most of the days before thepublic demo trying to follow every clue, trying every method of debugging and correcting potentialproblems before the chip started showing signs of life.

This course has been one of the most memorable one of all in CMU, and I believe that noneof us in the group have ever spent so much time working so intently on a project. It was a thrilland I certainly learnt a lot from the experience.

18 Class Impressions/Improvements

We thought this class was a unique experience to do a highly independent research and designproject at the undergraduate level. Being immersed in the project and being able to strugglewith problems was educational, but some more guidance would probably have resulted in a moresuccessful final demonstration. The tools were difficult to use and the labs were too guided andtoo short to provide appropriate preparation for the course project. We believe the chance to doa different project like the Solid State Drive instead of the prescribed video game platform was agreat opportunity, and we hope that there will be more of these alternative project options in thefuture.

19 References

• Chung, Eric “PCI Express Notes” ProtoFlex Project 2009. Retrieved: Oct 1, 2009.〈 http://www.ece.cmu.edu/ protoflex/doku.php?id=internal:pci express:pci express notes 〉

• Chung, Eric “ProtoFlex User Guide” ProtoFlex Project 2009. Retrieved: Oct 1, 2009.〈 http://www.ece.cmu.edu/ protoflex/doku.php?id=documentation:userguide 〉

• Corbet, Jonathan, Rubini, Alessandro and Kroah-Hartman, Greg Linux Device Drivers CA:O.Reilly Media, Inc. 2005.

• Gal, Eran “Algorithms and Data Structures for Flash Memories” 2004. Retrieved: Sep 15,2009.〈 http://www.tau.ac.il/ stoledo/Pubs/flash-survey.pdf 〉

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• Micron Technology, Inc. “256Mb: x4, x8, x16 DDR2 SDRAM” Product Specification 2009.Retrieved: Sep 29, 2009.〈 http://download.micron.com/pdf/datasheets/dram/ddr2/256MbDDR2.pdf 〉

• Micron Technology, Inc. “8, 16, 32, 64Gb NAND Flash Memory” 2008. Retrieved: Sep 3,2009.〈 URL not available publicly 〉

• Micron Technology, Inc. “ECC Module for Xilinx Spartan-3” Technical Note TN-29-05 2007.Retrieved: Oct 2, 2009.〈 http://download.micron.com/pdf/technotes/nand/tn2905.pdf 〉

• Micron Technology, Inc. “Hamming Codes for NAND Flash Memory Devices” Technical Note TN-29-082007. Retrieved: Sep 15, 2009〈 http://download.micron.com/pdf/technotes/nand/tn2908.pdf 〉

• Micron Technology, Inc. “Increasing NAND Flash Performance” Technical Note TN-29-142007. Retrieved: Oct 31, 2009.〈 http://download.micron.com/pdf/technotes/nand/tn2914.pdf 〉

• Micron Technology, Inc. “ML505/6/7 Block Diagram” ML505/6/7 Virtex-5 Evaluation Platform2008. Retrieved: Sep 2, 2009.〈 http://www.xilinx.com/support/documentation/boards and kits/ml50x schematics.pdf 〉

• Micron Technology, Inc. “NAND Flash 101” Technical Note TN-29-19 2006. Retrieved: Oct1, 2009.〈 http://download.micron.com/pdf/technotes/nand/tn2919.pdf 〉

• Micron Technology, Inc. “Wear-Leveling Techniques in NAND Flash Devices” Technical Note TN-29-422008. Retrieved Sep 15, 2009.〈 http://download.micron.com/pdf/technotes/nand/tn2942 nand wear leveling.pdf 〉

• Ng, Mark. “Supporting Multiple SD Devices with CPLDs” Xcell Journal First Quarter 2008.37-39.

• Numonyx, B.V. “Error correction code in single level cell NAND flash memories” Application Note AN18232008. Retrieved: Nov 18, 2009.〈 http://www.numonyx.com/Documents/Application

• Petazzoni, Thomas. “Block Device Drivers” Free Electrons, Embedded Linux Developers2009. Retrieved: Nov 25, 2009.〈 http://free-electrons.com/doc/block drivers.pdf 〉

• Qimonda AG. “Design Guide for DDR2 Memory Products” Application Note AN CD0352008. Retrieved: Sep 30, 2009.〈 http://www.qimonda.com/static/download/promopages/AN CD036 Design Guide for DDR2 rev100 x2x.pdf〉

• Rajimwale, Abhishek. “Block Management in Solid-State Devices” USENIX ’09 2009. Re-trieved: Nov 26, 2009.〈 http://www.usenix.org/events/usenix09/tech/full papers/rajimwale/rajimwale.pdf 〉

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• Xilinx, Inc. “Bus Master DMA Performance Demonstration Reference Design for the XilinxEndpoint PCI Express Solutions” Application Note XAPP1052 2009. Retrieved: Nov 15,2009.〈 http://www.xilinx.com/support/documentation/application notes/xapp1052.pdf 〉

• Xilinx, Inc. “Connecting Customized IP to the MicroBlaze Soft Processor Using the FastSimplex Link (FSL) Channel” Application Note XAPP529 2004. Retrieved: Oct 7, 2009.〈 http://www.xilinx.com/support/documentation/application notes/xapp529.pdf 〉

• Xilinx, Inc. “DDR2 Memory Controller for PowerPC 440 Processors” Product Specification DS5672009. Retrieved: Oct 18, 2009.〈 ftp://ftp.xilinx.com/pub/documentation/misc/ppc440mc ddr2.pdf 〉

• Xilinx, Inc. “High-Performance DDR2 SDRAM Interface in Virtex-5 Devices” Application Note XAPP8582008. Retrieved: Oct 2, 2009.〈 http://www.xilinx.com/support/documentation/application notes/xapp858.pdf 〉

• Xilinx, Inc. “Level Translation Using Xilinx CoolRunner-II CPLDs” Application Note XAPP7852005. Retrieved: Sep 18, 2009.〈 http://www.xilinx.com/support/documentation/application notes/xapp785.pdf 〉

• Xilinx, Inc. “Multi-Port Memory Controller (MPMC) (v4.02.a)” Product Specification DS6432008. Retrieved: Oct 7, 2009.〈 http://china.xilinx.com/support/documentation/ip documentation/mpmc.pdf 〉

• Xilinx, Inc. “XC2C256 CoolRunner-II CPLD” Product Specification DS094 2007. Retrieved:Sep 28, 2009.〈 http://www.xilinx.com/support/documentation/data sheets/ds094.pdf 〉

• Xilinx, Inc. “Xilinx Synthesis Technology (XST) User Guide” Xilinx Development SystemRetrieved: Nov 29, 2009.〈 http://www.xilinx.com/itp/xilinx9/books/docs/xst/xst.pdf 〉

28

A Custom-fabricated SODIMM Design Details

A.1 Original DesignN

AN

D+

DD

R D

IMM

sch

Not

esPi

nk (

spec

ial)

line

s ne

ed e

xtra

rou

ting

care

(m

ore

deta

il la

ter)

Key

Plea

se le

ave

test

pad

s fo

r al

l Pow

er n

ets

pow

ergn

dSid

e of

DIM

M w

ith P

in2

has

heig

ht r

estr

ictio

nsou

tin

For

the

bypa

ss c

aps,

fee

l fre

e to

use

a d

iffer

ent

part

if it

fits

the

req

uire

men

ts b

elow

bidi

rect

iona

lSpe

cial

MT2

9F16

G08

DAAW

P-ET

:A T

RM

icro

n M

T29

Chi

p1N

etXili

nx X

C2C

256

CPL

DFP

GA D

IMM

soc

ket

1N

C-

NAN

D1_

CLE

_1V8

4D

Q4

DQ

3212

3N

AN

D3_

CLE

_1V8

2N

C-

NAN

D1_

ALE

_1V8

5D

Q0

DQ

3612

4N

AN

D3_

ALE

_1V8

3N

C-

NAN

D1_

WE#

_1V8

6D

Q5

DQ

3312

5N

AN

D3_

WE#

_1V8

4N

C-

FT25

6M

CFB

FBM

CFT

256

NAN

D1_

WP#

_1V8

7D

Q1

DQ

3712

6N

AN

D3_

WP#

_1V8

5N

C-

6R/B

2#N

AN

D1_

RB2#

_3V3

B3

11

51

R1

NAN

D1_

RB2#

_1V8

NAN

D1_

RE#

_1V8

10D

M0

DM

413

0N

AN

D4_

CLE

_1V8

7R/B

#N

AN

D1_

RB#

_3V3

B4

21

52

N4

NAN

D1_

RB#

_1V8

NAN

D1_

CE#

_1V8

11D

QS0_

ND

QS4_

N12

9N

AN

D4_

ALE

_1V8

8RE#

NAN

D1_

RE#

_3V3

C4

31(

GSR)

53

N2

NAN

D1_

RE#

_1V8

NAN

D1_

CE2

#_1

V8

13D

QS0_

PD

QS4_

P13

1N

AN

D4_

WE#

_1V8

9CE#

NAN

D1_

CE#

_3V3

A2

41

(GCK1)

54

M3

NAN

D1_

CE#

_1V8

10CE2

#N

AN

D1_

CE2

#_3

V3

A3

51

55

P1N

AN

D1_

CE2

#_1

V8

NAN

D1_

IO0_

1V8

14D

Q6

DQ

3813

4N

AN

D3_

IO0_

1V8

11N

C-

NAN

D1_

IO1_

1V8

16D

Q7

DQ

3413

5N

AN

D3_

IO1_

1V8

12Vcc

VCC_3

V3

A4

61

(GCK0)

56

M2

NAN

D1_

CLE

_1V8

NAN

D1_

IO2_

1V8

17D

Q2

DQ

3913

6N

AN

D3_

IO2_

1V8

13Vss

Gnd

B5

121

512

L3N

AN

D1_

ALE

_1V8

NAN

D1_

IO3_

1V8

19D

Q3

DQ

3513

7N

AN

D3_

IO3_

1V8

14N

C-

A5

131

513

N1

NAN

D1_

WE#

_1V8

15N

C-

E814

15

14L4

NAN

D1_

WP#

_1V8

NAN

D1_

IO4_

1V8

20D

Q12

DQ

4414

0N

AN

D3_

IO4_

1V8

16CLE

NAN

D1_

CLE

_3V3

NAN

D1_

IO5_

1V8

22D

Q13

DQ

4014

1N

AN

D3_

IO5_

1V8

17ALE

NAN

D1_

ALE

_3V3

B6

151

515

M1

NAN

D1_

IO0_

1V8

NAN

D1_

IO6_

1V8

23D

Q8

DQ

4514

2N

AN

D3_

IO6_

1V8

18W

E#N

AN

D1_

WE#

_3V3

C7

161

516

L5N

AN

D1_

IO1_

1V8

NAN

D1_

IO7_

1V8

25D

Q9

DQ

4114

3N

AN

D3_

IO7_

1V8

19W

P#N

AN

D1_

WP#

_3V3

D3

12(

GTS

2)6

1N

3N

AN

D1_

IO2_

1V8

20N

C-

C3

22

(CD

RST)

62

P2N

AN

D1_

IO3_

1V8

NAN

D2_

RE#

_1V8

26D

M1

DM

514

7N

AN

D4_

WP#

_1V8

21N

C-

NAN

D2_

CE#

_1V8

29D

QS1_

ND

QS5_

N14

6N

AN

D4_

IO0_

1V8

22N

C-

E33

2(G

TS3)

63

P4N

AN

D1_

IO4_

1V8

NAN

D2_

CE2

#_1

V8

31D

QS1_

PD

QS5_

P14

8N

AN

D4_

IO1_

1V8

23N

C-

B2

42

(GCK2)

64

P5N

AN

D1_

IO5_

1V8

24N

C-

D4

52(

GTS

0)6

5R2

NAN

D1_

IO6_

1V8

NAN

D1_

RB2#

_1V8

35D

Q10

DQ

4215

1N

AN

D4_

IO2_

1V8

25D

NU

-D

26

26

6T1

NAN

D1_

IO7_

1V8

NAN

D1_

RB#

_1V8

36D

Q14

DQ

4615

2N

AN

D4_

IO3_

1V8

26D

NU

-N

AN

D2_

RB2#

_1V8

37D

Q11

DQ

4315

3N

AN

D4_

IO4_

1V8

27N

C-

NAN

D2_

RB#

_1V8

38D

Q15

DQ

4715

4N

AN

D4_

IO5_

1V8

28N

C-

E512

2(G

TS1)

(DG

E)6

12T2

NAN

D2_

RB2#

_1V8

29I/

O 0

NAN

D1_

IO0_

3V3

B1

132

613

N5

NAN

D2_

RB#

_1V8

NAN

D2_

CLE

_1V8

43D

Q16

DQ

4815

7N

AN

D4_

IO6_

1V8

30I/

O 1

NAN

D1_

IO1_

3V3

E414

26

14R4

NAN

D2_

RE#

_1V8

NAN

D2_

ALE

_1V8

44D

Q20

DQ

5215

8N

AN

D4_

IO7_

1V8

31I/

O 2

NAN

D1_

IO2_

3V3

C1

152

615

M5

NAN

D2_

CE#

_1V8

NAN

D2_

WE#

_1V8

45D

Q17

DQ

4915

9N

AN

D1_

DIR

32I/

O 3

NAN

D1_

IO3_

3V3

E216

26

16R5

NAN

D2_

CE2

#_1

V8

NAN

D2_

WP#

_1V8

46D

Q21

DQ

5316

0N

AN

D2_

DIR

33N

C-

34N

C-

A6

13

71

K4

NAN

D2_

CLE

_1V8

NAN

D3_

RE#

_1V8

49D

QS2_

ND

QS6_

N16

7SD

RAM

_DQ

S#

35N

C-

D7

23

72

L2N

AN

D2_

ALE

_1V8

NAN

D3_

CE#

_1V8

51D

QS2_

PD

QS6_

P16

9SD

RAM

_DQ

S36

Vss

Gnd

NAN

D1_

RB2#

_3V3

B7

33

73

K3

NAN

D2_

WE#

_1V8

NAN

D3_

CE2

#_1

V8

52D

M2

DM

617

0N

AN

D3_

DIR

37Vcc

VCC_3

V3

NAN

D1_

RB#

_3V3

E94

37

4L1

NAN

D2_

WP#

_1V8

38D

NU

or

Vss

-N

AN

D2_

IO0_

1V8

55D

Q18

DQ

5017

3SD

RAM

_DQ

039

NC

-N

AN

D1_

RE#

_3V3

A7

53

75

K5

NAN

D2_

IO0_

1V8

NAN

D2_

IO1_

1V8

56D

Q22

DQ

5417

4SD

RAM

_DQ

140

NC

-N

AN

D1_

CE#

_3V3

D8

63

76

K2

NAN

D2_

IO1_

1V8

NAN

D2_

IO2_

1V8

57D

Q19

DQ

5117

5SD

RAM

_DQ

241

I/0

4N

AN

D1_

IO4_

3V3

NAN

D1_

CE2

#_3

V3

B8

123

711

J4N

AN

D2_

IO2_

1V8

NAN

D2_

IO3_

1V8

58D

Q23

DQ

5517

6SD

RAM

_DQ

342

I/0

5N

AN

D1_

IO5_

3V3

NAN

D1_

CLE

_3V3

C8

133

712

K1

NAN

D2_

IO3_

1V8

43I/

0 6

NAN

D1_

IO6_

3V3

NAN

D2_

IO4_

1V8

61D

Q24

DQ

5617

9SD

RAM

_DQ

444

I/0

7N

AN

D1_

IO7_

3V3

NAN

D1_

ALE

_3V3

A8

143

713

J3N

AN

D2_

IO4_

1V8

NAN

D2_

IO5_

1V8

62D

Q28

DQ

6018

0SD

RAM

_DQ

545

NC

-N

AN

D1_

WE#

_3V3

E11

153

714

J2N

AN

D2_

IO5_

1V8

NAN

D2_

IO6_

1V8

63D

Q25

DQ

5718

1SD

RAM

_DQ

646

NC

-N

AN

D1_

WP#

_3V3

E10

163

715

J5N

AN

D2_

IO6_

1V8

NAN

D2_

IO7_

1V8

64D

Q29

DQ

6118

2SD

RAM

_DQ

747

NC

-N

AN

D2_

RB2#

_3V3

F21

47

16J1

NAN

D2_

IO7_

1V8

48D

NU

-N

AN

D4_

RE#

_1V8

67D

M3

DM

718

5N

AN

D4_

DIR

NAN

D4_

CE#

_1V8

68D

QS3_

ND

QS7_

N18

6SD

RAM

_RD

QS#

NAN

D2_

RB#

_3V3

F32

48

1R6

NAN

D3_

RB2#

_1V8

NAN

D4_

CE2

#_1

V8

70D

QS3_

PD

QS7_

P18

8SD

RAM

_DM

_RD

QS

Mic

ron

MT2

9 Chi

p2N

AN

D2_

RE#

_3V3

G4

34

82

N6

NAN

D3_

RB#

_1V8

1N

C-

NAN

D2_

CE#

_3V3

G3

44

83

R3

NAN

D3_

RE#

_1V8

NAN

D3_

RB2#

_1V8

73D

Q26

DQ

5818

9N

AN

D1_

DIR

2N

C-

NAN

D2_

CE2

#_3

V3

F55

48

4M

6N

AN

D3_

CE#

_1V8

NAN

D3_

RB#

_1V8

74D

Q30

DQ

5919

1N

AN

D2_

DIR

3N

C-

NAN

D2_

CLE

_3V3

G5

64

85

T3N

AN

D3_

CE2

#_1

V8

NAN

D4_

RB2#

_1V8

75D

Q27

DQ

6219

2N

AN

D3_

DIR

4N

C-

NAN

D4_

RB#

_1V8

76D

Q31

DQ

6319

4N

AN

D4_

DIR

5N

C-

NAN

D2_

ALE

_3V3

H2

124

86

P6N

AN

D3_

CLE

_1V8

6R/B

2#N

AN

D2_

RB2#

_3V3

NAN

D2_

WE#

_3V3

H4

134

811

T4N

AN

D3_

ALE

_1V8

Gnd

3VSS1

7R/B

#N

AN

D2_

RB#

_3V3

NAN

D2_

WP#

_3V3

H3

144

812

P7N

AN

D3_

WE#

_1V8

Gnd

9VSS2

VREF

1SD

RAM

_VREF

8RE#

NAN

D2_

RE#

_3V3

NAN

D3_

RB2#

_3V3

H1

154

813

T5N

AN

D3_

WP#

_1V8

Gnd

15VSS3

VD

DSPD

199

9CE#

NAN

D2_

CE#

_3V3

Gnd

21VSS4

10CE2

#N

AN

D2_

CE2

#_3

V3

NAN

D3_

RB#

_3V3

H5

164

814

N7

NAN

D3_

IO0_

1V8

Gnd

27VSS5

VD

D1

103

SD

RAM

_VD

D_1

V8

11N

C-

NAN

D3_

RE#

_3V3

B13

19

815

R7

NAN

D3_

IO1_

1V8

Gnd

33VSS6

VD

D2

111

SD

RAM

_VD

D_1

V8

12Vcc

VCC_3

V3

NAN

D3_

CE#

_3V3

B14

29

816

M7

NAN

D3_

IO2_

1V8

Gnd

39VSS7

VD

D3

117

SD

RAM

_VD

D_1

V8

13Vss

Gnd

NAN

D3_

CE2

#_3

V3

C13

39

131

R15

NAN

D3_

IO3_

1V8

Gnd

41VSS8

VD

D4

81SD

RAM

_VD

D_1

V8

14N

C-

Gnd

47VSS9

VD

D5

87SD

RAM

_VD

D_1

V8

15N

C-

NAN

D3_

CLE

_3V3

A15

49

132

T16

NAN

D3_

IO4_

1V8

Gnd

121

VSS10

VD

D6

95SD

RAM

_VD

D_1

V8

16CLE

NAN

D2_

CLE

_3V3

NAN

D3_

ALE

_3V3

C12

59

133

N14

NAN

D3_

IO5_

1V8

Gnd

127

VSS11

VD

D7

104

SD

RAM

_VD

D_1

V8

17ALE

NAN

D2_

ALE

_3V3

NAN

D3_

WE#

_3V3

B12

69

134

R16

NAN

D3_

IO6_

1V8

Gnd

133

VSS12

VD

D8

112

SD

RAM

_VD

D_1

V8

18W

E#N

AN

D2_

WE#

_3V3

NAN

D3_

WP#

_3V3

D13

119

135

N15

NAN

D3_

IO7_

1V8

Gnd

139

VSS13

VD

D9

118

SD

RAM

_VD

D_1

V8

19W

P#N

AN

D2_

WP#

_3V3

Gnd

145

VSS14

VD

D10

82SD

RAM

_VD

D_1

V8

20N

C-

Gnd

149

VSS15

VD

D11

88SD

RAM

_VD

D_1

V8

21N

C-

NAN

D4_

RB2#

_3V3

A14

129

136

M15

NAN

D4_

RB2#

_1V8

Gnd

53VSS16

VD

D12

96SD

RAM

_VD

D_1

V8

22N

C-

NAN

D4_

RB#

_3V3

E13

139

1312

M13

NAN

D4_

RB#

_1V8

Gnd

59VSS17

23N

C-

NAN

D4_

RE#

_3V3

A13

149

1313

P16

NAN

D4_

RE#

_1V8

Gnd

65VSS18

24N

C-

NAN

D4_

CE#

_3V3

C11

159

1314

N16

NAN

D4_

CE#

_1V8

Gnd

71VSS19

25D

NU

-N

AN

D4_

CE2

#_3

V3

A12

169

1315

L14

NAN

D4_

CE2

#_1

V8

Gnd

77VSS20

CK0_

P30

SD

RAM

_CK

C66

I/O

BAN

K 2

I/O

BAN

K 1

29

26D

NU

-G

nd15

5VSS21

CK0_

N32

SD

RAM

_CK#

C66

27N

C-

NAN

D4_

CLE

_3V3

A16

110

1316

M14

NAN

D4_

CLE

_1V8

Gnd

161

VSS22

28N

C-

NAN

D4_

ALE

_3V3

B15

210

141

P15

NAN

D4_

ALE

_1V8

Gnd

165

VSS23

CK1_

P16

4CPL

D_R

ESV_2

C67

29I/

O 0

NAN

D2_

IO0_

3V3

NAN

D4_

WE#

_3V3

C14

310

142

P14

NAN

D4_

WE#

_1V8

Gnd

171

VSS24

CK1_

N16

6CPL

D_R

ESV_3

C67

30I/

O 1

NAN

D2_

IO1_

3V3

NAN

D4_

WP#

_3V3

G11

410

143

P13

NAN

D4_

WP#

_1V8

Gnd

177

VSS25

31I/

O 2

NAN

D2_

IO2_

3V3

Gnd

183

VSS26

32I/

O 3

NAN

D2_

IO3_

3V3

NAN

D2_

IO0_

3V3

B16

510

144

R13

NAN

D4_

IO0_

1V8

Gnd

187

VSS27

CKE1

80CPL

D_R

ESV_4

Pull

Dow

n33

NC

-N

AN

D2_

IO1_

3V3

D15

610

145

N13

NAN

D4_

IO1_

1V8

Gnd

193

VSS28

CKE0

79SD

RAM

_CKE

Pull

Dow

n34

NC

-N

AN

D2_

IO2_

3V3

E14

1110

146

R14

NAN

D4_

IO2_

1V8

Gnd

2VSS29

35N

C-

NAN

D2_

IO3_

3V3

C16

1210

1412

T15

NAN

D4_

IO3_

1V8

Gnd

8VSS30

36Vss

Gnd

Gnd

12VSS31

A13

116

CPL

D_R

ESV_5

VTT

DD

R S

win

g37

Vcc

VCC_3

V3

NAN

D2_

IO4_

3V3

F14

1310

1413

R12

NAN

D4_

IO4_

1V8

Gnd

18VSS32

A12

89SD

RAM

_A12

VTT

DD

R S

win

g38

DN

U o

r Vss

-N

AN

D2_

IO5_

3V3

F13

1410

1414

N11

NAN

D4_

IO5_

1V8

Gnd

24VSS33

A11

90SD

RAM

_A11

VTT

DD

R S

win

g39

NC

-N

AN

D2_

IO6_

3V3

E15

1510

1415

M11

NAN

D4_

IO6_

1V8

Gnd

28VSS34

A9

91SD

RAM

_A9

VTT

DD

R S

win

g40

NC

-N

AN

D2_

IO7_

3V3

G13

1610

1416

N10

NAN

D4_

IO7_

1V8

Gnd

34VSS35

A8

93SD

RAM

_A8

VTT

DD

R S

win

g41

I/0

4N

AN

D2_

IO4_

3V3

Gnd

40VSS36

A7

92SD

RAM

_A7

VTT

DD

R S

win

g42

I/0

5N

AN

D2_

IO5_

3V3

NAN

D1_

IO0_

3V3

B11

111

151

L15

NAN

D1_

DIR

Gnd

42VSS37

A6

94SD

RAM

_A6

VTT

DD

R S

win

g43

I/0

6N

AN

D2_

IO6_

3V3

NAN

D1_

IO1_

3V3

D11

211

152

L13

NAN

D2_

DIR

Gnd

48VSS38

A5

97SD

RAM

_A5

VTT

DD

R S

win

g44

I/0

7N

AN

D2_

IO7_

3V3

NAN

D1_

IO2_

3V3

A11

311

153

M12

NAN

D3_

DIR

Gnd

122

VSS39

A4

98SD

RAM

_A4

VTT

DD

R S

win

g45

NC

-N

AN

D1_

IO3_

3V3

D10

411

154

M16

NAN

D4_

DIR

Gnd

128

VSS40

A3

99SD

RAM

_A3

VTT

DD

R S

win

g46

NC

-N

AN

D1_

IO4_

3V3

B10

511

155

K14

Gnd

132

VSS41

A2

100

SD

RAM

_A2

VTT

DD

R S

win

g47

NC

-N

AN

D1_

IO5_

3V3

E12

611

156

L16

Gnd

138

VSS42

A1

101

SD

RAM

_A1

VTT

DD

R S

win

g48

DN

U-

Gnd

144

VSS43

A0

102

SD

RAM

_A0

VTT

DD

R S

win

gN

AN

D1_

IO6_

3V3

F12

1111

1511

K15

CPL

D_R

ESV_1

Gnd

150

VSS44

A10

/AP

105

SD

RAM

_A10

VTT

DD

R S

win

gN

AN

D1_

IO7_

3V3

B9

1211

1512

L12

CPL

D_R

ESV_2

Gnd

54VSS45

Mic

ron

MT2

9 N

AN

D C

hip3

NAN

D3_

IO0_

3V3

C9

1311

1513

K16

CPL

D_R

ESV_3

Gnd

60VSS46

1N

C-

NAN

D3_

IO1_

3V3

C10

1411

1514

J14

CPL

D_R

ESV_4

Gnd

66VSS47

BA2

85CPL

D_R

ESV_6

VTT

DD

R S

win

g2

NC

-N

AN

D3_

IO2_

3V3

A9

1511

1515

J15

CPL

D_R

ESV_5

Gnd

72VSS48

BA1

106

SD

RAM

_BA1

VTT

DD

R S

win

g3

NC

-N

AN

D3_

IO3_

3V3

D9

1611

1516

J13

CPL

D_R

ESV_6

Gnd

78VSS49

BA0

107

SD

RAM

_BA0

VTT

DD

R S

win

g4

NC

-G

nd15

6VSS50

RAS_B

108

SD

RAM

_RAS#

VTT

DD

R S

win

g5

NC

-N

AN

D3_

IO4_

3V3

F15

112

161

P10

CPL

D_R

ESV_7

Gnd

162

VSS51

WE_

B10

9SD

RAM

_WE#

VTT

DD

R S

win

g6

R/B

2#N

AN

D3_

RB2#

_3V3

NAN

D3_

IO5_

3V3

G14

212

162

R10

CPL

D_R

ESV_8

Gnd

168

VSS52

CAS_B

113

SD

RAM

_CAS#

VTT

DD

R S

win

g7

R/B

#N

AN

D3_

RB#

_3V3

NAN

D3_

IO6_

3V3

E16

312

163

T10

CPL

D_R

ESV_9

Gnd

172

VSS53

8RE#

NAN

D3_

RE#

_3V3

NAN

D3_

IO7_

3V3

H12

412

164

R9

CPL

D_R

ESV_1

0G

nd17

8VSS54

S0_

B11

0SD

RAM

_CS#

VTT

DD

R S

win

g9

CE#

NAN

D3_

CE#

_3V3

NAN

D4_

IO0_

3V3

F16

512

165

N9

CPL

D_R

ESV_1

1G

nd18

4VSS55

S1_

B11

5CPL

D_R

ESV_7

VTT

DD

R S

win

g10

CE2

#N

AN

D3_

CE2

#_3

V3

NAN

D4_

IO1_

3V3

H16

612

166

M8

Gnd

190

VSS56

11N

C-

Gnd

196

VSS57

OD

T011

4SD

RAM

_OD

TPu

ll D

own

12Vcc

VCC_3

V3

NAN

D4_

IO2_

3V3

G15

1112

1611

T8O

DT1

119

CPL

D_R

ESV_8

Pull

Dow

n13

Vss

Gnd

NAN

D4_

IO3_

3V3

H13

1212

1612

P8N

C69

NC8

14N

C-

NAN

D4_

IO4_

3V3

G16

1312

1613

R8

NC

83N

C3

15N

C-

NAN

D4_

IO5_

3V3

H14

1412

1614

T7N

C16

3N

C7

SD

A19

5CPL

D_R

ESV_9

Pull

Up

16CLE

NAN

D3_

CLE

_3V3

NAN

D4_

IO6_

3V3

H15

1512

1615

N8

NC

50N

C6

SCL

197

CPL

D_R

ESV_1

Pull

Up

17ALE

NAN

D3_

ALE

_3V3

NAN

D4_

IO7_

3V3

J12

1612

1616

T6N

C12

0N

C4

SA0

198

Gnd

18W

E#N

AN

D3_

WE#

_3V3

NC

84N

C2

SA1

200

Gnd

19W

P#N

AN

D3_

WP#

_3V3

CPL

D_J

TAG

_TCK

P12

TCK

VCCIO

1J6

SD

RAM

_VD

D_1

V8

NC

86N

C1

20N

C-

CPL

D_J

TAG

_TD

IR11

TDI

VCCIO

1K6

SD

RAM

_VD

D_1

V8

"P2"

21N

C-

CPL

D_J

TAG

_TD

OA10

TDO

VCCIO

1L7

SD

RAM

_VD

D_1

V8

22N

C-

CPL

D_J

TAG

_TM

SN

12TM

SVCCIO

1L8

SD

RAM

_VD

D_1

V8

Not

e--

the

DIM

M s

lot

is b

eing

rep

urpo

sed

so t

he s

igna

l nam

es c

an b

e co

nfus

ing.

Be

care

ful!

23N

C-

CPL

D_J

TAG

_VCC

F4VCCAU

X(J

TAG

)VCCIO

1J1

1SD

RAM

_VD

D_1

V8

24N

C-

VCCIO

1K11

SD

RAM

_VD

D_1

V8

25D

NU

-CPL

D_V

CC_1

V8

P3VCC

VCCIO

1L1

0SD

RAM

_VD

D_1

V8

26D

NU

-CPL

D_V

CC_1

V8

K13

VCC

VCCIO

1L9

SD

RAM

_VD

D_1

V8

SD

RAM

127

NC

-CPL

D_V

CC_1

V8

D12

VCC

Mic

ron

60 F

BG

A x

4 M

T47H

64M

8 D

DR

28N

C-

CPL

D_V

CC_1

V8

D5

VCC

GN

DF1

1G

ndA1

VD

DSD

RAM

_VD

D_1

V8

29I/

O 0

NAN

D3_

IO0_

3V3

GN

DF6

Gnd

A2Q

S#

/NF

SD

RAM

_RD

QS#

30I/

O 1

NAN

D3_

IO1_

3V3

VCC_3

V3

F7VCCIO

2G

ND

G10

Gnd

A3

VSS

Gnd

31I/

O 2

NAN

D3_

IO2_

3V3

VCC_3

V3

F8VCCIO

2G

ND

G7

Gnd

A7

VSSQ

Gnd

32I/

O 3

NAN

D3_

IO3_

3V3

VCC_3

V3

G6

VCCIO

2G

ND

G8

Gnd

A8

DQ

S#

SD

RAM

_DQ

S#

33N

C-

VCC_3

V3

H6

VCCIO

2G

ND

G9

Gnd

A9

VD

DQ

SD

RAM

_VD

DQ

_1VD

Q p

ower

sup

ply:

1.8

V ±

0.1V

. Is

olat

ed o

34N

C-

VCC_3

V3

F10

VCCIO

2G

ND

H10

Gnd

35N

C-

VCC_3

V3

F9VCCIO

2G

ND

H7

Gnd

B1

DQ

6SD

RAM

_DQ

636

Vss

Gnd

VCC_3

V3

H11

VCCIO

2G

ND

H8

Gnd

B2

VSSQ

Gnd

37Vcc

VCC_3

V3

GN

DH

9G

ndB3

/RD

QS

SD

RAM

_DM

_RD

QS

38D

NU

or

Vss

-G

ND

J10

Gnd

B7

DQ

SSD

RAM

_DQ

S39

NC

--

A1

NC

GN

DJ7

Gnd

B8

VSSQ

Gnd

40N

C-

-C2

NC

GN

DJ8

Gnd

B9

DQ

7SD

RAM

_DQ

741

I/0

4N

AN

D3_

IO4_

3V3

-E6

NC

GN

DJ9

Gnd

42I/

0 5

NAN

D3_

IO5_

3V3

-D

1N

CG

ND

K10

Gnd

C1

VD

DQ

SD

RAM

_VD

DQ

_1V8

43I/

0 6

NAN

D3_

IO6_

3V3

-E1

NC

GN

DK7

Gnd

C2

DQ

1SD

RAM

_DQ

144

I/0

7N

AN

D3_

IO7_

3V3

-G

2N

CG

ND

K8

Gnd

C3

VD

DQ

SD

RAM

_VD

DQ

_1V8

45N

C-

-F1

NC

GN

DK9

Gnd

C7

VD

DQ

SD

RAM

_VD

DQ

_1V8

46N

C-

-G

1N

CG

ND

L11

Gnd

C8

DQ

0SD

RAM

_DQ

047

NC

--

M4

NC

GN

DL6

Gnd

C9

VD

DQ

SD

RAM

_VD

DQ

_1V8

48D

NU

--

T9N

C-

P9N

CD

1D

Q4

SD

RAM

_DQ

4-

M9

NC

NC

D16

-D

2VSSQ

Gnd

Mic

ron

MT2

9 Chi

p 4

-M

10N

CN

CG

12-

D3

DQ

3SD

RAM

_DQ

31

NC

--

T11

NC

NC

C15

-D

7D

Q2

SD

RAM

_DQ

22

NC

--

T12

NC

NC

D14

-D

8VSSQ

Gnd

3N

C-

-T1

3N

CN

CD

6-

D9

DQ

5SD

RAM

_DQ

54

NC

--

P11

NC

NC

C6

-5

NC

--

T14

NC

NC

E7-

E1VD

DL

SD

RAM

_VD

D_1

V8D

LL p

ower

sup

ply:

1.8

V ±

0.1V

.6

R/B

2#N

AN

D4_

RB2#

_3V3

-J1

6N

CN

CC5

-E2

VREF

SD

RAM

_VREF

7R/B

#N

AN

D4_

RB#

_3V3

K12

NC

E3VSS

Gnd

8RE#

NAN

D4_

RE#

_3V3

E7VSSD

LG

nd9

CE#

NAN

D4_

CE#

_3V3

Not

es:

E8CK

SD

RAM

_CK

10CE2

#N

AN

D4_

CE2

#_3

V3

1G

TS =

glo

bal o

utpu

t en

able

, G

SR =

glo

bal r

eset

/set

, G

CK =

glo

bal c

lock

, CD

RST

= c

lock

div

ide

rese

t, D

GE

= D

ataG

ATE

ena

ble.

E9VD

DSD

RAM

_VD

D_1

V8

11N

C-

2G

TS,

GSR a

nd G

CK p

ins

can

be u

sed

for

gene

ral p

urpo

se I

/O.

12Vcc

VCC_3

V3

13Vss

Gnd

F2CKE

SD

RAM

_CKE

14N

C-

F3W

E#SD

RAM

_WE#

15N

C-

F7RAS#

SD

RAM

_RAS#

16CLE

NAN

D4_

CLE

_3V3

F8CK#

SD

RAM

_CK#

17ALE

NAN

D4_

ALE

_3V3

JTAG

Hea

derD

igik

ey:

S60

09-0

7-N

DF9

OD

TSD

RAM

_OD

T

30

18W

E#N

AN

D4_

WE#

_3V3

Gnd

12

CPL

D_J

TAG

_VCC

19W

P#N

AN

D4_

WP#

_3V3

Gnd

34

CPL

D_J

TAG

_TM

SG

1RFU

-20

NC

-G

nd5

6CPL

D_J

TAG

_TCK

G2

BA0

SD

RAM

_BA0

21N

C-

Gnd

78

CPL

D_J

TAG

_TD

OG

3BA1

SD

RAM

_BA1

22N

C-

Gnd

910

CPL

D_J

TAG

_TD

IG

7CAS#

SD

RAM

_CAS#

23N

C-

Gnd

1112

-G

8CS#

SD

RAM

_CS#

24N

C-

Gnd

1314

-25

DN

U-

26D

NU

-H

2A10

SD

RAM

_A10

27N

C-

H3

A1

SD

RAM

_A1

28N

C-

H7

A2

SD

RAM

_A2

29I/

O 0

NAN

D4_

IO0_

3V3

H8

A0

SD

RAM

_A0

30I/

O 1

NAN

D4_

IO1_

3V3

H9

VD

DSD

RAM

_VD

D_1

V8

31I/

O 2

NAN

D4_

IO2_

3V3

4 pi

n Po

wer

Hea

der

32I/

O 3

NAN

D4_

IO3_

3V3

Dig

ikey

: A30

513-

ND

2 Pi

n H

DR (

jum

per)

J1VSS

Gnd

33N

C-

VCC_3

V3

1D

igik

ey:

A30

511-

ndJ2

A3

SD

RAM

_A3

34N

C-

Gnd

2CPL

D_V

CC_1

V8

1J3

A5

SD

RAM

_A5

35N

C-

SD

RAM

_VD

D_1

V8

3SD

RAM

_VD

D_1

V2

J7A6

SD

RAM

_A6

36Vss

Gnd

Gnd

42

Pin

HD

R (

jum

per)

J8A4

SD

RAM

_A4

37Vcc

VCC_3

V3

Dig

ikey

: A30

511-

nd38

DN

U o

r Vss

-SD

RAM

_VD

DQ

_1

39N

C-

SD

RAM

_VD

D_1

V2

40N

C-

K2

A7

SD

RAM

_A7

41I/

0 4

NAN

D4_

IO4_

3V3

K3

A9

SD

RAM

_A9

42I/

0 5

NAN

D4_

IO5_

3V3

K7

A11

SD

RAM

_A11

43I/

0 6

NAN

D4_

IO6_

3V3

K8

A8

SD

RAM

_A8

44I/

0 7

NAN

D4_

IO7_

3V3

K9

VSS

Gnd

45N

C-

46N

C-

L1VD

DSD

RAM

_VD

D_1

V8

47N

C-

L2A12

SD

RAM

_A12

48D

NU

-L3

RFU

-L7

RFU

-47

0pF

040

2 X7R

L8RFU

-D

igik

ey:

709-

1085

-1-N

DSD

RAM

_VD

DQ

_1V8

1N

ote-

- m

ake

sure

not

to

conf

use

DQ

5 an

d D

QS

Gnd

2 470p

F 0

402

X7R

Pow

er

Dig

ikey

: 70

9-10

85-1

-ND

http

://w

ww

.qim

onda

.com

/sta

tic/d

ownl

oad/

prom

opag

es/A

N_C

D03

6_D

esig

n_G

uide

_for

_DD

R2_

rev1

00_x

2x.p

dfSD

RAM

_VD

D_1

V8

1G

nd2 47

0pF

040

2 X7R

Dig

ikey

: 70

9-10

85-1

-ND

VCC_3

V3

1G

nd2 10

0nF

040

2 X5R

D

igik

ey:

399-

3027

-1-N

DSD

RAM

_VD

DQ

_1V8

1G

nd2 10

0nF

040

2 X5R

D

igik

ey:

399-

3027

-1-N

DSD

RAM

_VD

D_1

V8

1G

nd2 10

0nF

040

2 X5R

D

igik

ey:

399-

3027

-1-N

DVCC_3

V3

1G

nd2

A t

ypic

al s

elec

tion

wou

ld c

onsi

st o

f a

470

pF,

2.7n

F, 1

0 nF

, 10

0nF,

470

nF,

and

a 1

0uF

bypa

ss c

apac

itor

from

VD

D a

nd V

DD

Q t

o G

ND

, al

ong

with

a 4

70 p

F an

d 10

0 nF

pla

ced

from

VREF

to

GN

D.

This

seq

uenc

e of

de

coup

ling

shou

ld b

e du

plic

ated

for

eac

h D

DR2

chip

on

the

boar

d. I

f bo

ard

spac

e or

cos

t is

a c

once

rn,

a si

mpl

ified

arr

ay o

f de

coup

ling

capa

cito

rs s

houl

d in

clud

e, o

f at

leas

t tw

o ca

ps

(47

0 p

F, 1

00

nF)

sh

ould

b

e u

sed

for

eac

h s

up

ply

vol

tag

e an

d V

RE.

All

cap

acit

ors

shou

ld b

e p

lace

d c

lose

to

the

dev

ice

as

pos

sib

le a

nd

bet

wee

n t

he

via

and

th

e p

ower

pin

. If

pla

ced

aft

er t

he

pow

er p

in,

the

effe

ct o

f th

e d

ecou

plin

g c

ap is

str

ong

ly r

edu

ced

. A

ll ca

pac

itor

s sh

ould

be

cera

mic

an

d s

hou

ld h

ave

an X

R5

m

ater

ial r

atin

g.

Pac

kag

e ty

pes

are

typ

ical

ly S

MD

04

02

or

06

03

.

31

DIMM Package Outline NOTE: Images not drawn to same scale.

FRONT (pin 1) - DDR - CPLD - Connector - Caps

Front clearance (component thickness allowable) - 20mm throughout

40mm

REAR (pin 2) - NAND x 4 - Caps

Rear clearance (component thickness allowable) - 1.2mm for first 30mm height - 0mm for remaining 10mm height

30mm

10mm

Silkscreen: - power and jumper pin nets - serial number of DIMM starting at 0 - label nand1 through nand4

32

A.2 Schematic5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CP

LD_J

TAG

_VC

C

CLP

D_V

CC

_1V

8

SD

RA

M_V

DD

_1V

8

VC

C_3

V3

VC

C_3

V3

SD

RA

M_V

DD

_1V

8C

LPD

_VC

C_1

V8

CP

LD_J

TAG

_VC

C

NA

ND

1_1V

8_R

B2

NA

ND

1_1V

8_R

BN

AN

D1_

1V8_

RE

NA

ND

1_1V

8_C

EN

AN

D1_

1V8_

CE

2N

AN

D1_

1V8_

CLE

NA

ND

1_1V

8_A

LEN

AN

D1_

1V8_

WE

NA

ND

1_1V

8_W

P

NA

ND

2_1V

8_R

B2

NA

ND

2_1V

8_R

BN

AN

D2_

1V8_

RE

NA

ND

2_1V

8_C

EN

AN

D2_

1V8_

CE

2N

AN

D2_

1V8_

CLE

NA

ND

2_1V

8_A

LEN

AN

D2_

1V8_

WE

NA

ND

2_1V

8_W

P

NA

ND

3_R

EN

AN

D3_

CE

NA

ND

3_C

E2

NA

ND

3_C

LEN

AN

D3_

ALE

NA

ND

3_W

EN

AN

D3_

WP

NA

ND

4_R

B2

NA

ND

4_R

BN

AN

D4_

RE

NA

ND

4_C

EN

AN

D4_

CE

2N

AN

D4_

CLE

NA

ND

4_A

LEN

AN

D4_

WE

NA

ND

4_W

P

TCK

TDI

TDO

TMS

NA

ND

1_R

EN

AN

D1_

CE

NA

ND

1_C

E2

NA

ND

1_C

LEN

AN

D1_

ALE

NA

ND

1_W

EN

AN

D1_

WP

NA

ND

2_R

B2

NA

ND

2_R

BN

AN

D2_

RE

NA

ND

2_C

EN

AN

D2_

CE

2N

AN

D2_

CLE

NA

ND

2_A

LEN

AN

D2_

WE

NA

ND

2_W

PN

AN

D3_

RB

2N

AN

D3_

RB

NA

ND

1_R

B2

NA

ND

1_R

B

NA

ND

2_IO

0N

AN

D2_

IO1

NA

ND

2_IO

2N

AN

D2_

IO3

NA

ND

2_IO

4N

AN

D2_

IO5

NA

ND

2_IO

6N

AN

D2_

IO7

NA

ND

1_IO

0N

AN

D1_

IO1

NA

ND

1_IO

2N

AN

D1_

IO3

NA

ND

1_IO

4N

AN

D1_

IO5

NA

ND

1_IO

6N

AN

D1_

IO7

NA

ND

3_IO

0N

AN

D3_

IO1

NA

ND

3_IO

2N

AN

D3_

IO3

NA

ND

3_IO

4N

AN

D3_

IO5

NA

ND

3_IO

6N

AN

D3_

IO7

NA

ND

4_IO

0N

AN

D4_

IO1

NA

ND

4_IO

2N

AN

D4_

IO3

NA

ND

4_IO

4N

AN

D4_

IO5

NA

ND

4_IO

6N

AN

D4_

IO7

NA

ND

1_1V

8_IO

0N

AN

D1_

1V8_

IO1

NA

ND

1_1V

8_IO

2N

AN

D1_

1V8_

IO3

NA

ND

1_1V

8_IO

4N

AN

D1_

1V8_

IO5

NA

ND

1_1V

8_IO

6N

AN

D1_

1V8_

IO7

NA

ND

2_1V

8_IO

0N

AN

D2_

1V8_

IO1

NA

ND

2_1V

8_IO

2N

AN

D2_

1V8_

IO3

NA

ND

2_1V

8_IO

4N

AN

D2_

1V8_

IO5

NA

ND

2_1V

8_IO

6N

AN

D2_

1V8_

IO7

NA

ND

3_1V

8_R

B2

NA

ND

3_1V

8_R

BN

AN

D3_

1V8_

RE

NA

ND

3_1V

8_C

EN

AN

D3_

1V8_

CE

2N

AN

D3_

1V8_

CLE

NA

ND

3_1V

8_A

LEN

AN

D3_

1V8_

WE

NA

ND

3_1V

8_W

PN

AN

D3_

1V8_

IO0

NA

ND

3_1V

8_IO

1N

AN

D3_

1V8_

IO2

NA

ND

3_1V

8_IO

3N

AN

D3_

1V8_

IO4

NA

ND

3_1V

8_IO

5N

AN

D3_

1V8_

IO6

NA

ND

3_1V

8_IO

7

NA

ND

4_1V

8_IO

0N

AN

D4_

1V8_

IO1

NA

ND

4_1V

8_IO

2N

AN

D4_

1V8_

IO3

NA

ND

4_1V

8_IO

4N

AN

D4_

1V8_

IO5

NA

ND

4_1V

8_IO

6N

AN

D4_

1V8_

IO7

CP

LD_R

ES

V_1

CP

LD_R

ES

V_2

CP

LD_R

ES

V_3

CP

LD_R

ES

V_4

CP

LD_R

ES

V_5

CP

LD_R

ES

V_6

CP

LD_R

ES

V_7

CP

LD_R

ES

V_8

CP

LD_R

ES

V_9

NA

ND

4_1V

8_R

B2

NA

ND

4_1V

8_R

BN

AN

D4_

1V8_

RE

NA

ND

4_1V

8_C

EN

AN

D4_

1V8_

CE

2N

AN

D4_

1V8_

CLE

NA

ND

4_1V

8_A

LEN

AN

D4_

1V8_

WE

NA

ND

4_1V

8_W

P

NA

ND

1_D

IRN

AN

D2_

DIR

NA

ND

3_D

IRN

AN

D4_

DIR

CP

LD_R

ES

V_1

0C

PLD

_RE

SV

_11

CP

LD_R

ES

V_1

2C

PLD

_RE

SV

_13

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofC

PLD

A

NA

ND

+DD

R D

IMM

B

15

Wed

nesd

ay, N

ovem

ber 0

4, 2

009

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofC

PLD

A

NA

ND

+DD

R D

IMM

B

15

Wed

nesd

ay, N

ovem

ber 0

4, 2

009

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofC

PLD

A

NA

ND

+DD

R D

IMM

B

15

Wed

nesd

ay, N

ovem

ber 0

4, 2

009

C3

100n

FC

310

0nF

C5

100n

FC

510

0nF

C11

100n

FC

1110

0nF

C10

100n

FC

1010

0nF

B5M

1R

1B

5M2

N4

B5M

3N

2B

5(G

CK

1)M

4M

3B

5M5

P1

B5(

GC

K0)

M6

M2

B5M

12L3

B5M

13N

1B

5M14

L4B

5M15

M1

B5M

16L5

B6M

1N

3B

6(C

DR

ST)

M2

P2

B6M

4P

4B

6(G

CK

2)M

4P

5B

6M5

R2

B6M

6T1

B6(

DG

E)M

12T2

B6M

13N

5B

6M14

R4

B6M

15M

5B

6M16

R5

B7M

1K

4B

7M2

L2B

7M3

K3

B7M

4L1

B7M

5K

5B

7M6

K2

B7M

11J4

B7M

12K

1B

7M13

J3B

7M14

J2B

7M15

J5B

7M16

J1B

8M1

R6

B8M

2N

6B

8M3

R3

B8M

4M

6B

8M5

T3B

8M6

P6

B8M

11T4

B8M

12P

7B

8M13

T5B

8M14

N7

B8M

15R

7B

8M16

M7

N13

M5

N15

B13

M6

M15

B13

M12

M13

B13

M13

P16

B13

M14

N16

B13

M15

L14

B13

M16

M14

B14

M1

P15

B14

M2

P14

B14

M3

P13

B14

M4

R13

B14

M5

N13

B14

M6

R14

B14

M12

T15

B14

M13

R12

B14

M14

N11

B14

M15

M11

B14

M16

N10

B15

M1

L15

B15

M2

L13

B15

M3

M12

B15

M4

M16

B15

M5

K14

B15

M6

L16

B15

M11

K15

B15

M12

L12

B15

M13

K16

B15

M14

J14

B15

M15

J15

B15

M16

J13

B16

M1

P10

B16

M2

R10

B16

M3

T10

B16

M4

R9

B16

M5

N9

B16

M6

M8

B16

M11

T8B

16M

12P

8B

16M

13R

8B

16M

14T7

B16

M15

N8

B16

M16

T6

B13

M4

R16

B13

M3

N14

B13

M2

T16

B13

M1

R15

U1A XC

2C25

6_C

oolR

unne

r-II_

CP

LD

U1A XC

2C25

6_C

oolR

unne

r-II_

CP

LD

C7

100n

FC

710

0nF

C6

100n

FC

610

0nF

VC

CA

UX

(JTA

G)

F4

VC

CP

3V

CC

D5

VC

CK

13V

CC

D12

VC

CIO

1J6

VC

CIO

1K

6V

CC

IO1

L7V

CC

IO1

L8V

CC

IO1

J11

VC

CIO

1K

11V

CC

IO1

L10

VC

CIO

1L9

VC

CIO

2F7

VC

CIO

2F8

VC

CIO

2G

6V

CC

IO2

H6

VC

CIO

2F1

0V

CC

IO2

F9V

CC

IO2

H11

GN

DF1

1G

ND

F6G

ND

G10

GN

DG

7G

ND

G8

GN

DG

9G

ND

H10

GN

DH

7G

ND

H8

GN

DH

9G

ND

J10

GN

DJ7

GN

DJ8

GN

DJ9

GN

DK

10G

ND

K7

GN

DK

8G

ND

K9

GN

DL1

1G

ND

L6

NC

A1

NC

C2

NC

E6

NC

D1

NC

E1

NC

G2

NC

F1N

CG

1N

CM

4N

CT9

NC

P9

NC

M9

NC

M10

NC

T11

NC

T12

NC

T13

NC

P11

NC

T14

NC

J16

NC

K12

NC

D16

NC

G12

NC

C15

NC

D14

NC

D6

NC

C6

NC

E7

NC

C5

U1C XC

2C25

6_C

oolR

unne

r-II_

CP

LD

U1C XC

2C25

6_C

oolR

unne

r-II_

CP

LD

C2

100n

FC

210

0nF

B1M

1B

3B

1M2

B4

B1(

GS

R)M

3C

4B

1M4

A2

B1M

5A

3B

1M6

A4

B1M

12B

5B

1M13

A5

B1M

14E

8B

1M15

B6

B1M

16C

7B

2(G

TS2)

M1

D3

B2M

2C

3B

2(G

TS3)

M3

E3

B2M

4B

2B

2(G

TS0)

M5

D4

B2M

6D

2B

2(G

TS1)

M12

E5

B2M

13B

1B

2M14

E4

B2M

15C

1B

2M16

E2

B3M

1A

6B

3M2

D7

B3M

3B

7B

3M4

E9

B3M

5A

7B

3M6

D8

B3M

12B

8B

3M13

C8

B3M

14A

8B

3M15

E11

B3M

16E

10B

4M1

F2B

4M2

F3B

4M3

G4

B4M

4G

3B

4M5

F5B

4M6

G5

B4M

12H

2B

4M13

H4

B4M

14H

3B

4M15

H1

B4M

16H

5

B9M

1B

13B

9M2

B14

B9M

3C

13B

9M4

A15

B9M

5C

12B

9M6

B12

B9M

11D

13B

9M12

A14

B9M

13E

13B

9M14

A13

B9M

15C

11B

9M16

A12

B10

M1

A16

B10

M2

B15

B10

M3

C14

B10

M4

G11

B10

M5

B16

B10

M6

D15

B10

M11

E14

B10

M12

C16

B10

M13

F14

B10

M14

F13

B10

M15

E15

B10

M16

G13

B11

M1

B11

B11

M2

D11

B11

M3

A11

B11

M4

D10

B11

M5

B10

B11

M6

E12

B11

M11

F12

B11

M12

B9

B11

M13

C9

B11

M14

C10

B11

M15

A9

B11

M16

D9

B12

M1

F15

B12

M2

G14

B12

M3

E16

B12

M4

H12

B12

M5

F16

B12

M6

H16

B12

M11

G15

B12

M12

H13

B12

M13

G16

B12

M14

H14

B12

M15

H15

B12

M16

J12

TCK

P12

TDI

R11

TDO

A10

TMS

N12

U1B XC

2C25

6_C

oolR

unne

r-II_

CP

LD

U1B XC

2C25

6_C

oolR

unne

r-II_

CP

LD

C1

100n

FC

110

0nF

C8

100n

FC

810

0nF

C9

100n

FC

910

0nF

C4

100n

FC

410

0nF

33

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SD

RA

M_V

DD

_1V

8

SD

RA

M_V

DD

_1V

8S

DR

AM

_VD

D_1

V8

SD

RA

M_V

DD

Q_1

V8

SD

RA

M_V

RE

F

SD

RA

M_V

DD

Q_1

V8

SD

RA

M_V

DD

Q_1

V8

SD

RA

M_V

RE

F

SD

RA

M_R

DQ

S#

SD

RA

M_D

QS

#

SD

RA

M_D

Q0

SD

RA

M_D

Q1

SD

RA

M_D

Q2

SD

RA

M_D

Q3

SD

RA

M_D

Q4

SD

RA

M_D

Q5

SD

RA

M_D

Q6

SD

RA

M_D

Q7

SD

RA

M_D

QS

SD

RA

M_D

M_R

DQ

S

SD

RA

M_C

K

SD

RA

M_C

KE

SD

RA

M_W

E#

SD

RA

M_R

AS

#S

DR

AM

_CK

#S

DR

AM

_OD

T

SD

RA

M_B

A0

SD

RA

M_B

A1

SD

RA

M_C

AS

#S

DR

AM

_CS

#

SD

RA

M_A

0S

DR

AM

_A1

SD

RA

M_A

2

SD

RA

M_A

3S

DR

AM

_A4

SD

RA

M_A

5

SD

RA

M_A

6

SD

RA

M_A

7S

DR

AM

_A8

SD

RA

M_A

9

SD

RA

M_A

10

SD

RA

M_A

11

SD

RA

M_A

12

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofD

DR

A

NA

ND

+DD

R D

IMM

B

25

Tues

day,

Nov

embe

r 03,

200

9

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofD

DR

A

NA

ND

+DD

R D

IMM

B

25

Tues

day,

Nov

embe

r 03,

200

9

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofD

DR

A

NA

ND

+DD

R D

IMM

B

25

Tues

day,

Nov

embe

r 03,

200

9

C18

470p

FC

1847

0pF

C21

470p

FC

2147

0pF

VD

DA

1R

DQ

S#/

NF

A2

VS

SA

3

VS

SQ

A7

DQ

S#

A8

VD

DQ

A9

DQ

6B

1V

SS

QB

2D

M/R

DQ

SB

3

DQ

SB

7V

SS

QB

8D

Q7

B9

VD

DQ

C1

DQ

1C

2V

DD

QC

3

VD

DQ

C7

VQ

0C

8V

DD

QC

9

DQ

4D

1V

SS

QD

2D

Q3

D3

DQ

2D

7V

SS

QD

8D

Q5

D9

VD

DL

E1

VR

EF

E2

VS

SE

3

VS

SD

LE

7C

KE

8V

DD

E9

CK

EF2

WE

#F3

RA

S#

F7C

K#

F8O

DT

F9

RFU

G1

BA

0G

2B

A1

G3

CA

S#

G7

CS

#G

8

A10

H2

A1

H3

A2

H7

A0

H8

VD

DH

9

VS

SJ1

A3

J2A

5J3

A6

J7A

4J8

A7

K2

A9

K3

A11

K7

A8

K8

VS

SK

9

VD

DL1

A12

L2R

FUL3

RFU

L7R

FUL8

U2 MT4

7H32

M8-

GO

OD

U2 MT4

7H32

M8-

GO

OD

C19

470p

FC

1947

0pF

C20

100n

FC

2010

0nF

C14

470p

FC

1447

0pF

C12

100n

FC

1210

0nF

C15

470p

FC

1547

0pF

C16

100n

FC

1610

0nF

C13

100n

FC

1310

0nF

C17

100n

FC

1710

0nF

34

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SD

RA

M_V

DD

_1V

8

SD

RA

M_V

RE

F

SD

RA

M_A

0S

DR

AM

_A1

SD

RA

M_A

2S

DR

AM

_A3

SD

RA

M_A

4S

DR

AM

_A5

SD

RA

M_A

6S

DR

AM

_A7

SD

RA

M_A

8S

DR

AM

_A9

SD

RA

M_A

10S

DR

AM

_A11

SD

RA

M_A

12C

PLD

_RE

SV

_5

CP

LD_R

ES

V_6

CP

LD_R

ES

V_2

CP

LD_R

ES

V_3

CP

LD_R

ES

V_1

CP

LD_R

ES

V_9

CP

LD_R

ES

V_7

CP

LD_R

ES

V_8

SD

RA

M_B

A0

SD

RA

M_B

A1

SD

RA

M_C

AS

#

SD

RA

M_C

K#

SD

RA

M_C

K

SD

RA

M_C

KE

CP

LD_R

ES

V_4

SD

RA

M_R

AS

#

SD

RA

M_C

S#

SD

RA

M_O

DT

NA

ND

1_1V

8_R

EN

AN

D2_

1V8_

RE

NA

ND

3_1V

8_C

E2

NA

ND

4_1V

8_R

EN

AN

D4_

1V8_

CLE

NA

ND

4_1V

8_W

PC

PLD

_RE

SV

_12

CP

LD_R

ES

V_1

3

NA

ND

1_1V

8_A

LEN

AN

D1_

1V8_

WP

NA

ND

2_1V

8_IO

0

NA

ND

1_1V

8_IO

0

NA

ND

1_1V

8_IO

2N

AN

D1_

1V8_

IO3

NA

ND

1_1V

8_C

LEN

AN

D1_

1V8_

WE

NA

ND

1_1V

8_IO

1N

AN

D1_

1V8_

IO6

NA

ND

1_1V

8_IO

7N

AN

D1_

1V8_

RB

2N

AN

D2_

1V8_

RB

2N

AN

D1_

1V8_

IO4

NA

ND

1_1V

8_IO

5N

AN

D1_

1V8_

RB

NA

ND

2_1V

8_R

BN

AN

D2_

1V8_

CLE

NA

ND

2_1V

8_W

E

NA

ND

2_1V

8_IO

1

NA

ND

2_1V

8_IO

2

NA

ND

2_1V

8_IO

3N

AN

D2_

1V8_

IO4

NA

ND

2_1V

8_IO

5

NA

ND

2_1V

8_IO

6

NA

ND

2_1V

8_IO

7

NA

ND

2_1V

8_A

LEN

AN

D2_

1V8_

WP

NA

ND

3_1V

8_R

B2

NA

ND

4_1V

8_R

B2

NA

ND

3_1V

8_R

BN

AN

D4_

1V8_

RB

NA

ND

3_1V

8_C

LEN

AN

D3_

1V8_

WE

NA

ND

3_1V

8_A

LEN

AN

D3_

1V8_

WP

NA

ND

3_1V

8_IO

0

NA

ND

3_1V

8_IO

1

NA

ND

3_1V

8_IO

2

NA

ND

3_1V

8_IO

3

NA

ND

3_1V

8_IO

4

NA

ND

3_1V

8_IO

5

NA

ND

3_1V

8_IO

6

NA

ND

3_1V

8_IO

7

CP

LD_R

ES

V_1

0

CP

LD_R

ES

V_1

1

NA

ND

4_1V

8_IO

0N

AN

D4_

1V8_

IO1

NA

ND

4_1V

8_IO

2

NA

ND

4_1V

8_IO

3

NA

ND

4_1V

8_IO

4

NA

ND

4_1V

8_IO

5N

AN

D4_

1V8_

IO6

NA

ND

4_1V

8_IO

7

SD

RA

M_D

Q0

SD

RA

M_D

Q2

SD

RA

M_D

Q1

SD

RA

M_D

Q3

SD

RA

M_D

Q4

SD

RA

M_D

Q5

SD

RA

M_D

Q6

SD

RA

M_D

Q7

NA

ND

1_D

IRN

AN

D2_

DIR

NA

ND

3_D

IRN

AN

D4_

DIR

NA

ND

1_1V

8_C

EN

AN

D1_

1V8_

CE

2N

AN

D2_

1V8_

CE

NA

ND

2_1V

8_C

E2

NA

ND

3_1V

8_R

EN

AN

D3_

1V8_

CE

NA

ND

4_1V

8_C

EN

AN

D4_

1V8_

CE

2N

AN

D4_

1V8_

ALE

NA

ND

4_1V

8_W

E

SD

RA

M_D

QS

#S

DR

AM

_DQ

SS

DR

AM

_RD

QS

#S

DR

AM

_DM

_RD

QS

SD

RA

M_W

E#

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofD

IMM

SO

CK

ET

A

NA

ND

+DD

R D

IMM

B

36

Wed

nesd

ay, N

ovem

ber 0

4, 2

009

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofD

IMM

SO

CK

ET

A

NA

ND

+DD

R D

IMM

B

36

Wed

nesd

ay, N

ovem

ber 0

4, 2

009

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofD

IMM

SO

CK

ET

A

NA

ND

+DD

R D

IMM

B

36

Wed

nesd

ay, N

ovem

ber 0

4, 2

009

A0

102

A1

101

A2

100

A3

99A

498

A5

97A

694

A7

92A

893

A9

91A

10/A

P10

5A

1190

A12

89A

1311

6

BA

010

7B

A1

106

BA

285

CA

S_B

113

CK

0_N

32C

KO

_P30

CK

1_N

166

CK

1_P

164

CK

E0

79C

KE

180

DM

010

DM

126

DM

252

DM

367

DM

413

0D

M5

147

DM

617

0D

M7

185

DQ

05

DQ

17

DQ

217

DQ

319

DQ

44

DQ

56

DQ

614

DQ

716

DQ

823

DQ

925

DQ

1035

DQ

1137

DQ

1220

DQ

1322

DQ

1436

DQ

1538

DQ

1643

DQ

1745

DQ

1855

DQ

1957

DQ

2044

DQ

2146

DQ

2256

DQ

2358

DQ

2461

DQ

2563

DQ

2673

DQ

2775

DQ

2862

DQ

2964

DQ

3074

DQ

3176

DQ

3212

3D

Q33

125

DQ

3413

5D

Q35

137

DQ

3612

4D

Q37

126

DQ

3813

4D

Q39

136

DQ

4014

1D

Q41

143

DQ

4215

1D

Q43

153

DQ

4414

0D

Q45

142

DQ

4615

2D

Q47

154

DQ

4815

7D

Q49

159

DQ

5017

3D

Q51

175

DQ

5215

8D

Q53

160

DQ

5417

4D

Q55

176

DQ

5617

9D

Q57

181

DQ

5818

9D

Q59

191

DQ

6018

0D

Q61

182

DQ

6219

2D

Q63

194

DQ

S0_

N11

DQ

S0_

P13

DQ

S1_

N29

DQ

S1_

P31

DQ

S2_

N49

DQ

S2_

P51

DQ

S3_

N68

DQ

S3_

P70

DQ

S4_

N12

9D

QS

4_P

131

DQ

S5_

N14

6D

QS

5_P

148

DQ

S6_

N16

7D

QS

6_P

169

DQ

S7_

N18

6D

QS

7_P

188

NC

86N

C84

NC

83

NC

120

NC

50

NC

163

NC

69

OD

T011

4O

DT1

119

RA

S_B

108

S0_

B11

0S

1_B

115

SA

019

8S

A1

200

SC

L19

7S

DA

195

WE

_B10

9

U3-

1

DIM

M-S

OC

KE

T-20

0PIN

U3-

1

DIM

M-S

OC

KE

T-20

0PIN

VS

S2

VS

S3

VS

S8

VS

S9

VS

S12

VS

S15

VS

S18

VS

S21

VS

S24

VS

S27

VS

S28

VS

S33

VS

S34

VS

S39

VS

S40

VS

S41

VS

S42

VS

S47

VS

S48

VS

S53

VS

S54

VS

S59

VS

S60

VS

S65

VS

S66

VS

S71

VS

S72

VS

S77

VS

S78

VS

S12

1V

SS

122

VS

S12

7V

SS

128

VS

S13

2V

SS

133

VS

S13

8V

SS

139

VS

S14

4V

SS

145

VS

S14

9V

SS

150

VS

S15

5V

SS

156

VS

S16

1V

SS

162

VS

S16

5V

SS

168

VS

S17

1V

SS

172

VS

S17

7V

SS

178

VS

S18

3V

SS

184

VS

S18

7V

SS

190

VS

S19

3V

SS

196

VD

D81

VD

D82

VD

D87

VD

D88

VD

D95

VD

D96

VD

D10

3V

DD

104

VD

D11

1V

DD

112

VD

D11

7V

DD

118

VD

DS

PD

199

VR

EF

1

U3-

2

DIM

M-S

OC

KE

T-20

0PIN

U3-

2

DIM

M-S

OC

KE

T-20

0PIN

35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

VC

C_3

V3

NA

ND

1_R

B2

NA

ND

1_R

BN

AN

D1_

RE

NA

ND

1_C

EN

AN

D1_

CE

2

NA

ND

1_C

LEN

AN

D1_

ALE

NA

ND

1_W

EN

AN

D1_

WP

NA

ND

1_IO

0N

AN

D1_

IO1

NA

ND

1_IO

2N

AN

D1_

IO3

NA

ND

1_IO

4N

AN

D1_

IO5

NA

ND

1_IO

6N

AN

D1_

IO7

NA

ND

2_R

B2

NA

ND

2_R

BN

AN

D2_

RE

NA

ND

2_C

EN

AN

D2_

CE

2

NA

ND

2_C

LEN

AN

D2_

ALE

NA

ND

2_W

EN

AN

D2_

WP

NA

ND

2_IO

0N

AN

D2_

IO1

NA

ND

2_IO

2N

AN

D2_

IO3

NA

ND

2_IO

4N

AN

D2_

IO5

NA

ND

2_IO

6N

AN

D2_

IO7

NA

ND

3_R

B2

NA

ND

3_R

BN

AN

D3_

RE

NA

ND

3_C

EN

AN

D3_

CE

2

NA

ND

3_C

LEN

AN

D3_

ALE

NA

ND

3_W

EN

AN

D3_

WP

NA

ND

3_IO

0N

AN

D3_

IO1

NA

ND

3_IO

2N

AN

D3_

IO3

NA

ND

3_IO

4N

AN

D3_

IO5

NA

ND

3_IO

6N

AN

D3_

IO7

NA

ND

4_IO

0N

AN

D4_

IO1

NA

ND

4_IO

2N

AN

D4_

IO3

NA

ND

4_IO

4N

AN

D4_

IO5

NA

ND

4_IO

6N

AN

D4_

IO7

NA

ND

4_R

B2

NA

ND

4_R

BN

AN

D4_

RE

NA

ND

4_C

EN

AN

D4_

CE

2

NA

ND

4_C

LEN

AN

D4_

ALE

NA

ND

4_W

EN

AN

D4_

WP

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofFl

ash

Arr

ayA

NA

ND

+DD

R D

IMM

B

45

Tues

day,

Nov

embe

r 03,

200

9

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofFl

ash

Arr

ayA

NA

ND

+DD

R D

IMM

B

45

Tues

day,

Nov

embe

r 03,

200

9

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofFl

ash

Arr

ayA

NA

ND

+DD

R D

IMM

B

45

Tues

day,

Nov

embe

r 03,

200

9

C25

100n

FC

2510

0nF

C26

100n

FC

2610

0nF

NC

1N

C2

NC

3N

C4

NC

5R

/B2#

16

R/B

#7

RE

#8

CE

#9

CE

2#1

10N

C11

VC

C12

VS

S13

NC

14N

C15

CLE

16A

LE17

WE

#18

WP

#19

NC

20N

C21

DN

U22

NC

23N

C24

DN

U/V

ss2

48N

C47

NC

46N

C45

I/O7

44I/O

643

I/O5

42I/O

441

NC

40D

NU

/Vcc

239

DN

U38

VC

C37

VS

S36

NC

35D

NU

/Vcc

234

NC

33I/O

332

I/O2

31I/O

130

I/O0

29N

C28

NC

27N

C26

DN

U/V

ss2

25

U7 NA

ND

_FLA

SH

_ME

MO

RY

U7 NA

ND

_FLA

SH

_ME

MO

RY

C22

100n

FC

2210

0nF

NC

1N

C2

NC

3N

C4

NC

5R

/B2#

16

R/B

#7

RE

#8

CE

#9

CE

2#1

10N

C11

VC

C12

VS

S13

NC

14N

C15

CLE

16A

LE17

WE

#18

WP

#19

NC

20N

C21

DN

U22

NC

23N

C24

DN

U/V

ss2

48N

C47

NC

46N

C45

I/O7

44I/O

643

I/O5

42I/O

441

NC

40D

NU

/Vcc

239

DN

U38

VC

C37

VS

S36

NC

35D

NU

/Vcc

234

NC

33I/O

332

I/O2

31I/O

130

I/O0

29N

C28

NC

27N

C26

DN

U/V

ss2

25

U6 NA

ND

_FLA

SH

_ME

MO

RY

U6 NA

ND

_FLA

SH

_ME

MO

RY

C23

100n

FC

2310

0nF

C29

100n

FC

2910

0nF

NC

1N

C2

NC

3N

C4

NC

5R

/B2#

16

R/B

#7

RE

#8

CE

#9

CE

2#1

10N

C11

VC

C12

VS

S13

NC

14N

C15

CLE

16A

LE17

WE

#18

WP

#19

NC

20N

C21

DN

U22

NC

23N

C24

DN

U/V

ss2

48N

C47

NC

46N

C45

I/O7

44I/O

643

I/O5

42I/O

441

NC

40D

NU

/Vcc

239

DN

U38

VC

C37

VS

S36

NC

35D

NU

/Vcc

234

NC

33I/O

332

I/O2

31I/O

130

I/O0

29N

C28

NC

27N

C26

DN

U/V

ss2

25

U5 NA

ND

_FLA

SH

_ME

MO

RY

U5 NA

ND

_FLA

SH

_ME

MO

RY

NC

1N

C2

NC

3N

C4

NC

5R

/B2#

16

R/B

#7

RE

#8

CE

#9

CE

2#1

10N

C11

VC

C12

VS

S13

NC

14N

C15

CLE

16A

LE17

WE

#18

WP

#19

NC

20N

C21

DN

U22

NC

23N

C24

DN

U/V

ss2

48N

C47

NC

46N

C45

I/O7

44I/O

643

I/O5

42I/O

441

NC

40D

NU

/Vcc

239

DN

U38

VC

C37

VS

S36

NC

35D

NU

/Vcc

234

NC

33I/O

332

I/O2

31I/O

130

I/O0

29N

C28

NC

27N

C26

DN

U/V

ss2

25

U4 NA

ND

_FLA

SH

_ME

MO

RY

U4 NA

ND

_FLA

SH

_ME

MO

RY

C27

100n

FC

2710

0nF

C28

100n

FC

2810

0nF

C24

100n

FC

2410

0nF

36

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CP

LD_J

TAG

_VC

CC

LPD

_VC

C_1

V8

SD

RA

M_V

DD

_1V

8

SD

RA

M_V

DD

_1V

8S

DR

AM

_VD

DQ

_1V

8

VC

C_3

V3

SD

RA

M_V

DD

_1V

8

TMS

TCK

TDO

TDI

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofM

isc.

Det

ails

A

NA

ND

+DD

R D

IMM

B

55

Tues

day,

Nov

embe

r 03,

200

9

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofM

isc.

Det

ails

A

NA

ND

+DD

R D

IMM

B

55

Tues

day,

Nov

embe

r 03,

200

9

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

ofM

isc.

Det

ails

A

NA

ND

+DD

R D

IMM

B

55

Tues

day,

Nov

embe

r 03,

200

9

JT

AG

12

J4 A30

511-

ND

J4 A30

511-

ND

12

J2 A30

511-

ND

J2 A30

511-

ND

1 3 5 7 9 11

2 4 6 8 10 1213

14

J1 S60

09-0

7-N

D

J1 S60

09-0

7-N

D

1 2 3 4

J3 A30

513-

ND

J3 A30

513-

ND

37

A.3 Placement

38

39

A.4 Layers

40

41

42

43

44

45

A.5 Silk

46

47

A.6 Final Assembly

48

49

50

A.7 End Product/Photos

Figure 13: Frontal view of the custom-fabricated SODIMM

Figure 14: Rear view of the custom-fabricated SODIMM

51

Figure 15: Xilinx LX110T board with the custom-fabricated SODIMM installed, inserted into aPCI Express x1 lane on the Gigabyte GA-G31M-ES2L motherboard

52